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19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/jiffies.h>
23#include <linux/memblock.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_pci.h>
29#include <linux/pci.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32
33#define PCIECORE_CTLANDSTATUS 0x50
34#define PIM1_1L 0x80
35#define IBAR2 0x98
36#define IR2MSK 0x9c
37#define PIM2_1L 0xa0
38#define IBAR3L 0xb4
39#define IR3MSKL 0xbc
40#define PIM3_1L 0xc4
41#define OMR1BARL 0x100
42#define OMR2BARL 0x118
43#define OMR3BARL 0x130
44#define CFGBARL 0x154
45#define CFGBARH 0x158
46#define CFGCTL 0x15c
47#define RTDID 0x160
48#define BRIDGE_CFG_0 0x2000
49#define BRIDGE_CFG_4 0x2010
50#define BRIDGE_STATUS_0 0x2600
51
52#define LINK_UP_MASK 0x00000100
53#define AXI_EP_CFG_ACCESS 0x10000
54#define EN_COHERENCY 0xF0000000
55#define EN_REG 0x00000001
56#define OB_LO_IO 0x00000002
57#define XGENE_PCIE_VENDORID 0x10E8
58#define XGENE_PCIE_DEVICEID 0xE004
59#define SZ_1T (SZ_1G*1024ULL)
60#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
61
62struct xgene_pcie_port {
63 struct device_node *node;
64 struct device *dev;
65 struct clk *clk;
66 void __iomem *csr_base;
67 void __iomem *cfg_base;
68 unsigned long cfg_addr;
69 bool link_up;
70};
71
72static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
73{
74 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
75}
76
77
78
79
80
81static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
82{
83 struct xgene_pcie_port *port = bus->sysdata;
84
85 if (bus->number >= (bus->primary + 1))
86 return port->cfg_base + AXI_EP_CFG_ACCESS;
87
88 return port->cfg_base;
89}
90
91
92
93
94
95static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
96{
97 struct xgene_pcie_port *port = bus->sysdata;
98 unsigned int b, d, f;
99 u32 rtdid_val = 0;
100
101 b = bus->number;
102 d = PCI_SLOT(devfn);
103 f = PCI_FUNC(devfn);
104
105 if (!pci_is_root_bus(bus))
106 rtdid_val = (b << 8) | (d << 3) | f;
107
108 writel(rtdid_val, port->csr_base + RTDID);
109
110 readl(port->csr_base + RTDID);
111}
112
113
114
115
116
117
118
119
120
121static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
122{
123 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
124 (offset == PCI_BASE_ADDRESS_1)))
125 return true;
126
127 return false;
128}
129
130static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
131 int offset)
132{
133 struct xgene_pcie_port *port = bus->sysdata;
134
135 if ((pci_is_root_bus(bus) && devfn != 0) || !port->link_up ||
136 xgene_pcie_hide_rc_bars(bus, offset))
137 return NULL;
138
139 xgene_pcie_set_rtdid_reg(bus, devfn);
140 return xgene_pcie_get_cfg_base(bus) + offset;
141}
142
143static struct pci_ops xgene_pcie_ops = {
144 .map_bus = xgene_pcie_map_bus,
145 .read = pci_generic_config_read32,
146 .write = pci_generic_config_write32,
147};
148
149static u64 xgene_pcie_set_ib_mask(void __iomem *csr_base, u32 addr,
150 u32 flags, u64 size)
151{
152 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
153 u32 val32 = 0;
154 u32 val;
155
156 val32 = readl(csr_base + addr);
157 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
158 writel(val, csr_base + addr);
159
160 val32 = readl(csr_base + addr + 0x04);
161 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
162 writel(val, csr_base + addr + 0x04);
163
164 val32 = readl(csr_base + addr + 0x04);
165 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
166 writel(val, csr_base + addr + 0x04);
167
168 val32 = readl(csr_base + addr + 0x08);
169 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
170 writel(val, csr_base + addr + 0x08);
171
172 return mask;
173}
174
175static void xgene_pcie_linkup(struct xgene_pcie_port *port,
176 u32 *lanes, u32 *speed)
177{
178 void __iomem *csr_base = port->csr_base;
179 u32 val32;
180
181 port->link_up = false;
182 val32 = readl(csr_base + PCIECORE_CTLANDSTATUS);
183 if (val32 & LINK_UP_MASK) {
184 port->link_up = true;
185 *speed = PIPE_PHY_RATE_RD(val32);
186 val32 = readl(csr_base + BRIDGE_STATUS_0);
187 *lanes = val32 >> 26;
188 }
189}
190
191static int xgene_pcie_init_port(struct xgene_pcie_port *port)
192{
193 int rc;
194
195 port->clk = clk_get(port->dev, NULL);
196 if (IS_ERR(port->clk)) {
197 dev_err(port->dev, "clock not available\n");
198 return -ENODEV;
199 }
200
201 rc = clk_prepare_enable(port->clk);
202 if (rc) {
203 dev_err(port->dev, "clock enable failed\n");
204 return rc;
205 }
206
207 return 0;
208}
209
210static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
211 struct platform_device *pdev)
212{
213 struct resource *res;
214
215 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
216 port->csr_base = devm_ioremap_resource(port->dev, res);
217 if (IS_ERR(port->csr_base))
218 return PTR_ERR(port->csr_base);
219
220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
221 port->cfg_base = devm_ioremap_resource(port->dev, res);
222 if (IS_ERR(port->cfg_base))
223 return PTR_ERR(port->cfg_base);
224 port->cfg_addr = res->start;
225
226 return 0;
227}
228
229static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
230 struct resource *res, u32 offset,
231 u64 cpu_addr, u64 pci_addr)
232{
233 void __iomem *base = port->csr_base + offset;
234 resource_size_t size = resource_size(res);
235 u64 restype = resource_type(res);
236 u64 mask = 0;
237 u32 min_size;
238 u32 flag = EN_REG;
239
240 if (restype == IORESOURCE_MEM) {
241 min_size = SZ_128M;
242 } else {
243 min_size = 128;
244 flag |= OB_LO_IO;
245 }
246
247 if (size >= min_size)
248 mask = ~(size - 1) | flag;
249 else
250 dev_warn(port->dev, "res size 0x%llx less than minimum 0x%x\n",
251 (u64)size, min_size);
252
253 writel(lower_32_bits(cpu_addr), base);
254 writel(upper_32_bits(cpu_addr), base + 0x04);
255 writel(lower_32_bits(mask), base + 0x08);
256 writel(upper_32_bits(mask), base + 0x0c);
257 writel(lower_32_bits(pci_addr), base + 0x10);
258 writel(upper_32_bits(pci_addr), base + 0x14);
259}
260
261static void xgene_pcie_setup_cfg_reg(void __iomem *csr_base, u64 addr)
262{
263 writel(lower_32_bits(addr), csr_base + CFGBARL);
264 writel(upper_32_bits(addr), csr_base + CFGBARH);
265 writel(EN_REG, csr_base + CFGCTL);
266}
267
268static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
269 struct list_head *res,
270 resource_size_t io_base)
271{
272 struct resource_entry *window;
273 struct device *dev = port->dev;
274 int ret;
275
276 resource_list_for_each_entry(window, res) {
277 struct resource *res = window->res;
278 u64 restype = resource_type(res);
279
280 dev_dbg(port->dev, "%pR\n", res);
281
282 switch (restype) {
283 case IORESOURCE_IO:
284 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
285 res->start - window->offset);
286 ret = pci_remap_iospace(res, io_base);
287 if (ret < 0)
288 return ret;
289 break;
290 case IORESOURCE_MEM:
291 xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start,
292 res->start - window->offset);
293 break;
294 case IORESOURCE_BUS:
295 break;
296 default:
297 dev_err(dev, "invalid resource %pR\n", res);
298 return -EINVAL;
299 }
300 }
301 xgene_pcie_setup_cfg_reg(port->csr_base, port->cfg_addr);
302
303 return 0;
304}
305
306static void xgene_pcie_setup_pims(void *addr, u64 pim, u64 size)
307{
308 writel(lower_32_bits(pim), addr);
309 writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04);
310 writel(lower_32_bits(size), addr + 0x10);
311 writel(upper_32_bits(size), addr + 0x14);
312}
313
314
315
316
317
318static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
319{
320 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
321 *ib_reg_mask |= (1 << 1);
322 return 1;
323 }
324
325 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
326 *ib_reg_mask |= (1 << 0);
327 return 0;
328 }
329
330 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
331 *ib_reg_mask |= (1 << 2);
332 return 2;
333 }
334
335 return -EINVAL;
336}
337
338static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
339 struct of_pci_range *range, u8 *ib_reg_mask)
340{
341 void __iomem *csr_base = port->csr_base;
342 void __iomem *cfg_base = port->cfg_base;
343 void *bar_addr;
344 void *pim_addr;
345 u64 cpu_addr = range->cpu_addr;
346 u64 pci_addr = range->pci_addr;
347 u64 size = range->size;
348 u64 mask = ~(size - 1) | EN_REG;
349 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
350 u32 bar_low;
351 int region;
352
353 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
354 if (region < 0) {
355 dev_warn(port->dev, "invalid pcie dma-range config\n");
356 return;
357 }
358
359 if (range->flags & IORESOURCE_PREFETCH)
360 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
361
362 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
363 switch (region) {
364 case 0:
365 xgene_pcie_set_ib_mask(csr_base, BRIDGE_CFG_4, flags, size);
366 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
367 writel(bar_low, bar_addr);
368 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
369 pim_addr = csr_base + PIM1_1L;
370 break;
371 case 1:
372 bar_addr = csr_base + IBAR2;
373 writel(bar_low, bar_addr);
374 writel(lower_32_bits(mask), csr_base + IR2MSK);
375 pim_addr = csr_base + PIM2_1L;
376 break;
377 case 2:
378 bar_addr = csr_base + IBAR3L;
379 writel(bar_low, bar_addr);
380 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
381 writel(lower_32_bits(mask), csr_base + IR3MSKL);
382 writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4);
383 pim_addr = csr_base + PIM3_1L;
384 break;
385 }
386
387 xgene_pcie_setup_pims(pim_addr, pci_addr, ~(size - 1));
388}
389
390static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
391 struct device_node *node)
392{
393 const int na = 3, ns = 2;
394 int rlen;
395
396 parser->node = node;
397 parser->pna = of_n_addr_cells(node);
398 parser->np = parser->pna + na + ns;
399
400 parser->range = of_get_property(node, "dma-ranges", &rlen);
401 if (!parser->range)
402 return -ENOENT;
403 parser->end = parser->range + rlen / sizeof(__be32);
404
405 return 0;
406}
407
408static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
409{
410 struct device_node *np = port->node;
411 struct of_pci_range range;
412 struct of_pci_range_parser parser;
413 struct device *dev = port->dev;
414 u8 ib_reg_mask = 0;
415
416 if (pci_dma_range_parser_init(&parser, np)) {
417 dev_err(dev, "missing dma-ranges property\n");
418 return -EINVAL;
419 }
420
421
422 for_each_of_pci_range(&parser, &range) {
423 u64 end = range.cpu_addr + range.size - 1;
424
425 dev_dbg(port->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
426 range.flags, range.cpu_addr, end, range.pci_addr);
427 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
428 }
429 return 0;
430}
431
432
433static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
434{
435 int i;
436
437 for (i = PIM1_1L; i <= CFGCTL; i += 4)
438 writel(0x0, port->csr_base + i);
439}
440
441static int xgene_pcie_setup(struct xgene_pcie_port *port,
442 struct list_head *res,
443 resource_size_t io_base)
444{
445 u32 val, lanes = 0, speed = 0;
446 int ret;
447
448 xgene_pcie_clear_config(port);
449
450
451 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
452 writel(val, port->csr_base + BRIDGE_CFG_0);
453
454 ret = xgene_pcie_map_ranges(port, res, io_base);
455 if (ret)
456 return ret;
457
458 ret = xgene_pcie_parse_map_dma_ranges(port);
459 if (ret)
460 return ret;
461
462 xgene_pcie_linkup(port, &lanes, &speed);
463 if (!port->link_up)
464 dev_info(port->dev, "(rc) link down\n");
465 else
466 dev_info(port->dev, "(rc) x%d gen-%d link up\n",
467 lanes, speed + 1);
468 return 0;
469}
470
471static int xgene_pcie_probe_bridge(struct platform_device *pdev)
472{
473 struct device_node *dn = pdev->dev.of_node;
474 struct xgene_pcie_port *port;
475 resource_size_t iobase = 0;
476 struct pci_bus *bus;
477 int ret;
478 LIST_HEAD(res);
479
480 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
481 if (!port)
482 return -ENOMEM;
483 port->node = of_node_get(pdev->dev.of_node);
484 port->dev = &pdev->dev;
485
486 ret = xgene_pcie_map_reg(port, pdev);
487 if (ret)
488 return ret;
489
490 ret = xgene_pcie_init_port(port);
491 if (ret)
492 return ret;
493
494 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
495 if (ret)
496 return ret;
497
498 ret = xgene_pcie_setup(port, &res, iobase);
499 if (ret)
500 return ret;
501
502 bus = pci_create_root_bus(&pdev->dev, 0,
503 &xgene_pcie_ops, port, &res);
504 if (!bus)
505 return -ENOMEM;
506
507 pci_scan_child_bus(bus);
508 pci_assign_unassigned_bus_resources(bus);
509 pci_bus_add_devices(bus);
510
511 platform_set_drvdata(pdev, port);
512 return 0;
513}
514
515static const struct of_device_id xgene_pcie_match_table[] = {
516 {.compatible = "apm,xgene-pcie",},
517 {},
518};
519
520static struct platform_driver xgene_pcie_driver = {
521 .driver = {
522 .name = "xgene-pcie",
523 .of_match_table = of_match_ptr(xgene_pcie_match_table),
524 },
525 .probe = xgene_pcie_probe_bridge,
526};
527module_platform_driver(xgene_pcie_driver);
528
529MODULE_AUTHOR("Tanmay Inamdar <tinamdar@apm.com>");
530MODULE_DESCRIPTION("APM X-Gene PCIe driver");
531MODULE_LICENSE("GPL v2");
532
