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13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#define PA_BASE 0
20#define PB_BASE 32
21#define PC_BASE 64
22#define PD_BASE 96
23#define PE_BASE 128
24#define PF_BASE 160
25#define PG_BASE 192
26#define PH_BASE 224
27#define PI_BASE 256
28#define PL_BASE 352
29#define PM_BASE 384
30#define PN_BASE 416
31
32#define SUNXI_PINCTRL_PIN(bank, pin) \
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34
35#define SUNXI_PIN_NAME_MAX_LEN 5
36
37#define BANK_MEM_SIZE 0x24
38#define MUX_REGS_OFFSET 0x0
39#define DATA_REGS_OFFSET 0x10
40#define DLEVEL_REGS_OFFSET 0x14
41#define PULL_REGS_OFFSET 0x1c
42
43#define PINS_PER_BANK 32
44#define MUX_PINS_PER_REG 8
45#define MUX_PINS_BITS 4
46#define MUX_PINS_MASK 0x0f
47#define DATA_PINS_PER_REG 32
48#define DATA_PINS_BITS 1
49#define DATA_PINS_MASK 0x01
50#define DLEVEL_PINS_PER_REG 16
51#define DLEVEL_PINS_BITS 2
52#define DLEVEL_PINS_MASK 0x03
53#define PULL_PINS_PER_REG 16
54#define PULL_PINS_BITS 2
55#define PULL_PINS_MASK 0x03
56
57#define IRQ_PER_BANK 32
58
59#define IRQ_CFG_REG 0x200
60#define IRQ_CFG_IRQ_PER_REG 8
61#define IRQ_CFG_IRQ_BITS 4
62#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
63#define IRQ_CTRL_REG 0x210
64#define IRQ_CTRL_IRQ_PER_REG 32
65#define IRQ_CTRL_IRQ_BITS 1
66#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
67#define IRQ_STATUS_REG 0x214
68#define IRQ_STATUS_IRQ_PER_REG 32
69#define IRQ_STATUS_IRQ_BITS 1
70#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
71
72#define IRQ_MEM_SIZE 0x20
73
74#define IRQ_EDGE_RISING 0x00
75#define IRQ_EDGE_FALLING 0x01
76#define IRQ_LEVEL_HIGH 0x02
77#define IRQ_LEVEL_LOW 0x03
78#define IRQ_EDGE_BOTH 0x04
79
80#define SUN4I_FUNC_INPUT 0
81#define SUN4I_FUNC_IRQ 6
82
83struct sunxi_desc_function {
84 const char *name;
85 u8 muxval;
86 u8 irqbank;
87 u8 irqnum;
88};
89
90struct sunxi_desc_pin {
91 struct pinctrl_pin_desc pin;
92 struct sunxi_desc_function *functions;
93};
94
95struct sunxi_pinctrl_desc {
96 const struct sunxi_desc_pin *pins;
97 int npins;
98 unsigned pin_base;
99 unsigned irq_banks;
100 bool irq_read_needs_mux;
101};
102
103struct sunxi_pinctrl_function {
104 const char *name;
105 const char **groups;
106 unsigned ngroups;
107};
108
109struct sunxi_pinctrl_group {
110 const char *name;
111 unsigned long config;
112 unsigned pin;
113};
114
115struct sunxi_pinctrl {
116 void __iomem *membase;
117 struct gpio_chip *chip;
118 const struct sunxi_pinctrl_desc *desc;
119 struct device *dev;
120 struct irq_domain *domain;
121 struct sunxi_pinctrl_function *functions;
122 unsigned nfunctions;
123 struct sunxi_pinctrl_group *groups;
124 unsigned ngroups;
125 int *irq;
126 unsigned *irq_array;
127 spinlock_t lock;
128 struct pinctrl_dev *pctl_dev;
129};
130
131#define SUNXI_PIN(_pin, ...) \
132 { \
133 .pin = _pin, \
134 .functions = (struct sunxi_desc_function[]){ \
135 __VA_ARGS__, { } }, \
136 }
137
138#define SUNXI_FUNCTION(_val, _name) \
139 { \
140 .name = _name, \
141 .muxval = _val, \
142 }
143
144#define SUNXI_FUNCTION_IRQ(_val, _irq) \
145 { \
146 .name = "irq", \
147 .muxval = _val, \
148 .irqnum = _irq, \
149 }
150
151#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
152 { \
153 .name = "irq", \
154 .muxval = _val, \
155 .irqbank = _bank, \
156 .irqnum = _irq, \
157 }
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175
176static inline u32 sunxi_mux_reg(u16 pin)
177{
178 u8 bank = pin / PINS_PER_BANK;
179 u32 offset = bank * BANK_MEM_SIZE;
180 offset += MUX_REGS_OFFSET;
181 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
182 return round_down(offset, 4);
183}
184
185static inline u32 sunxi_mux_offset(u16 pin)
186{
187 u32 pin_num = pin % MUX_PINS_PER_REG;
188 return pin_num * MUX_PINS_BITS;
189}
190
191static inline u32 sunxi_data_reg(u16 pin)
192{
193 u8 bank = pin / PINS_PER_BANK;
194 u32 offset = bank * BANK_MEM_SIZE;
195 offset += DATA_REGS_OFFSET;
196 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
197 return round_down(offset, 4);
198}
199
200static inline u32 sunxi_data_offset(u16 pin)
201{
202 u32 pin_num = pin % DATA_PINS_PER_REG;
203 return pin_num * DATA_PINS_BITS;
204}
205
206static inline u32 sunxi_dlevel_reg(u16 pin)
207{
208 u8 bank = pin / PINS_PER_BANK;
209 u32 offset = bank * BANK_MEM_SIZE;
210 offset += DLEVEL_REGS_OFFSET;
211 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
212 return round_down(offset, 4);
213}
214
215static inline u32 sunxi_dlevel_offset(u16 pin)
216{
217 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
218 return pin_num * DLEVEL_PINS_BITS;
219}
220
221static inline u32 sunxi_pull_reg(u16 pin)
222{
223 u8 bank = pin / PINS_PER_BANK;
224 u32 offset = bank * BANK_MEM_SIZE;
225 offset += PULL_REGS_OFFSET;
226 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
227 return round_down(offset, 4);
228}
229
230static inline u32 sunxi_pull_offset(u16 pin)
231{
232 u32 pin_num = pin % PULL_PINS_PER_REG;
233 return pin_num * PULL_PINS_BITS;
234}
235
236static inline u32 sunxi_irq_cfg_reg(u16 irq)
237{
238 u8 bank = irq / IRQ_PER_BANK;
239 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
240
241 return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
242}
243
244static inline u32 sunxi_irq_cfg_offset(u16 irq)
245{
246 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
247 return irq_num * IRQ_CFG_IRQ_BITS;
248}
249
250static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
251{
252 return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
253}
254
255static inline u32 sunxi_irq_ctrl_reg(u16 irq)
256{
257 u8 bank = irq / IRQ_PER_BANK;
258
259 return sunxi_irq_ctrl_reg_from_bank(bank);
260}
261
262static inline u32 sunxi_irq_ctrl_offset(u16 irq)
263{
264 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
265 return irq_num * IRQ_CTRL_IRQ_BITS;
266}
267
268static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
269{
270 return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
271}
272
273static inline u32 sunxi_irq_status_reg(u16 irq)
274{
275 u8 bank = irq / IRQ_PER_BANK;
276
277 return sunxi_irq_status_reg_from_bank(bank);
278}
279
280static inline u32 sunxi_irq_status_offset(u16 irq)
281{
282 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
283 return irq_num * IRQ_STATUS_IRQ_BITS;
284}
285
286int sunxi_pinctrl_init(struct platform_device *pdev,
287 const struct sunxi_pinctrl_desc *desc);
288
289#endif
290
