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30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/interrupt.h>
33
34#include "../comedidev.h"
35
36#include "comedi_fc.h"
37
38
39
40
41
42
43
44#define NI6527_DI_REG(x) (0x00 + (x))
45#define NI6527_DO_REG(x) (0x03 + (x))
46#define NI6527_ID_REG 0x06
47#define NI6527_CLR_REG 0x07
48#define NI6527_CLR_EDGE (1 << 3)
49#define NI6527_CLR_OVERFLOW (1 << 2)
50#define NI6527_CLR_FILT (1 << 1)
51#define NI6527_CLR_INTERVAL (1 << 0)
52#define NI6527_CLR_IRQS (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
53#define NI6527_CLR_RESET_FILT (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
54#define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
55#define NI6527_FILT_ENA_REG(x) (0x0c + (x))
56#define NI6527_STATUS_REG 0x14
57#define NI6527_STATUS_IRQ (1 << 2)
58#define NI6527_STATUS_OVERFLOW (1 << 1)
59#define NI6527_STATUS_EDGE (1 << 0)
60#define NI6527_CTRL_REG 0x15
61#define NI6527_CTRL_FALLING (1 << 4)
62#define NI6527_CTRL_RISING (1 << 3)
63#define NI6527_CTRL_IRQ (1 << 2)
64#define NI6527_CTRL_OVERFLOW (1 << 1)
65#define NI6527_CTRL_EDGE (1 << 0)
66#define NI6527_CTRL_DISABLE_IRQS 0
67#define NI6527_CTRL_ENABLE_IRQS (NI6527_CTRL_FALLING | \
68 NI6527_CTRL_RISING | \
69 NI6527_CTRL_IRQ | NI6527_CTRL_EDGE)
70#define NI6527_RISING_EDGE_REG(x) (0x18 + (x))
71#define NI6527_FALLING_EDGE_REG(x) (0x20 + (x))
72
73enum ni6527_boardid {
74 BOARD_PCI6527,
75 BOARD_PXI6527,
76};
77
78struct ni6527_board {
79 const char *name;
80};
81
82static const struct ni6527_board ni6527_boards[] = {
83 [BOARD_PCI6527] = {
84 .name = "pci-6527",
85 },
86 [BOARD_PXI6527] = {
87 .name = "pxi-6527",
88 },
89};
90
91struct ni6527_private {
92 unsigned int filter_interval;
93 unsigned int filter_enable;
94};
95
96static void ni6527_set_filter_interval(struct comedi_device *dev,
97 unsigned int val)
98{
99 struct ni6527_private *devpriv = dev->private;
100
101 if (val != devpriv->filter_interval) {
102 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0));
103 writeb((val >> 8) & 0xff,
104 dev->mmio + NI6527_FILT_INTERVAL_REG(1));
105 writeb((val >> 16) & 0x0f,
106 dev->mmio + NI6527_FILT_INTERVAL_REG(2));
107
108 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG);
109
110 devpriv->filter_interval = val;
111 }
112}
113
114static void ni6527_set_filter_enable(struct comedi_device *dev,
115 unsigned int val)
116{
117 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0));
118 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1));
119 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2));
120}
121
122static int ni6527_di_insn_config(struct comedi_device *dev,
123 struct comedi_subdevice *s,
124 struct comedi_insn *insn,
125 unsigned int *data)
126{
127 struct ni6527_private *devpriv = dev->private;
128 unsigned int chan = CR_CHAN(insn->chanspec);
129 unsigned int interval;
130
131 switch (data[0]) {
132 case INSN_CONFIG_FILTER:
133
134
135
136
137
138 interval = (data[1] + 100) / 200;
139 data[1] = interval * 200;
140
141 if (interval) {
142 ni6527_set_filter_interval(dev, interval);
143 devpriv->filter_enable |= 1 << chan;
144 } else {
145 devpriv->filter_enable &= ~(1 << chan);
146 }
147 ni6527_set_filter_enable(dev, devpriv->filter_enable);
148 break;
149 default:
150 return -EINVAL;
151 }
152
153 return insn->n;
154}
155
156static int ni6527_di_insn_bits(struct comedi_device *dev,
157 struct comedi_subdevice *s,
158 struct comedi_insn *insn,
159 unsigned int *data)
160{
161 unsigned int val;
162
163 val = readb(dev->mmio + NI6527_DI_REG(0));
164 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8);
165 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16);
166
167 data[1] = val;
168
169 return insn->n;
170}
171
172static int ni6527_do_insn_bits(struct comedi_device *dev,
173 struct comedi_subdevice *s,
174 struct comedi_insn *insn,
175 unsigned int *data)
176{
177 unsigned int mask;
178
179 mask = comedi_dio_update_state(s, data);
180 if (mask) {
181
182 unsigned int val = s->state ^ 0xffffff;
183
184 if (mask & 0x0000ff)
185 writeb(val & 0xff, dev->mmio + NI6527_DO_REG(0));
186 if (mask & 0x00ff00)
187 writeb((val >> 8) & 0xff,
188 dev->mmio + NI6527_DO_REG(1));
189 if (mask & 0xff0000)
190 writeb((val >> 16) & 0xff,
191 dev->mmio + NI6527_DO_REG(2));
192 }
193
194 data[1] = s->state;
195
196 return insn->n;
197}
198
199static irqreturn_t ni6527_interrupt(int irq, void *d)
200{
201 struct comedi_device *dev = d;
202 struct comedi_subdevice *s = dev->read_subdev;
203 unsigned int status;
204
205 status = readb(dev->mmio + NI6527_STATUS_REG);
206 if (!(status & NI6527_STATUS_IRQ))
207 return IRQ_NONE;
208
209 if (status & NI6527_STATUS_EDGE) {
210 comedi_buf_write_samples(s, &s->state, 1);
211 comedi_handle_events(dev, s);
212 }
213
214 writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
215
216 return IRQ_HANDLED;
217}
218
219static int ni6527_intr_cmdtest(struct comedi_device *dev,
220 struct comedi_subdevice *s,
221 struct comedi_cmd *cmd)
222{
223 int err = 0;
224
225
226
227 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
228 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_OTHER);
229 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
230 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
231 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT);
232
233 if (err)
234 return 1;
235
236
237
238
239
240
241 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
242 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
243 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
244 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
245 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
246
247 if (err)
248 return 3;
249
250
251
252
253
254 return 0;
255}
256
257static int ni6527_intr_cmd(struct comedi_device *dev,
258 struct comedi_subdevice *s)
259{
260 writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
261 writeb(NI6527_CTRL_ENABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
262
263 return 0;
264}
265
266static int ni6527_intr_cancel(struct comedi_device *dev,
267 struct comedi_subdevice *s)
268{
269 writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
270
271 return 0;
272}
273
274static int ni6527_intr_insn_bits(struct comedi_device *dev,
275 struct comedi_subdevice *s,
276 struct comedi_insn *insn, unsigned int *data)
277{
278 data[1] = 0;
279 return insn->n;
280}
281
282static void ni6527_set_edge_detection(struct comedi_device *dev,
283 unsigned int mask,
284 unsigned int rising,
285 unsigned int falling)
286{
287 unsigned int i;
288
289 rising &= mask;
290 falling &= mask;
291 for (i = 0; i < 2; i++) {
292 if (mask & 0xff) {
293 if (~mask & 0xff) {
294
295 rising |= readb(dev->mmio +
296 NI6527_RISING_EDGE_REG(i)) &
297 (~mask & 0xff);
298
299 falling |= readb(dev->mmio +
300 NI6527_FALLING_EDGE_REG(i)) &
301 (~mask & 0xff);
302 }
303
304 writeb(rising & 0xff,
305 dev->mmio + NI6527_RISING_EDGE_REG(i));
306
307 writeb(falling & 0xff,
308 dev->mmio + NI6527_FALLING_EDGE_REG(i));
309 }
310 rising >>= 8;
311 falling >>= 8;
312 mask >>= 8;
313 }
314}
315
316static int ni6527_intr_insn_config(struct comedi_device *dev,
317 struct comedi_subdevice *s,
318 struct comedi_insn *insn,
319 unsigned int *data)
320{
321 unsigned int mask = 0xffffffff;
322 unsigned int rising, falling, shift;
323
324 switch (data[0]) {
325 case INSN_CONFIG_CHANGE_NOTIFY:
326
327 if (insn->n != 3)
328 return -EINVAL;
329 rising = data[1];
330 falling = data[2];
331 ni6527_set_edge_detection(dev, mask, rising, falling);
332 break;
333 case INSN_CONFIG_DIGITAL_TRIG:
334
335 if (data[1] != 0)
336 return -EINVAL;
337
338 switch (data[2]) {
339 case COMEDI_DIGITAL_TRIG_DISABLE:
340 rising = 0;
341 falling = 0;
342 break;
343 case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
344
345 shift = data[3];
346 if (shift >= s->n_chan) {
347 mask = 0;
348 rising = 0;
349 falling = 0;
350 } else {
351 mask <<= shift;
352 rising = data[4] << shift;
353 falling = data[5] << shift;
354 }
355 break;
356 default:
357 return -EINVAL;
358 }
359 ni6527_set_edge_detection(dev, mask, rising, falling);
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 return insn->n;
366}
367
368static void ni6527_reset(struct comedi_device *dev)
369{
370
371 ni6527_set_filter_enable(dev, 0);
372
373
374 ni6527_set_edge_detection(dev, 0xffffffff, 0, 0);
375
376 writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
377 dev->mmio + NI6527_CLR_REG);
378 writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
379}
380
381static int ni6527_auto_attach(struct comedi_device *dev,
382 unsigned long context)
383{
384 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
385 const struct ni6527_board *board = NULL;
386 struct ni6527_private *devpriv;
387 struct comedi_subdevice *s;
388 int ret;
389
390 if (context < ARRAY_SIZE(ni6527_boards))
391 board = &ni6527_boards[context];
392 if (!board)
393 return -ENODEV;
394 dev->board_ptr = board;
395 dev->board_name = board->name;
396
397 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
398 if (!devpriv)
399 return -ENOMEM;
400
401 ret = comedi_pci_enable(dev);
402 if (ret)
403 return ret;
404
405 dev->mmio = pci_ioremap_bar(pcidev, 1);
406 if (!dev->mmio)
407 return -ENOMEM;
408
409
410 if (readb(dev->mmio + NI6527_ID_REG) != 0x27)
411 return -ENODEV;
412
413 ni6527_reset(dev);
414
415 ret = request_irq(pcidev->irq, ni6527_interrupt, IRQF_SHARED,
416 dev->board_name, dev);
417 if (ret == 0)
418 dev->irq = pcidev->irq;
419
420 ret = comedi_alloc_subdevices(dev, 3);
421 if (ret)
422 return ret;
423
424
425 s = &dev->subdevices[0];
426 s->type = COMEDI_SUBD_DI;
427 s->subdev_flags = SDF_READABLE;
428 s->n_chan = 24;
429 s->maxdata = 1;
430 s->range_table = &range_digital;
431 s->insn_config = ni6527_di_insn_config;
432 s->insn_bits = ni6527_di_insn_bits;
433
434
435 s = &dev->subdevices[1];
436 s->type = COMEDI_SUBD_DO;
437 s->subdev_flags = SDF_WRITABLE;
438 s->n_chan = 24;
439 s->maxdata = 1;
440 s->range_table = &range_digital;
441 s->insn_bits = ni6527_do_insn_bits;
442
443
444 s = &dev->subdevices[2];
445 if (dev->irq) {
446 dev->read_subdev = s;
447 s->type = COMEDI_SUBD_DI;
448 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
449 s->n_chan = 1;
450 s->maxdata = 1;
451 s->range_table = &range_digital;
452 s->insn_config = ni6527_intr_insn_config;
453 s->insn_bits = ni6527_intr_insn_bits;
454 s->len_chanlist = 1;
455 s->do_cmdtest = ni6527_intr_cmdtest;
456 s->do_cmd = ni6527_intr_cmd;
457 s->cancel = ni6527_intr_cancel;
458 } else {
459 s->type = COMEDI_SUBD_UNUSED;
460 }
461
462 return 0;
463}
464
465static void ni6527_detach(struct comedi_device *dev)
466{
467 if (dev->mmio)
468 ni6527_reset(dev);
469 comedi_pci_detach(dev);
470}
471
472static struct comedi_driver ni6527_driver = {
473 .driver_name = "ni_6527",
474 .module = THIS_MODULE,
475 .auto_attach = ni6527_auto_attach,
476 .detach = ni6527_detach,
477};
478
479static int ni6527_pci_probe(struct pci_dev *dev,
480 const struct pci_device_id *id)
481{
482 return comedi_pci_auto_config(dev, &ni6527_driver, id->driver_data);
483}
484
485static const struct pci_device_id ni6527_pci_table[] = {
486 { PCI_VDEVICE(NI, 0x2b10), BOARD_PXI6527 },
487 { PCI_VDEVICE(NI, 0x2b20), BOARD_PCI6527 },
488 { 0 }
489};
490MODULE_DEVICE_TABLE(pci, ni6527_pci_table);
491
492static struct pci_driver ni6527_pci_driver = {
493 .name = "ni_6527",
494 .id_table = ni6527_pci_table,
495 .probe = ni6527_pci_probe,
496 .remove = comedi_pci_auto_unconfig,
497};
498module_comedi_pci_driver(ni6527_driver, ni6527_pci_driver);
499
500MODULE_AUTHOR("Comedi http://www.comedi.org");
501MODULE_DESCRIPTION("Comedi driver for National Instruments PCI-6527");
502MODULE_LICENSE("GPL");
503
