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23#ifndef _LINUX_EMXX_H
24#define _LINUX_EMXX_H
25
26
27
28
29
30#if 0
31#define DEBUG
32#define UDC_DEBUG_DUMP
33#endif
34
35
36
37
38#define USE_DMA 1
39#define USE_SUSPEND_WAIT 1
40
41
42
43#ifndef TRUE
44#define TRUE 1
45#define FALSE 0
46#endif
47
48
49
50#define VBUS_VALUE GPIO_VBUS
51
52
53#define GPIO_VBUS 0
54#define INT_VBUS 0
55
56
57
58
59#define VBUS_CHATTERING_MDELAY 1
60
61#define DMA_DISABLE_TIME 10
62
63
64
65
66#define NUM_ENDPOINTS 14
67#define REG_EP_NUM 15
68#define DMA_MAX_COUNT 256
69
70
71
72#define EPC_RST_DISABLE_TIME 1
73#define EPC_DIRPD_DISABLE_TIME 1
74#define EPC_PLL_LOCK_COUNT 1000
75#define IN_DATA_EMPTY_COUNT 1000
76
77#define CHATGER_TIME 700
78#define USB_SUSPEND_TIME 2000
79
80
81
82#define U2F_ENABLE 1
83#define U2F_DISABLE 0
84
85
86
87#define BIT00 0x00000001
88#define BIT01 0x00000002
89#define BIT02 0x00000004
90#define BIT03 0x00000008
91#define BIT04 0x00000010
92#define BIT05 0x00000020
93#define BIT06 0x00000040
94#define BIT07 0x00000080
95#define BIT08 0x00000100
96#define BIT09 0x00000200
97#define BIT10 0x00000400
98#define BIT11 0x00000800
99#define BIT12 0x00001000
100#define BIT13 0x00002000
101#define BIT14 0x00004000
102#define BIT15 0x00008000
103#define BIT16 0x00010000
104#define BIT17 0x00020000
105#define BIT18 0x00040000
106#define BIT19 0x00080000
107#define BIT20 0x00100000
108#define BIT21 0x00200000
109#define BIT22 0x00400000
110#define BIT23 0x00800000
111#define BIT24 0x01000000
112#define BIT25 0x02000000
113#define BIT26 0x04000000
114#define BIT27 0x08000000
115#define BIT28 0x10000000
116#define BIT29 0x20000000
117#define BIT30 0x40000000
118#define BIT31 0x80000000
119
120#if 0
121
122#define USBTESTMODE (BIT18+BIT17+BIT16)
123#define TEST_J BIT16
124#define TEST_K BIT17
125#define TEST_SE0_NAK (BIT17+BIT16)
126#define TEST_PACKET BIT18
127#endif
128#define TEST_FORCE_ENABLE (BIT18+BIT16)
129
130#define INT_SEL BIT10
131#define CONSTFS BIT09
132#define SOF_RCV BIT08
133#define RSUM_IN BIT07
134#define SUSPEND BIT06
135#define CONF BIT05
136#define DEFAULT BIT04
137#define CONNECTB BIT03
138#define PUE2 BIT02
139
140#define MAX_TEST_MODE_NUM 0x05
141#define TEST_MODE_SHIFT 16
142
143
144#define SPEED_MODE BIT06
145#define HIGH_SPEED BIT06
146
147#define CONF BIT05
148#define DEFAULT BIT04
149#define USB_RST BIT03
150#define SPND_OUT BIT02
151#define RSUM_OUT BIT01
152
153
154#define USB_ADDR 0x007F0000
155#define SOF_STATUS BIT15
156#define UFRAME (BIT14+BIT13+BIT12)
157#define FRAME 0x000007FF
158
159#define USB_ADRS_SHIFT 16
160
161
162#define SQUSET (BIT07+BIT06+BIT05+BIT04)
163
164#define USB_SQUSET (BIT06+BIT05+BIT04)
165
166
167#define FORCEHS BIT02
168#define CS_TESTMODEEN BIT01
169#define LOOPBACK BIT00
170
171
172
173
174
175#define EPn_INT 0x00FFFF00
176#define EP15_INT BIT23
177#define EP14_INT BIT22
178#define EP13_INT BIT21
179#define EP12_INT BIT20
180#define EP11_INT BIT19
181#define EP10_INT BIT18
182#define EP9_INT BIT17
183#define EP8_INT BIT16
184#define EP7_INT BIT15
185#define EP6_INT BIT14
186#define EP5_INT BIT13
187#define EP4_INT BIT12
188#define EP3_INT BIT11
189#define EP2_INT BIT10
190#define EP1_INT BIT09
191#define EP0_INT BIT08
192#define SPEED_MODE_INT BIT06
193#define SOF_ERROR_INT BIT05
194#define SOF_INT BIT04
195#define USB_RST_INT BIT03
196#define SPND_INT BIT02
197#define RSUM_INT BIT01
198
199#define USB_INT_STA_RW 0x7E
200
201
202#define EP15_0_EN 0x00FFFF00
203#define EP15_EN BIT23
204#define EP14_EN BIT22
205#define EP13_EN BIT21
206#define EP12_EN BIT20
207#define EP11_EN BIT19
208#define EP10_EN BIT18
209#define EP9_EN BIT17
210#define EP8_EN BIT16
211#define EP7_EN BIT15
212#define EP6_EN BIT14
213#define EP5_EN BIT13
214#define EP4_EN BIT12
215#define EP3_EN BIT11
216#define EP2_EN BIT10
217#define EP1_EN BIT09
218#define EP0_EN BIT08
219#define SPEED_MODE_EN BIT06
220#define SOF_ERROR_EN BIT05
221#define SOF_EN BIT04
222#define USB_RST_EN BIT03
223#define SPND_EN BIT02
224#define RSUM_EN BIT01
225
226#define USB_INT_EN_BIT \
227 (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN)
228
229
230#define EP0_STGSEL BIT18
231#define EP0_OVERSEL BIT17
232#define EP0_AUTO BIT16
233#define EP0_PIDCLR BIT09
234#define EP0_BCLR BIT08
235#define EP0_DEND BIT07
236#define EP0_DW (BIT06+BIT05)
237#define EP0_DW4 0
238#define EP0_DW3 (BIT06+BIT05)
239#define EP0_DW2 BIT06
240#define EP0_DW1 BIT05
241
242#define EP0_INAK_EN BIT04
243#define EP0_PERR_NAK_CLR BIT03
244#define EP0_STL BIT02
245#define EP0_INAK BIT01
246#define EP0_ONAK BIT00
247
248
249#define EP0_PID BIT18
250#define EP0_PERR_NAK BIT17
251#define EP0_PERR_NAK_INT BIT16
252#define EP0_OUT_NAK_INT BIT15
253#define EP0_OUT_NULL BIT14
254#define EP0_OUT_FULL BIT13
255#define EP0_OUT_EMPTY BIT12
256#define EP0_IN_NAK_INT BIT11
257#define EP0_IN_DATA BIT10
258#define EP0_IN_FULL BIT09
259#define EP0_IN_EMPTY BIT08
260#define EP0_OUT_NULL_INT BIT07
261#define EP0_OUT_OR_INT BIT06
262#define EP0_OUT_INT BIT05
263#define EP0_IN_INT BIT04
264#define EP0_STALL_INT BIT03
265#define STG_END_INT BIT02
266#define STG_START_INT BIT01
267#define SETUP_INT BIT00
268
269#define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
270
271
272#define EP0_PERR_NAK_EN BIT16
273#define EP0_OUT_NAK_EN BIT15
274
275#define EP0_IN_NAK_EN BIT11
276
277#define EP0_OUT_NULL_EN BIT07
278#define EP0_OUT_OR_EN BIT06
279#define EP0_OUT_EN BIT05
280#define EP0_IN_EN BIT04
281#define EP0_STALL_EN BIT03
282#define STG_END_EN BIT02
283#define STG_START_EN BIT01
284#define SETUP_EN BIT00
285
286#define EP0_INT_EN_BIT \
287 (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN)
288
289
290#define EP0_LDATA 0x0000007F
291
292
293
294
295
296#define EPn_EN BIT31
297#define EPn_BUF_TYPE BIT30
298#define EPn_BUF_SINGLE BIT30
299
300#define EPn_DIR0 BIT26
301#define EPn_MODE (BIT25+BIT24)
302#define EPn_BULK 0
303#define EPn_INTERRUPT BIT24
304#define EPn_ISO BIT25
305
306#define EPn_OVERSEL BIT17
307#define EPn_AUTO BIT16
308
309#define EPn_IPIDCLR BIT11
310#define EPn_OPIDCLR BIT10
311#define EPn_BCLR BIT09
312#define EPn_CBCLR BIT08
313#define EPn_DEND BIT07
314#define EPn_DW (BIT06+BIT05)
315#define EPn_DW4 0
316#define EPn_DW3 (BIT06+BIT05)
317#define EPn_DW2 BIT06
318#define EPn_DW1 BIT05
319
320#define EPn_OSTL_EN BIT04
321#define EPn_ISTL BIT03
322#define EPn_OSTL BIT02
323
324#define EPn_ONAK BIT00
325
326
327#define EPn_ISO_PIDERR BIT29
328#define EPn_OPID BIT28
329#define EPn_OUT_NOTKN BIT27
330#define EPn_ISO_OR BIT26
331
332#define EPn_ISO_CRC BIT24
333#define EPn_OUT_END_INT BIT23
334#define EPn_OUT_OR_INT BIT22
335#define EPn_OUT_NAK_ERR_INT BIT21
336#define EPn_OUT_STALL_INT BIT20
337#define EPn_OUT_INT BIT19
338#define EPn_OUT_NULL_INT BIT18
339#define EPn_OUT_FULL BIT17
340#define EPn_OUT_EMPTY BIT16
341
342#define EPn_IPID BIT10
343#define EPn_IN_NOTKN BIT09
344#define EPn_ISO_UR BIT08
345#define EPn_IN_END_INT BIT07
346
347#define EPn_IN_NAK_ERR_INT BIT05
348#define EPn_IN_STALL_INT BIT04
349#define EPn_IN_INT BIT03
350#define EPn_IN_DATA BIT02
351#define EPn_IN_FULL BIT01
352#define EPn_IN_EMPTY BIT00
353
354#define EPn_INT_EN \
355 (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT)
356
357
358#define EPn_OUT_END_EN BIT23
359#define EPn_OUT_OR_EN BIT22
360#define EPn_OUT_NAK_ERR_EN BIT21
361#define EPn_OUT_STALL_EN BIT20
362#define EPn_OUT_EN BIT19
363#define EPn_OUT_NULL_EN BIT18
364
365#define EPn_IN_END_EN BIT07
366
367#define EPn_IN_NAK_ERR_EN BIT05
368#define EPn_IN_STALL_EN BIT04
369#define EPn_IN_EN BIT03
370
371
372#define EPn_STOP_MODE BIT11
373#define EPn_DEND_SET BIT10
374#define EPn_BURST_SET BIT09
375#define EPn_STOP_SET BIT08
376
377#define EPn_DMA_EN BIT04
378
379#define EPn_DMAMODE0 BIT00
380
381
382#define EPn_BASEAD 0x1FFF0000
383#define EPn_MPKT 0x000007FF
384
385
386#define EPn_DMACNT 0x01FF0000
387#define EPn_LDATA 0x000007FF
388
389
390
391
392
393#define WAIT_MODE BIT00
394
395
396#define ARBITER_CTR BIT31
397#define MCYCLE_RST BIT12
398
399#define ENDIAN_CTR (BIT09+BIT08)
400#define ENDIAN_BYTE_SWAP BIT09
401#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR
402
403#define HBUSREQ_MODE BIT05
404#define HTRANS_MODE BIT04
405
406#define WBURST_TYPE BIT02
407#define BURST_TYPE (BIT01+BIT00)
408#define BURST_MAX_16 0
409#define BURST_MAX_8 BIT00
410#define BURST_MAX_4 BIT01
411#define BURST_SINGLE BURST_TYPE
412
413
414#define DMA_ENDINT 0xFFFE0000
415
416#define AHB_VBUS_INT BIT13
417
418#define MBUS_ERRINT BIT06
419
420#define SBUS_ERRINT0 BIT04
421#define ERR_MASTER 0x0000000F
422
423
424#define DMA_ENDINTEN 0xFFFE0000
425
426#define VBUS_INTEN BIT13
427
428#define MBUS_ERRINTEN BIT06
429
430#define SBUS_ERRINT0EN BIT04
431
432
433#define DIRPD BIT12
434
435#define VBUS_LEVEL BIT08
436
437#define PLL_RESUME BIT05
438#define PLL_LOCK BIT04
439
440#define EPC_RST BIT00
441
442
443#define LINESTATE (BIT09+BIT08)
444#define DM_LEVEL BIT09
445#define DP_LEVEL BIT08
446
447#define PHY_TST BIT01
448#define PHY_TSTCLK BIT00
449
450
451#define AHBB_VER 0x00FF0000
452#define EPC_VER 0x0000FF00
453#define SS_VER 0x000000FF
454
455
456#define EP_AVAILABLE 0xFFFF0000
457#define DMA_AVAILABLE 0x0000FFFF
458
459
460#define DCR1_EPn_DMACNT 0x00FF0000
461
462#define DCR1_EPn_DIR0 BIT01
463#define DCR1_EPn_REQEN BIT00
464
465
466#define DCR2_EPn_LMPKT 0x07FF0000
467
468#define DCR2_EPn_MPKT 0x000007FF
469
470
471#define EPn_TADR 0xFFFFFFFF
472
473
474
475
476
477
478typedef struct _T_EP_REGS {
479 u32 EP_CONTROL;
480 u32 EP_STATUS;
481 u32 EP_INT_ENA;
482 u32 EP_DMA_CTRL;
483 u32 EP_PCKT_ADRS;
484 u32 EP_LEN_DCNT;
485 u32 EP_READ;
486 u32 EP_WRITE;
487} T_EP_REGS, *PT_EP_REGS;
488
489
490typedef struct _T_EP_DCR {
491 u32 EP_DCR1;
492 u32 EP_DCR2;
493 u32 EP_TADR;
494 u32 Reserved;
495} T_EP_DCR, *PT_EP_DCR;
496
497
498typedef struct _T_FC_REGS {
499 u32 USB_CONTROL;
500 u32 USB_STATUS;
501 u32 USB_ADDRESS;
502 u32 UTMI_CHARACTER_1;
503 u32 TEST_CONTROL;
504 u32 Reserved_14;
505 u32 SETUP_DATA0;
506 u32 SETUP_DATA1;
507 u32 USB_INT_STA;
508 u32 USB_INT_ENA;
509 u32 EP0_CONTROL;
510 u32 EP0_STATUS;
511 u32 EP0_INT_ENA;
512 u32 EP0_LENGTH;
513 u32 EP0_READ;
514 u32 EP0_WRITE;
515
516 T_EP_REGS EP_REGS[REG_EP_NUM];
517
518 u8 Reserved220[0x1000-0x220];
519
520 u32 AHBSCTR;
521 u32 AHBMCTR;
522 u32 AHBBINT;
523 u32 AHBBINTEN;
524 u32 EPCTR;
525 u32 USBF_EPTEST;
526
527 u8 Reserved1018[0x20-0x18];
528
529 u32 USBSSVER;
530 u32 USBSSCONF;
531
532 u8 Reserved1028[0x110-0x28];
533
534 T_EP_DCR EP_DCR[REG_EP_NUM];
535
536 u8 Reserved1200[0x1000-0x200];
537
538} __attribute__ ((aligned(32))) T_FC_REGS, *PT_FC_REGS;
539
540
541
542
543
544
545
546
547#define EP0_PACKETSIZE 64
548#define EP_PACKETSIZE 1024
549
550
551#define D_RAM_SIZE_CTRL 64
552
553
554#define D_FS_RAM_SIZE_BULK 64
555#define D_HS_RAM_SIZE_BULK 512
556
557
558struct nbu2ss_udc;
559
560
561enum ep0_state {
562 EP0_IDLE,
563 EP0_IN_DATA_PHASE,
564 EP0_OUT_DATA_PHASE,
565 EP0_IN_STATUS_PHASE,
566 EP0_OUT_STATUS_PAHSE,
567 EP0_END_XFER,
568 EP0_SUSPEND,
569 EP0_STALL,
570};
571
572struct nbu2ss_req {
573 struct usb_request req;
574 struct list_head queue;
575
576 u32 div_len;
577 bool dma_flag;
578 bool zero;
579
580 bool unaligned;
581
582 unsigned mapped:1;
583};
584
585struct nbu2ss_ep {
586 struct usb_ep ep;
587 struct list_head queue;
588
589 struct nbu2ss_udc *udc;
590
591 const struct usb_endpoint_descriptor *desc;
592
593 u8 epnum;
594 u8 direct;
595 u8 ep_type;
596
597 unsigned wedged:1;
598 unsigned halted:1;
599 unsigned stalled:1;
600
601 u8 *virt_buf;
602 dma_addr_t phys_buf;
603};
604
605
606struct nbu2ss_udc {
607 struct usb_gadget gadget;
608 struct usb_gadget_driver *driver;
609 struct platform_device *pdev;
610 struct device *dev;
611 spinlock_t lock;
612 struct completion *pdone;
613
614 enum ep0_state ep0state;
615 enum usb_device_state devstate;
616 struct usb_ctrlrequest ctrl;
617 struct nbu2ss_req ep0_req;
618 u8 ep0_buf[EP0_PACKETSIZE];
619
620 struct nbu2ss_ep ep[NUM_ENDPOINTS];
621
622 unsigned softconnect:1;
623 unsigned vbus_active:1;
624 unsigned linux_suspended:1;
625 unsigned linux_resume:1;
626 unsigned usb_suspended:1;
627 unsigned remote_wakeup:1;
628 unsigned udc_enabled:1;
629
630 unsigned mA;
631
632 u32 curr_config;
633
634 PT_FC_REGS p_regs;
635};
636
637
638typedef volatile union {
639 struct {
640 unsigned char DATA[4];
641 } byte;
642 unsigned int dw;
643} USB_REG_ACCESS;
644
645
646#define ERR(stuff...) printk(KERN_ERR "udc: " stuff)
647
648#endif
649