1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#define _HCI_HAL_INIT_C_
21
22#include <osdep_service.h>
23#include <drv_types.h>
24#include <rtw_efuse.h>
25#include <fw.h>
26#include <rtl8188e_hal.h>
27#include <rtl8188e_led.h>
28#include <rtw_iol.h>
29#include <usb_hal.h>
30#include <phy.h>
31
32#define HAL_BB_ENABLE 1
33
34static void _ConfigNormalChipOutEP_8188E(struct adapter *adapt, u8 NumOutPipe)
35{
36 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
37
38 switch (NumOutPipe) {
39 case 3:
40 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
41 haldata->OutEpNumber = 3;
42 break;
43 case 2:
44 haldata->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
45 haldata->OutEpNumber = 2;
46 break;
47 case 1:
48 haldata->OutEpQueueSel = TX_SELE_HQ;
49 haldata->OutEpNumber = 1;
50 break;
51 default:
52 break;
53 }
54 DBG_88E("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, haldata->OutEpQueueSel, haldata->OutEpNumber);
55}
56
57static bool HalUsbSetQueuePipeMapping8188EUsb(struct adapter *adapt, u8 NumInPipe, u8 NumOutPipe)
58{
59 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
60 bool result = false;
61
62 _ConfigNormalChipOutEP_8188E(adapt, NumOutPipe);
63
64
65 if (1 == haldata->OutEpNumber) {
66 if (1 != NumInPipe)
67 return result;
68 }
69
70
71
72 result = Hal_MappingOutPipe(adapt, NumOutPipe);
73
74 return result;
75}
76
77static void rtl8188eu_interface_configure(struct adapter *adapt)
78{
79 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
80 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt);
81
82 if (pdvobjpriv->ishighspeed)
83 haldata->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;
84 else
85 haldata->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;
86
87 haldata->interfaceIndex = pdvobjpriv->InterfaceNumber;
88
89 haldata->UsbTxAggMode = 1;
90 haldata->UsbTxAggDescNum = 0x6;
91
92 haldata->UsbRxAggMode = USB_RX_AGG_DMA;
93 haldata->UsbRxAggBlockCount = 8;
94 haldata->UsbRxAggBlockTimeout = 0x6;
95 haldata->UsbRxAggPageCount = 48;
96 haldata->UsbRxAggPageTimeout = 0x4;
97
98 HalUsbSetQueuePipeMapping8188EUsb(adapt,
99 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
100}
101
102static u32 rtl8188eu_InitPowerOn(struct adapter *adapt)
103{
104 u16 value16;
105
106 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
107 if (haldata->bMacPwrCtrlOn)
108 return _SUCCESS;
109
110 if (!rtl88eu_pwrseqcmdparsing(adapt, PWR_CUT_ALL_MSK,
111 PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,
112 Rtl8188E_NIC_PWR_ON_FLOW)) {
113 DBG_88E(KERN_ERR "%s: run power on flow fail\n", __func__);
114 return _FAIL;
115 }
116
117
118
119 usb_write16(adapt, REG_CR, 0x00);
120
121
122 value16 = usb_read16(adapt, REG_CR);
123 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
124 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
125
126
127 usb_write16(adapt, REG_CR, value16);
128 haldata->bMacPwrCtrlOn = true;
129
130 return _SUCCESS;
131}
132
133
134static void _InitInterrupt(struct adapter *Adapter)
135{
136 u32 imr, imr_ex;
137 u8 usb_opt;
138 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
139
140
141 usb_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
142
143 imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E;
144 usb_write32(Adapter, REG_HIMR_88E, imr);
145 haldata->IntrMask[0] = imr;
146
147 imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E | IMR_RXFOVW_88E;
148 usb_write32(Adapter, REG_HIMRE_88E, imr_ex);
149 haldata->IntrMask[1] = imr_ex;
150
151
152
153
154 usb_opt = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
155
156 if (!adapter_to_dvobj(Adapter)->ishighspeed)
157 usb_opt = usb_opt & (~INT_BULK_SEL);
158 else
159 usb_opt = usb_opt | (INT_BULK_SEL);
160
161 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt);
162}
163
164static void _InitQueueReservedPage(struct adapter *Adapter)
165{
166 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
167 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
168 u32 numHQ = 0;
169 u32 numLQ = 0;
170 u32 numNQ = 0;
171 u32 numPubQ;
172 u32 value32;
173 u8 value8;
174 bool bWiFiConfig = pregistrypriv->wifi_spec;
175
176 if (bWiFiConfig) {
177 if (haldata->OutEpQueueSel & TX_SELE_HQ)
178 numHQ = 0x29;
179
180 if (haldata->OutEpQueueSel & TX_SELE_LQ)
181 numLQ = 0x1C;
182
183
184 if (haldata->OutEpQueueSel & TX_SELE_NQ)
185 numNQ = 0x1C;
186 value8 = (u8)_NPQ(numNQ);
187 usb_write8(Adapter, REG_RQPN_NPQ, value8);
188
189 numPubQ = 0xA8 - numHQ - numLQ - numNQ;
190
191
192 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
193 usb_write32(Adapter, REG_RQPN, value32);
194 } else {
195 usb_write16(Adapter, REG_RQPN_NPQ, 0x0000);
196 usb_write16(Adapter, REG_RQPN_NPQ, 0x0d);
197 usb_write32(Adapter, REG_RQPN, 0x808E000d);
198 }
199}
200
201static void _InitTxBufferBoundary(struct adapter *Adapter, u8 txpktbuf_bndy)
202{
203 usb_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
204 usb_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
205 usb_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
206 usb_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
207 usb_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
208}
209
210static void _InitPageBoundary(struct adapter *Adapter)
211{
212
213
214 u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
215
216 usb_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
217}
218
219static void _InitNormalChipRegPriority(struct adapter *Adapter, u16 beQ,
220 u16 bkQ, u16 viQ, u16 voQ, u16 mgtQ,
221 u16 hiQ)
222{
223 u16 value16 = (usb_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
224
225 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
226 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
227 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
228
229 usb_write16(Adapter, REG_TRXDMA_CTRL, value16);
230}
231
232static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
233{
234 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
235
236 u16 value = 0;
237 switch (haldata->OutEpQueueSel) {
238 case TX_SELE_HQ:
239 value = QUEUE_HIGH;
240 break;
241 case TX_SELE_LQ:
242 value = QUEUE_LOW;
243 break;
244 case TX_SELE_NQ:
245 value = QUEUE_NORMAL;
246 break;
247 default:
248 break;
249 }
250 _InitNormalChipRegPriority(Adapter, value, value, value, value,
251 value, value);
252}
253
254static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
255{
256 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
257 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
258 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
259 u16 valueHi = 0;
260 u16 valueLow = 0;
261
262 switch (haldata->OutEpQueueSel) {
263 case (TX_SELE_HQ | TX_SELE_LQ):
264 valueHi = QUEUE_HIGH;
265 valueLow = QUEUE_LOW;
266 break;
267 case (TX_SELE_NQ | TX_SELE_LQ):
268 valueHi = QUEUE_NORMAL;
269 valueLow = QUEUE_LOW;
270 break;
271 case (TX_SELE_HQ | TX_SELE_NQ):
272 valueHi = QUEUE_HIGH;
273 valueLow = QUEUE_NORMAL;
274 break;
275 default:
276 break;
277 }
278
279 if (!pregistrypriv->wifi_spec) {
280 beQ = valueLow;
281 bkQ = valueLow;
282 viQ = valueHi;
283 voQ = valueHi;
284 mgtQ = valueHi;
285 hiQ = valueHi;
286 } else {
287 beQ = valueLow;
288 bkQ = valueHi;
289 viQ = valueHi;
290 voQ = valueLow;
291 mgtQ = valueHi;
292 hiQ = valueHi;
293 }
294 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
295}
296
297static void _InitNormalChipThreeOutEpPriority(struct adapter *Adapter)
298{
299 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
300 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
301
302 if (!pregistrypriv->wifi_spec) {
303 beQ = QUEUE_LOW;
304 bkQ = QUEUE_LOW;
305 viQ = QUEUE_NORMAL;
306 voQ = QUEUE_HIGH;
307 mgtQ = QUEUE_HIGH;
308 hiQ = QUEUE_HIGH;
309 } else {
310 beQ = QUEUE_LOW;
311 bkQ = QUEUE_NORMAL;
312 viQ = QUEUE_NORMAL;
313 voQ = QUEUE_HIGH;
314 mgtQ = QUEUE_HIGH;
315 hiQ = QUEUE_HIGH;
316 }
317 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
318}
319
320static void _InitQueuePriority(struct adapter *Adapter)
321{
322 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
323
324 switch (haldata->OutEpNumber) {
325 case 1:
326 _InitNormalChipOneOutEpPriority(Adapter);
327 break;
328 case 2:
329 _InitNormalChipTwoOutEpPriority(Adapter);
330 break;
331 case 3:
332 _InitNormalChipThreeOutEpPriority(Adapter);
333 break;
334 default:
335 break;
336 }
337}
338
339static void _InitNetworkType(struct adapter *Adapter)
340{
341 u32 value32;
342
343 value32 = usb_read32(Adapter, REG_CR);
344
345 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
346
347 usb_write32(Adapter, REG_CR, value32);
348}
349
350static void _InitTransferPageSize(struct adapter *Adapter)
351{
352
353
354 u8 value8;
355 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
356 usb_write8(Adapter, REG_PBP, value8);
357}
358
359static void _InitDriverInfoSize(struct adapter *Adapter, u8 drvInfoSize)
360{
361 usb_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
362}
363
364static void _InitWMACSetting(struct adapter *Adapter)
365{
366 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
367
368 haldata->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |
369 RCR_CBSSID_DATA | RCR_CBSSID_BCN |
370 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
371 RCR_APP_MIC | RCR_APP_PHYSTS;
372
373
374 usb_write32(Adapter, REG_RCR, haldata->ReceiveConfig);
375
376
377 usb_write32(Adapter, REG_MAR, 0xFFFFFFFF);
378 usb_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
379}
380
381static void _InitAdaptiveCtrl(struct adapter *Adapter)
382{
383 u16 value16;
384 u32 value32;
385
386
387 value32 = usb_read32(Adapter, REG_RRSR);
388 value32 &= ~RATE_BITMAP_ALL;
389 value32 |= RATE_RRSR_CCK_ONLY_1M;
390 usb_write32(Adapter, REG_RRSR, value32);
391
392
393
394
395 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
396 usb_write16(Adapter, REG_SPEC_SIFS, value16);
397
398
399 value16 = _LRL(0x30) | _SRL(0x30);
400 usb_write16(Adapter, REG_RL, value16);
401}
402
403static void _InitEDCA(struct adapter *Adapter)
404{
405
406 usb_write16(Adapter, REG_SPEC_SIFS, 0x100a);
407 usb_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
408
409
410 usb_write16(Adapter, REG_SIFS_CTX, 0x100a);
411
412
413 usb_write16(Adapter, REG_SIFS_TRX, 0x100a);
414
415
416 usb_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
417 usb_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
418 usb_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
419 usb_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
420}
421
422static void _InitRDGSetting(struct adapter *Adapter)
423{
424 usb_write8(Adapter, REG_RD_CTRL, 0xFF);
425 usb_write16(Adapter, REG_RD_NAV_NXT, 0x200);
426 usb_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
427}
428
429static void _InitRxSetting(struct adapter *Adapter)
430{
431 usb_write32(Adapter, REG_MACID, 0x87654321);
432 usb_write32(Adapter, 0x0700, 0x87654321);
433}
434
435static void _InitRetryFunction(struct adapter *Adapter)
436{
437 u8 value8;
438
439 value8 = usb_read8(Adapter, REG_FWHW_TXQ_CTRL);
440 value8 |= EN_AMPDU_RTY_NEW;
441 usb_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
442
443
444 usb_write8(Adapter, REG_ACKTO, 0x40);
445}
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462static void usb_AggSettingTxUpdate(struct adapter *Adapter)
463{
464 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
465 u32 value32;
466
467 if (Adapter->registrypriv.wifi_spec)
468 haldata->UsbTxAggMode = false;
469
470 if (haldata->UsbTxAggMode) {
471 value32 = usb_read32(Adapter, REG_TDECTRL);
472 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
473 value32 |= ((haldata->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
474
475 usb_write32(Adapter, REG_TDECTRL, value32);
476 }
477}
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494static void
495usb_AggSettingRxUpdate(
496 struct adapter *Adapter
497 )
498{
499 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
500 u8 valueDMA;
501 u8 valueUSB;
502
503 valueDMA = usb_read8(Adapter, REG_TRXDMA_CTRL);
504 valueUSB = usb_read8(Adapter, REG_USB_SPECIAL_OPTION);
505
506 switch (haldata->UsbRxAggMode) {
507 case USB_RX_AGG_DMA:
508 valueDMA |= RXDMA_AGG_EN;
509 valueUSB &= ~USB_AGG_EN;
510 break;
511 case USB_RX_AGG_USB:
512 valueDMA &= ~RXDMA_AGG_EN;
513 valueUSB |= USB_AGG_EN;
514 break;
515 case USB_RX_AGG_MIX:
516 valueDMA |= RXDMA_AGG_EN;
517 valueUSB |= USB_AGG_EN;
518 break;
519 case USB_RX_AGG_DISABLE:
520 default:
521 valueDMA &= ~RXDMA_AGG_EN;
522 valueUSB &= ~USB_AGG_EN;
523 break;
524 }
525
526 usb_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
527 usb_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
528
529 switch (haldata->UsbRxAggMode) {
530 case USB_RX_AGG_DMA:
531 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
532 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, haldata->UsbRxAggPageTimeout);
533 break;
534 case USB_RX_AGG_USB:
535 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
536 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
537 break;
538 case USB_RX_AGG_MIX:
539 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, haldata->UsbRxAggPageCount);
540 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (haldata->UsbRxAggPageTimeout & 0x1F));
541 usb_write8(Adapter, REG_USB_AGG_TH, haldata->UsbRxAggBlockCount);
542 usb_write8(Adapter, REG_USB_AGG_TO, haldata->UsbRxAggBlockTimeout);
543 break;
544 case USB_RX_AGG_DISABLE:
545 default:
546
547 break;
548 }
549
550 switch (PBP_128) {
551 case PBP_128:
552 haldata->HwRxPageSize = 128;
553 break;
554 case PBP_64:
555 haldata->HwRxPageSize = 64;
556 break;
557 case PBP_256:
558 haldata->HwRxPageSize = 256;
559 break;
560 case PBP_512:
561 haldata->HwRxPageSize = 512;
562 break;
563 case PBP_1024:
564 haldata->HwRxPageSize = 1024;
565 break;
566 default:
567 break;
568 }
569}
570
571static void InitUsbAggregationSetting(struct adapter *Adapter)
572{
573 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
574
575
576 usb_AggSettingTxUpdate(Adapter);
577
578
579 usb_AggSettingRxUpdate(Adapter);
580
581
582 haldata->UsbRxHighSpeedMode = false;
583}
584
585static void _InitBeaconParameters(struct adapter *Adapter)
586{
587 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
588
589 usb_write16(Adapter, REG_BCN_CTRL, 0x1010);
590
591
592 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404);
593 usb_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
594 usb_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
595
596
597
598 usb_write16(Adapter, REG_BCNTCFG, 0x660F);
599
600 haldata->RegBcnCtrlVal = usb_read8(Adapter, REG_BCN_CTRL);
601 haldata->RegTxPause = usb_read8(Adapter, REG_TXPAUSE);
602 haldata->RegFwHwTxQCtrl = usb_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
603 haldata->RegReg542 = usb_read8(Adapter, REG_TBTT_PROHIBIT+2);
604 haldata->RegCR_1 = usb_read8(Adapter, REG_CR+1);
605}
606
607static void _BeaconFunctionEnable(struct adapter *Adapter,
608 bool Enable, bool Linked)
609{
610 usb_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
611
612 usb_write8(Adapter, REG_RD_CTRL+1, 0x6F);
613}
614
615
616static void _BBTurnOnBlock(struct adapter *Adapter)
617{
618 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
619 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
620}
621
622enum {
623 Antenna_Lfet = 1,
624 Antenna_Right = 2,
625};
626
627static void _InitAntenna_Selection(struct adapter *Adapter)
628{
629 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
630
631 if (haldata->AntDivCfg == 0)
632 return;
633 DBG_88E("==> %s ....\n", __func__);
634
635 usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0)|BIT23);
636 phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
637
638 if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
639 haldata->CurAntenna = Antenna_A;
640 else
641 haldata->CurAntenna = Antenna_B;
642 DBG_88E("%s,Cur_ant:(%x)%s\n", __func__, haldata->CurAntenna, (haldata->CurAntenna == Antenna_A) ? "Antenna_A" : "Antenna_B");
643}
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
661{
662 u8 val8;
663 enum rt_rf_power_state rfpowerstate = rf_off;
664
665 if (adapt->pwrctrlpriv.bHWPowerdown) {
666 val8 = usb_read8(adapt, REG_HSISR);
667 DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
668 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
669 } else {
670 usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
671 val8 = usb_read8(adapt, REG_GPIO_IO_SEL);
672 DBG_88E("GPIO_IN=%02x\n", val8);
673 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
674 }
675 return rfpowerstate;
676}
677
678static u32 rtl8188eu_hal_init(struct adapter *Adapter)
679{
680 u8 value8 = 0;
681 u16 value16;
682 u8 txpktbuf_bndy;
683 u32 status = _SUCCESS;
684 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
685 struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
686 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
687 u32 init_start_time = jiffies;
688
689 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
690
691
692 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
693
694 if (Adapter->pwrctrlpriv.bkeepfwalive) {
695
696 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
697 rtl88eu_phy_iq_calibrate(Adapter, true);
698 } else {
699 rtl88eu_phy_iq_calibrate(Adapter, false);
700 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
701 }
702
703 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
704 rtl88eu_phy_lc_calibrate(Adapter);
705
706 goto exit;
707 }
708
709 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
710 status = rtl8188eu_InitPowerOn(Adapter);
711 if (status == _FAIL) {
712 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
713 goto exit;
714 }
715
716
717 haldata->CurrentChannel = 6;
718
719 if (pwrctrlpriv->reg_rfoff) {
720 pwrctrlpriv->rf_pwrstate = rf_off;
721 }
722
723
724
725
726
727 if (!pregistrypriv->wifi_spec) {
728 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
729 } else {
730
731 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
732 }
733
734 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
735 _InitQueueReservedPage(Adapter);
736 _InitQueuePriority(Adapter);
737 _InitPageBoundary(Adapter);
738 _InitTransferPageSize(Adapter);
739
740 _InitTxBufferBoundary(Adapter, 0);
741
742 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
743 if (Adapter->registrypriv.mp_mode == 1) {
744 _InitRxSetting(Adapter);
745 Adapter->bFWReady = false;
746 haldata->fw_ractrl = false;
747 } else {
748 status = rtl88eu_download_fw(Adapter);
749
750 if (status) {
751 DBG_88E("%s: Download Firmware failed!!\n", __func__);
752 Adapter->bFWReady = false;
753 haldata->fw_ractrl = false;
754 return status;
755 } else {
756 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializeadapt8192CSdio(): Download Firmware Success!!\n"));
757 Adapter->bFWReady = true;
758 haldata->fw_ractrl = false;
759 }
760 }
761 rtl8188e_InitializeFirmwareVars(Adapter);
762
763 rtl88eu_phy_mac_config(Adapter);
764
765 rtl88eu_phy_bb_config(Adapter);
766
767 rtl88eu_phy_rf_config(Adapter);
768
769 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
770 status = rtl8188e_iol_efuse_patch(Adapter);
771 if (status == _FAIL) {
772 DBG_88E("%s rtl8188e_iol_efuse_patch failed\n", __func__);
773 goto exit;
774 }
775
776 _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
777
778 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
779 status = InitLLTTable(Adapter, txpktbuf_bndy);
780 if (status == _FAIL) {
781 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
782 goto exit;
783 }
784
785 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
786
787 _InitDriverInfoSize(Adapter, DRVINFO_SZ);
788
789 _InitInterrupt(Adapter);
790 hal_init_macaddr(Adapter);
791 _InitNetworkType(Adapter);
792 _InitWMACSetting(Adapter);
793 _InitAdaptiveCtrl(Adapter);
794 _InitEDCA(Adapter);
795 _InitRetryFunction(Adapter);
796 InitUsbAggregationSetting(Adapter);
797 _InitBeaconParameters(Adapter);
798
799
800
801 value16 = usb_read16(Adapter, REG_CR);
802 value16 |= (MACTXEN | MACRXEN);
803 usb_write8(Adapter, REG_CR, value16);
804
805 if (haldata->bRDGEnable)
806 _InitRDGSetting(Adapter);
807
808
809
810 value8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
811 usb_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
812
813 usb_write8(Adapter, REG_TX_RPT_CTRL+1, 2);
814
815 usb_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
816
817 usb_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
818
819 usb_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);
820 usb_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);
821
822
823 haldata->RfRegChnlVal[0] = phy_query_rf_reg(Adapter, (enum rf_radio_path)0, RF_CHNLBW, bRFRegOffsetMask);
824 haldata->RfRegChnlVal[1] = phy_query_rf_reg(Adapter, (enum rf_radio_path)1, RF_CHNLBW, bRFRegOffsetMask);
825
826HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
827 _BBTurnOnBlock(Adapter);
828
829HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
830 invalidate_cam_all(Adapter);
831
832HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
833
834 phy_set_tx_power_level(Adapter, haldata->CurrentChannel);
835
836
837
838
839 _InitAntenna_Selection(Adapter);
840
841
842
843
844
845 usb_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
846
847
848
849 usb_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
850
851 if (pregistrypriv->wifi_spec)
852 usb_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
853
854
855 usb_write8(Adapter, 0x652, 0x0);
856
857HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
858 rtl8188e_InitHalDm(Adapter);
859
860
861
862
863
864
865
866
867 pwrctrlpriv->rf_pwrstate = rf_on;
868
869
870 usb_write8(Adapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
871
872
873 usb_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);
874
875
876 usb_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
877
878
879 usb_write16(Adapter, REG_TXDMA_OFFSET_CHK, (usb_read16(Adapter, REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
880
881HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
882
883 if (pwrctrlpriv->rf_pwrstate == rf_on) {
884 if (haldata->odmpriv.RFCalibrateInfo.bIQKInitialized) {
885 rtl88eu_phy_iq_calibrate(Adapter, true);
886 } else {
887 rtl88eu_phy_iq_calibrate(Adapter, false);
888 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
889 }
890
891HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
892
893 ODM_TXPowerTrackingCheck(&haldata->odmpriv);
894
895HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
896 rtl88eu_phy_lc_calibrate(Adapter);
897 }
898
899
900
901 usb_write8(Adapter, REG_USB_HRPWM, 0);
902
903
904 usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
905
906exit:
907HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
908
909 DBG_88E("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time));
910
911
912 return status;
913}
914
915static void CardDisableRTL8188EU(struct adapter *Adapter)
916{
917 u8 val8;
918 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
919
920 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CardDisableRTL8188EU\n"));
921
922
923 val8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
924 usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
925
926
927 usb_write8(Adapter, REG_CR, 0x0);
928
929
930 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
931 PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,
932 Rtl8188E_NIC_LPS_ENTER_FLOW);
933
934
935
936 val8 = usb_read8(Adapter, REG_MCUFWDL);
937 if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) {
938
939 val8 = usb_read8(Adapter, REG_SYS_FUNC_EN+1);
940 val8 &= ~BIT(2);
941 usb_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
942 }
943
944
945 usb_write8(Adapter, REG_MCUFWDL, 0);
946
947
948
949 val8 = usb_read8(Adapter, REG_32K_CTRL);
950 usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
951
952
953 rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
954 PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,
955 Rtl8188E_NIC_DISABLE_FLOW);
956
957
958 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
959 usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
960 val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
961 usb_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
962
963
964 val8 = usb_read8(Adapter, GPIO_IN);
965 usb_write8(Adapter, GPIO_OUT, val8);
966 usb_write8(Adapter, GPIO_IO_SEL, 0xFF);
967
968 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL);
969 usb_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
970 val8 = usb_read8(Adapter, REG_GPIO_IO_SEL+1);
971 usb_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);
972 usb_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);
973 haldata->bMacPwrCtrlOn = false;
974 Adapter->bFWReady = false;
975}
976static void rtl8192cu_hw_power_down(struct adapter *adapt)
977{
978
979
980
981
982 usb_write8(adapt, REG_RSV_CTRL, 0x0);
983 usb_write16(adapt, REG_APS_FSMCO, 0x8812);
984}
985
986static u32 rtl8188eu_hal_deinit(struct adapter *Adapter)
987{
988
989 DBG_88E("==> %s\n", __func__);
990
991 usb_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
992 usb_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
993
994 DBG_88E("bkeepfwalive(%x)\n", Adapter->pwrctrlpriv.bkeepfwalive);
995 if (Adapter->pwrctrlpriv.bkeepfwalive) {
996 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
997 rtl8192cu_hw_power_down(Adapter);
998 } else {
999 if (Adapter->hw_init_completed) {
1000 CardDisableRTL8188EU(Adapter);
1001
1002 if ((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown))
1003 rtl8192cu_hw_power_down(Adapter);
1004 }
1005 }
1006 return _SUCCESS;
1007 }
1008
1009static unsigned int rtl8188eu_inirp_init(struct adapter *Adapter)
1010{
1011 u8 i;
1012 struct recv_buf *precvbuf;
1013 uint status;
1014 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1015
1016 status = _SUCCESS;
1017
1018 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1019 ("===> usb_inirp_init\n"));
1020
1021 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1022
1023
1024 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1025 for (i = 0; i < NR_RECVBUFF; i++) {
1026 if (usb_read_port(Adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == false) {
1027 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n"));
1028 status = _FAIL;
1029 goto exit;
1030 }
1031
1032 precvbuf++;
1033 precvpriv->free_recv_buf_queue_cnt--;
1034 }
1035
1036exit:
1037
1038 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n"));
1039
1040
1041 return status;
1042}
1043
1044static unsigned int rtl8188eu_inirp_deinit(struct adapter *Adapter)
1045{
1046 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n"));
1047
1048 usb_read_port_cancel(Adapter);
1049
1050 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n"));
1051
1052 return _SUCCESS;
1053}
1054
1055
1056
1057
1058
1059
1060static void Hal_EfuseParsePIDVID_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1061{
1062 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1063
1064 if (!AutoLoadFail) {
1065
1066 haldata->EEPROMVID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_VID_88EU]);
1067 haldata->EEPROMPID = EF2BYTE(*(__le16 *)&hwinfo[EEPROM_PID_88EU]);
1068
1069
1070 haldata->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CUSTOMERID_88E];
1071 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1072 } else {
1073 haldata->EEPROMVID = EEPROM_Default_VID;
1074 haldata->EEPROMPID = EEPROM_Default_PID;
1075
1076
1077 haldata->EEPROMCustomerID = EEPROM_Default_CustomerID;
1078 haldata->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
1079 }
1080
1081 DBG_88E("VID = 0x%04X, PID = 0x%04X\n", haldata->EEPROMVID, haldata->EEPROMPID);
1082 DBG_88E("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", haldata->EEPROMCustomerID, haldata->EEPROMSubCustomerID);
1083}
1084
1085static void Hal_EfuseParseMACAddr_8188EU(struct adapter *adapt, u8 *hwinfo, bool AutoLoadFail)
1086{
1087 u16 i;
1088 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
1089 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1090
1091 if (AutoLoadFail) {
1092 for (i = 0; i < 6; i++)
1093 eeprom->mac_addr[i] = sMacAddr[i];
1094 } else {
1095
1096 memcpy(eeprom->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
1097 }
1098 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1099 ("Hal_EfuseParseMACAddr_8188EU: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1100 eeprom->mac_addr[0], eeprom->mac_addr[1],
1101 eeprom->mac_addr[2], eeprom->mac_addr[3],
1102 eeprom->mac_addr[4], eeprom->mac_addr[5]));
1103}
1104
1105static void
1106readAdapterInfo_8188EU(
1107 struct adapter *adapt
1108 )
1109{
1110 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(adapt);
1111
1112
1113 Hal_EfuseParseIDCode88E(adapt, eeprom->efuse_eeprom_data);
1114 Hal_EfuseParsePIDVID_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1115 Hal_EfuseParseMACAddr_8188EU(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1116
1117 Hal_ReadPowerSavingMode88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1118 Hal_ReadTxPowerInfo88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1119 Hal_EfuseParseEEPROMVer88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1120 rtl8188e_EfuseParseChnlPlan(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1121 Hal_EfuseParseXtal_8188E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1122 Hal_EfuseParseCustomerID88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1123 Hal_ReadAntennaDiversity88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1124 Hal_EfuseParseBoardType88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1125 Hal_ReadThermalMeter_88E(adapt, eeprom->efuse_eeprom_data, eeprom->bautoload_fail_flag);
1126
1127}
1128
1129static void _ReadPROMContent(
1130 struct adapter *Adapter
1131 )
1132{
1133 struct eeprom_priv *eeprom = GET_EEPROM_EFUSE_PRIV(Adapter);
1134 u8 eeValue;
1135
1136
1137 eeValue = usb_read8(Adapter, REG_9346CR);
1138 eeprom->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1139 eeprom->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1140
1141 DBG_88E("Boot from %s, Autoload %s !\n", (eeprom->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1142 (eeprom->bautoload_fail_flag ? "Fail" : "OK"));
1143
1144 Hal_InitPGData88E(Adapter);
1145 readAdapterInfo_8188EU(Adapter);
1146}
1147
1148static void _ReadRFType(struct adapter *Adapter)
1149{
1150 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1151
1152 haldata->rf_chip = RF_6052;
1153}
1154
1155static void _ReadAdapterInfo8188EU(struct adapter *Adapter)
1156{
1157 u32 start = jiffies;
1158
1159 MSG_88E("====> %s\n", __func__);
1160
1161 _ReadRFType(Adapter);
1162 _ReadPROMContent(Adapter);
1163
1164 MSG_88E("<==== %s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
1165}
1166
1167#define GPIO_DEBUG_PORT_NUM 0
1168static void rtl8192cu_trigger_gpio_0(struct adapter *adapt)
1169{
1170}
1171
1172static void ResumeTxBeacon(struct adapter *adapt)
1173{
1174 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1175
1176
1177
1178
1179 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
1180 haldata->RegFwHwTxQCtrl |= BIT6;
1181 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
1182 haldata->RegReg542 |= BIT0;
1183 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1184}
1185
1186static void StopTxBeacon(struct adapter *adapt)
1187{
1188 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
1189
1190
1191
1192
1193 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
1194 haldata->RegFwHwTxQCtrl &= (~BIT6);
1195 usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
1196 haldata->RegReg542 &= ~(BIT0);
1197 usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
1198
1199
1200}
1201
1202static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
1203{
1204 u8 val8;
1205 u8 mode = *((u8 *)val);
1206
1207
1208 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1209
1210
1211 val8 = usb_read8(Adapter, MSR)&0x0c;
1212 val8 |= mode;
1213 usb_write8(Adapter, MSR, val8);
1214
1215 DBG_88E("%s()-%d mode = %d\n", __func__, __LINE__, mode);
1216
1217 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
1218 StopTxBeacon(Adapter);
1219
1220 usb_write8(Adapter, REG_BCN_CTRL, 0x19);
1221 } else if ((mode == _HW_STATE_ADHOC_)) {
1222 ResumeTxBeacon(Adapter);
1223 usb_write8(Adapter, REG_BCN_CTRL, 0x1a);
1224 } else if (mode == _HW_STATE_AP_) {
1225 ResumeTxBeacon(Adapter);
1226
1227 usb_write8(Adapter, REG_BCN_CTRL, 0x12);
1228
1229
1230 usb_write32(Adapter, REG_RCR, 0x7000208e);
1231
1232 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1233
1234 usb_write16(Adapter, REG_RXFLTMAP1, 0x0400);
1235
1236
1237 usb_write8(Adapter, REG_BCNDMATIM, 0x02);
1238
1239 usb_write8(Adapter, REG_ATIMWND, 0x0a);
1240 usb_write16(Adapter, REG_BCNTCFG, 0x00);
1241 usb_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
1242 usb_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
1243
1244
1245 usb_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
1246
1247
1248 usb_write8(Adapter, REG_MBID_NUM, usb_read8(Adapter, REG_MBID_NUM) | BIT(3) | BIT(4));
1249
1250
1251
1252 usb_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | BIT(1)));
1253
1254
1255 usb_write8(Adapter, REG_BCN_CTRL_1, usb_read8(Adapter, REG_BCN_CTRL_1) | BIT(0));
1256 }
1257}
1258
1259static void hw_var_set_macaddr(struct adapter *Adapter, u8 variable, u8 *val)
1260{
1261 u8 idx = 0;
1262 u32 reg_macid;
1263
1264 reg_macid = REG_MACID;
1265
1266 for (idx = 0; idx < 6; idx++)
1267 usb_write8(Adapter, (reg_macid+idx), val[idx]);
1268}
1269
1270static void hw_var_set_bssid(struct adapter *Adapter, u8 variable, u8 *val)
1271{
1272 u8 idx = 0;
1273 u32 reg_bssid;
1274
1275 reg_bssid = REG_BSSID;
1276
1277 for (idx = 0; idx < 6; idx++)
1278 usb_write8(Adapter, (reg_bssid+idx), val[idx]);
1279}
1280
1281static void hw_var_set_bcn_func(struct adapter *Adapter, u8 variable, u8 *val)
1282{
1283 u32 bcn_ctrl_reg;
1284
1285 bcn_ctrl_reg = REG_BCN_CTRL;
1286
1287 if (*((u8 *)val))
1288 usb_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
1289 else
1290 usb_write8(Adapter, bcn_ctrl_reg, usb_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
1291}
1292
1293static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1294{
1295 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1296 struct dm_priv *pdmpriv = &haldata->dmpriv;
1297 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1298
1299 switch (variable) {
1300 case HW_VAR_MEDIA_STATUS:
1301 {
1302 u8 val8;
1303
1304 val8 = usb_read8(Adapter, MSR)&0x0c;
1305 val8 |= *((u8 *)val);
1306 usb_write8(Adapter, MSR, val8);
1307 }
1308 break;
1309 case HW_VAR_MEDIA_STATUS1:
1310 {
1311 u8 val8;
1312
1313 val8 = usb_read8(Adapter, MSR) & 0x03;
1314 val8 |= *((u8 *)val) << 2;
1315 usb_write8(Adapter, MSR, val8);
1316 }
1317 break;
1318 case HW_VAR_SET_OPMODE:
1319 hw_var_set_opmode(Adapter, variable, val);
1320 break;
1321 case HW_VAR_MAC_ADDR:
1322 hw_var_set_macaddr(Adapter, variable, val);
1323 break;
1324 case HW_VAR_BSSID:
1325 hw_var_set_bssid(Adapter, variable, val);
1326 break;
1327 case HW_VAR_BASIC_RATE:
1328 {
1329 u16 BrateCfg = 0;
1330 u8 RateIndex = 0;
1331
1332
1333
1334
1335
1336 HalSetBrateCfg(Adapter, val, &BrateCfg);
1337 DBG_88E("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg);
1338
1339
1340
1341
1342
1343
1344 BrateCfg = (BrateCfg | 0xd) & 0x15d;
1345 haldata->BasicRateSet = BrateCfg;
1346
1347 BrateCfg |= 0x01;
1348
1349 usb_write8(Adapter, REG_RRSR, BrateCfg & 0xff);
1350 usb_write8(Adapter, REG_RRSR+1, (BrateCfg >> 8) & 0xff);
1351 usb_write8(Adapter, REG_RRSR+2, usb_read8(Adapter, REG_RRSR+2)&0xf0);
1352
1353
1354 while (BrateCfg > 0x1) {
1355 BrateCfg = (BrateCfg >> 1);
1356 RateIndex++;
1357 }
1358
1359 usb_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex);
1360 }
1361 break;
1362 case HW_VAR_TXPAUSE:
1363 usb_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
1364 break;
1365 case HW_VAR_BCN_FUNC:
1366 hw_var_set_bcn_func(Adapter, variable, val);
1367 break;
1368 case HW_VAR_CORRECT_TSF:
1369 {
1370 u64 tsf;
1371 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1372 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1373
1374 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) - 1024;
1375
1376 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1377 StopTxBeacon(Adapter);
1378
1379
1380 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
1381
1382 usb_write32(Adapter, REG_TSFTR, tsf);
1383 usb_write32(Adapter, REG_TSFTR+4, tsf>>32);
1384
1385
1386 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(3));
1387
1388 if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
1389 ResumeTxBeacon(Adapter);
1390 }
1391 break;
1392 case HW_VAR_CHECK_BSSID:
1393 if (*((u8 *)val)) {
1394 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1395 } else {
1396 u32 val32;
1397
1398 val32 = usb_read32(Adapter, REG_RCR);
1399
1400 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1401
1402 usb_write32(Adapter, REG_RCR, val32);
1403 }
1404 break;
1405 case HW_VAR_MLME_DISCONNECT:
1406
1407
1408 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1409
1410
1411 usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
1412
1413
1414 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1415 break;
1416 case HW_VAR_MLME_SITESURVEY:
1417 if (*((u8 *)val)) {
1418
1419 u32 v = usb_read32(Adapter, REG_RCR);
1420 v &= ~(RCR_CBSSID_BCN);
1421 usb_write32(Adapter, REG_RCR, v);
1422
1423 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1424
1425
1426 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
1427 } else {
1428 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1429 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1430
1431 if ((is_client_associated_to_ap(Adapter)) ||
1432 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) {
1433
1434 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1435
1436
1437 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1438 } else if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1439 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1440
1441 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1442 }
1443 if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) {
1444 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1445 } else {
1446 if (Adapter->in_cta_test) {
1447 u32 v = usb_read32(Adapter, REG_RCR);
1448 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1449 usb_write32(Adapter, REG_RCR, v);
1450 } else {
1451 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
1452 }
1453 }
1454 }
1455 break;
1456 case HW_VAR_MLME_JOIN:
1457 {
1458 u8 RetryLimit = 0x30;
1459 u8 type = *((u8 *)val);
1460 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1461
1462 if (type == 0) {
1463
1464 usb_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
1465
1466 if (Adapter->in_cta_test) {
1467 u32 v = usb_read32(Adapter, REG_RCR);
1468 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1469 usb_write32(Adapter, REG_RCR, v);
1470 } else {
1471 usb_write32(Adapter, REG_RCR, usb_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
1472 }
1473
1474 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
1475 RetryLimit = (haldata->CustomerID == RT_CID_CCX) ? 7 : 48;
1476 else
1477 RetryLimit = 0x7;
1478 } else if (type == 1) {
1479
1480 usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
1481 } else if (type == 2) {
1482
1483
1484 usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
1485
1486 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
1487 RetryLimit = 0x7;
1488 }
1489 usb_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
1490 }
1491 break;
1492 case HW_VAR_BEACON_INTERVAL:
1493 usb_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
1494 break;
1495 case HW_VAR_SLOT_TIME:
1496 {
1497 u8 u1bAIFS, aSifsTime;
1498 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1499 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1500
1501 usb_write8(Adapter, REG_SLOT, val[0]);
1502
1503 if (pmlmeinfo->WMM_enable == 0) {
1504 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
1505 aSifsTime = 10;
1506 else
1507 aSifsTime = 16;
1508
1509 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
1510
1511
1512 usb_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS);
1513 usb_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS);
1514 usb_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS);
1515 usb_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS);
1516 }
1517 }
1518 break;
1519 case HW_VAR_RESP_SIFS:
1520
1521 usb_write8(Adapter, REG_R2T_SIFS, val[0]);
1522 usb_write8(Adapter, REG_R2T_SIFS+1, val[1]);
1523
1524 usb_write8(Adapter, REG_T2T_SIFS, val[2]);
1525 usb_write8(Adapter, REG_T2T_SIFS+1, val[3]);
1526 break;
1527 case HW_VAR_ACK_PREAMBLE:
1528 {
1529 u8 regTmp;
1530 u8 bShortPreamble = *((bool *)val);
1531
1532 regTmp = (haldata->nCur40MhzPrimeSC)<<5;
1533 if (bShortPreamble)
1534 regTmp |= 0x80;
1535
1536 usb_write8(Adapter, REG_RRSR+2, regTmp);
1537 }
1538 break;
1539 case HW_VAR_SEC_CFG:
1540 usb_write8(Adapter, REG_SECCFG, *((u8 *)val));
1541 break;
1542 case HW_VAR_DM_FLAG:
1543 podmpriv->SupportAbility = *((u8 *)val);
1544 break;
1545 case HW_VAR_DM_FUNC_OP:
1546 if (val[0])
1547 podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
1548 else
1549 podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
1550 break;
1551 case HW_VAR_DM_FUNC_SET:
1552 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1553 pdmpriv->DMFlag = pdmpriv->InitDMFlag;
1554 podmpriv->SupportAbility = pdmpriv->InitODMFlag;
1555 } else {
1556 podmpriv->SupportAbility |= *((u32 *)val);
1557 }
1558 break;
1559 case HW_VAR_DM_FUNC_CLR:
1560 podmpriv->SupportAbility &= *((u32 *)val);
1561 break;
1562 case HW_VAR_CAM_EMPTY_ENTRY:
1563 {
1564 u8 ucIndex = *((u8 *)val);
1565 u8 i;
1566 u32 ulCommand = 0;
1567 u32 ulContent = 0;
1568 u32 ulEncAlgo = CAM_AES;
1569
1570 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
1571
1572 if (i == 0)
1573 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
1574 else
1575 ulContent = 0;
1576
1577 ulCommand = CAM_CONTENT_COUNT*ucIndex+i;
1578 ulCommand = ulCommand | CAM_POLLINIG|CAM_WRITE;
1579
1580 usb_write32(Adapter, WCAMI, ulContent);
1581 usb_write32(Adapter, RWCAM, ulCommand);
1582 }
1583 }
1584 break;
1585 case HW_VAR_CAM_INVALID_ALL:
1586 usb_write32(Adapter, RWCAM, BIT(31)|BIT(30));
1587 break;
1588 case HW_VAR_CAM_WRITE:
1589 {
1590 u32 cmd;
1591 u32 *cam_val = (u32 *)val;
1592 usb_write32(Adapter, WCAMI, cam_val[0]);
1593
1594 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
1595 usb_write32(Adapter, RWCAM, cmd);
1596 }
1597 break;
1598 case HW_VAR_AC_PARAM_VO:
1599 usb_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
1600 break;
1601 case HW_VAR_AC_PARAM_VI:
1602 usb_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
1603 break;
1604 case HW_VAR_AC_PARAM_BE:
1605 haldata->AcParam_BE = ((u32 *)(val))[0];
1606 usb_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
1607 break;
1608 case HW_VAR_AC_PARAM_BK:
1609 usb_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
1610 break;
1611 case HW_VAR_ACM_CTRL:
1612 {
1613 u8 acm_ctrl = *((u8 *)val);
1614 u8 AcmCtrl = usb_read8(Adapter, REG_ACMHWCTRL);
1615
1616 if (acm_ctrl > 1)
1617 AcmCtrl = AcmCtrl | 0x1;
1618
1619 if (acm_ctrl & BIT(3))
1620 AcmCtrl |= AcmHw_VoqEn;
1621 else
1622 AcmCtrl &= (~AcmHw_VoqEn);
1623
1624 if (acm_ctrl & BIT(2))
1625 AcmCtrl |= AcmHw_ViqEn;
1626 else
1627 AcmCtrl &= (~AcmHw_ViqEn);
1628
1629 if (acm_ctrl & BIT(1))
1630 AcmCtrl |= AcmHw_BeqEn;
1631 else
1632 AcmCtrl &= (~AcmHw_BeqEn);
1633
1634 DBG_88E("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1635 usb_write8(Adapter, REG_ACMHWCTRL, AcmCtrl);
1636 }
1637 break;
1638 case HW_VAR_AMPDU_MIN_SPACE:
1639 {
1640 u8 MinSpacingToSet;
1641 u8 SecMinSpace;
1642
1643 MinSpacingToSet = *((u8 *)val);
1644 if (MinSpacingToSet <= 7) {
1645 switch (Adapter->securitypriv.dot11PrivacyAlgrthm) {
1646 case _NO_PRIVACY_:
1647 case _AES_:
1648 SecMinSpace = 0;
1649 break;
1650 case _WEP40_:
1651 case _WEP104_:
1652 case _TKIP_:
1653 case _TKIP_WTMIC_:
1654 SecMinSpace = 6;
1655 break;
1656 default:
1657 SecMinSpace = 7;
1658 break;
1659 }
1660 if (MinSpacingToSet < SecMinSpace)
1661 MinSpacingToSet = SecMinSpace;
1662 usb_write8(Adapter, REG_AMPDU_MIN_SPACE, (usb_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
1663 }
1664 }
1665 break;
1666 case HW_VAR_AMPDU_FACTOR:
1667 {
1668 u8 RegToSet_Normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1669 u8 FactorToSet;
1670 u8 *pRegToSet;
1671 u8 index = 0;
1672
1673 pRegToSet = RegToSet_Normal;
1674 FactorToSet = *((u8 *)val);
1675 if (FactorToSet <= 3) {
1676 FactorToSet = 1 << (FactorToSet + 2);
1677 if (FactorToSet > 0xf)
1678 FactorToSet = 0xf;
1679
1680 for (index = 0; index < 4; index++) {
1681 if ((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
1682 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
1683
1684 if ((pRegToSet[index] & 0x0f) > FactorToSet)
1685 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
1686
1687 usb_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
1688 }
1689 }
1690 }
1691 break;
1692 case HW_VAR_RXDMA_AGG_PG_TH:
1693 {
1694 u8 threshold = *((u8 *)val);
1695 if (threshold == 0)
1696 threshold = haldata->UsbRxAggPageCount;
1697 usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
1698 }
1699 break;
1700 case HW_VAR_SET_RPWM:
1701 break;
1702 case HW_VAR_H2C_FW_PWRMODE:
1703 {
1704 u8 psmode = (*(u8 *)val);
1705
1706
1707
1708 if ((psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(haldata->VersionID)))
1709 ODM_RF_Saving(podmpriv, true);
1710 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
1711 }
1712 break;
1713 case HW_VAR_H2C_FW_JOINBSSRPT:
1714 {
1715 u8 mstatus = (*(u8 *)val);
1716 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
1717 }
1718 break;
1719 case HW_VAR_INITIAL_GAIN:
1720 {
1721 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1722 u32 rx_gain = ((u32 *)(val))[0];
1723
1724 if (rx_gain == 0xff) {
1725 ODM_Write_DIG(podmpriv, pDigTable->BackupIGValue);
1726 } else {
1727 pDigTable->BackupIGValue = pDigTable->CurIGValue;
1728 ODM_Write_DIG(podmpriv, rx_gain);
1729 }
1730 }
1731 break;
1732 case HW_VAR_TRIGGER_GPIO_0:
1733 rtl8192cu_trigger_gpio_0(Adapter);
1734 break;
1735 case HW_VAR_RPT_TIMER_SETTING:
1736 {
1737 u16 min_rpt_time = (*(u16 *)val);
1738 ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
1739 }
1740 break;
1741 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
1742 {
1743 u8 Optimum_antenna = (*(u8 *)val);
1744 u8 Ant;
1745
1746 if (haldata->CurAntenna != Optimum_antenna) {
1747 Ant = (Optimum_antenna == 2) ? MAIN_ANT : AUX_ANT;
1748 rtl88eu_dm_update_rx_idle_ant(&haldata->odmpriv, Ant);
1749
1750 haldata->CurAntenna = Optimum_antenna;
1751 }
1752 }
1753 break;
1754 case HW_VAR_EFUSE_BYTES:
1755 haldata->EfuseUsedBytes = *((u16 *)val);
1756 break;
1757 case HW_VAR_FIFO_CLEARN_UP:
1758 {
1759 struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv;
1760 u8 trycnt = 100;
1761
1762
1763 usb_write8(Adapter, REG_TXPAUSE, 0xff);
1764
1765
1766 Adapter->xmitpriv.nqos_ssn = usb_read16(Adapter, REG_NQOS_SEQ);
1767
1768 if (!pwrpriv->bkeepfwalive) {
1769
1770 usb_write32(Adapter, REG_RXPKT_NUM, (usb_read32(Adapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1771 do {
1772 if (!(usb_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE))
1773 break;
1774 } while (trycnt--);
1775 if (trycnt == 0)
1776 DBG_88E("Stop RX DMA failed......\n");
1777
1778
1779 usb_write16(Adapter, REG_RQPN_NPQ, 0x0);
1780 usb_write32(Adapter, REG_RQPN, 0x80000000);
1781 mdelay(10);
1782 }
1783 }
1784 break;
1785 case HW_VAR_CHECK_TXBUF:
1786 break;
1787 case HW_VAR_APFM_ON_MAC:
1788 haldata->bMacPwrCtrlOn = *val;
1789 DBG_88E("%s: bMacPwrCtrlOn=%d\n", __func__, haldata->bMacPwrCtrlOn);
1790 break;
1791 case HW_VAR_TX_RPT_MAX_MACID:
1792 {
1793 u8 maxMacid = *val;
1794 DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
1795 usb_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
1796 }
1797 break;
1798 case HW_VAR_H2C_MEDIA_STATUS_RPT:
1799 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(__le16 *)val));
1800 break;
1801 case HW_VAR_BCN_VALID:
1802
1803 usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT0);
1804 break;
1805 default:
1806 break;
1807 }
1808}
1809
1810static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
1811{
1812 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1813 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1814
1815 switch (variable) {
1816 case HW_VAR_BASIC_RATE:
1817 *((u16 *)(val)) = haldata->BasicRateSet;
1818 case HW_VAR_TXPAUSE:
1819 val[0] = usb_read8(Adapter, REG_TXPAUSE);
1820 break;
1821 case HW_VAR_BCN_VALID:
1822
1823 val[0] = (BIT0 & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false;
1824 break;
1825 case HW_VAR_DM_FLAG:
1826 val[0] = podmpriv->SupportAbility;
1827 break;
1828 case HW_VAR_RF_TYPE:
1829 val[0] = haldata->rf_type;
1830 break;
1831 case HW_VAR_FWLPS_RF_ON:
1832 {
1833
1834 if (Adapter->pwrctrlpriv.rf_pwrstate == rf_off) {
1835
1836
1837 val[0] = true;
1838 } else {
1839 u32 valRCR;
1840 valRCR = usb_read32(Adapter, REG_RCR);
1841 valRCR &= 0x00070000;
1842 if (valRCR)
1843 val[0] = false;
1844 else
1845 val[0] = true;
1846 }
1847 }
1848 break;
1849 case HW_VAR_CURRENT_ANTENNA:
1850 val[0] = haldata->CurAntenna;
1851 break;
1852 case HW_VAR_EFUSE_BYTES:
1853 *((u16 *)(val)) = haldata->EfuseUsedBytes;
1854 break;
1855 case HW_VAR_APFM_ON_MAC:
1856 *val = haldata->bMacPwrCtrlOn;
1857 break;
1858 case HW_VAR_CHK_HI_QUEUE_EMPTY:
1859 *val = ((usb_read32(Adapter, REG_HGQ_INFORMATION)&0x0000ff00) == 0) ? true : false;
1860 break;
1861 default:
1862 break;
1863 }
1864
1865}
1866
1867
1868
1869
1870
1871static u8
1872GetHalDefVar8188EUsb(
1873 struct adapter *Adapter,
1874 enum hal_def_variable eVariable,
1875 void *pValue
1876 )
1877{
1878 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1879 u8 bResult = _SUCCESS;
1880
1881 switch (eVariable) {
1882 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1883 {
1884 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
1885 struct sta_priv *pstapriv = &Adapter->stapriv;
1886 struct sta_info *psta;
1887 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1888 if (psta)
1889 *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1890 }
1891 break;
1892 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1893 *((u8 *)pValue) = (haldata->AntDivCfg == 0) ? false : true;
1894 break;
1895 case HAL_DEF_CURRENT_ANTENNA:
1896 *((u8 *)pValue) = haldata->CurAntenna;
1897 break;
1898 case HAL_DEF_DRVINFO_SZ:
1899 *((u32 *)pValue) = DRVINFO_SZ;
1900 break;
1901 case HAL_DEF_MAX_RECVBUF_SZ:
1902 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1903 break;
1904 case HAL_DEF_RX_PACKET_OFFSET:
1905 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1906 break;
1907 case HAL_DEF_DBG_DM_FUNC:
1908 *((u32 *)pValue) = haldata->odmpriv.SupportAbility;
1909 break;
1910 case HAL_DEF_RA_DECISION_RATE:
1911 {
1912 u8 MacID = *((u8 *)pValue);
1913 *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&(haldata->odmpriv), MacID);
1914 }
1915 break;
1916 case HAL_DEF_RA_SGI:
1917 {
1918 u8 MacID = *((u8 *)pValue);
1919 *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&(haldata->odmpriv), MacID);
1920 }
1921 break;
1922 case HAL_DEF_PT_PWR_STATUS:
1923 {
1924 u8 MacID = *((u8 *)pValue);
1925 *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(haldata->odmpriv), MacID);
1926 }
1927 break;
1928 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1929 *((u32 *)pValue) = MAX_AMPDU_FACTOR_64K;
1930 break;
1931 case HW_DEF_RA_INFO_DUMP:
1932 {
1933 u8 entry_id = *((u8 *)pValue);
1934 if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
1935 DBG_88E("============ RA status check ===================\n");
1936 DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
1937 entry_id,
1938 haldata->odmpriv.RAInfo[entry_id].RateID,
1939 haldata->odmpriv.RAInfo[entry_id].RAUseRate,
1940 haldata->odmpriv.RAInfo[entry_id].RateSGI,
1941 haldata->odmpriv.RAInfo[entry_id].DecisionRate,
1942 haldata->odmpriv.RAInfo[entry_id].PTStage);
1943 }
1944 }
1945 break;
1946 case HW_DEF_ODM_DBG_FLAG:
1947 {
1948 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
1949 pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
1950 }
1951 break;
1952 case HAL_DEF_DBG_DUMP_RXPKT:
1953 *((u8 *)pValue) = haldata->bDumpRxPkt;
1954 break;
1955 case HAL_DEF_DBG_DUMP_TXPKT:
1956 *((u8 *)pValue) = haldata->bDumpTxPkt;
1957 break;
1958 default:
1959 bResult = _FAIL;
1960 break;
1961 }
1962
1963 return bResult;
1964}
1965
1966
1967
1968
1969
1970static u8 SetHalDefVar8188EUsb(struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue)
1971{
1972 struct hal_data_8188e *haldata = GET_HAL_DATA(Adapter);
1973 u8 bResult = _SUCCESS;
1974
1975 switch (eVariable) {
1976 case HAL_DEF_DBG_DM_FUNC:
1977 {
1978 u8 dm_func = *((u8 *)pValue);
1979 struct odm_dm_struct *podmpriv = &haldata->odmpriv;
1980
1981 if (dm_func == 0) {
1982 podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
1983 DBG_88E("==> Disable all dynamic function...\n");
1984 } else if (dm_func == 1) {
1985 podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
1986 DBG_88E("==> Disable DIG...\n");
1987 } else if (dm_func == 2) {
1988 podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1989 } else if (dm_func == 3) {
1990 podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
1991 DBG_88E("==> Disable tx power tracking...\n");
1992 } else if (dm_func == 5) {
1993 podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
1994 } else if (dm_func == 6) {
1995 if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) {
1996 struct rtw_dig *pDigTable = &podmpriv->DM_DigTable;
1997 pDigTable->CurIGValue = usb_read8(Adapter, 0xc50);
1998 }
1999 podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
2000 DBG_88E("==> Turn on all dynamic function...\n");
2001 }
2002 }
2003 break;
2004 case HAL_DEF_DBG_DUMP_RXPKT:
2005 haldata->bDumpRxPkt = *((u8 *)pValue);
2006 break;
2007 case HAL_DEF_DBG_DUMP_TXPKT:
2008 haldata->bDumpTxPkt = *((u8 *)pValue);
2009 break;
2010 case HW_DEF_FA_CNT_DUMP:
2011 {
2012 u8 bRSSIDump = *((u8 *)pValue);
2013 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2014 if (bRSSIDump)
2015 dm_ocm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT;
2016 else
2017 dm_ocm->DebugComponents = 0;
2018 }
2019 break;
2020 case HW_DEF_ODM_DBG_FLAG:
2021 {
2022 u64 DebugComponents = *((u64 *)pValue);
2023 struct odm_dm_struct *dm_ocm = &(haldata->odmpriv);
2024 dm_ocm->DebugComponents = DebugComponents;
2025 }
2026 break;
2027 default:
2028 bResult = _FAIL;
2029 break;
2030 }
2031
2032 return bResult;
2033}
2034
2035static void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level)
2036{
2037 u8 init_rate = 0;
2038 u8 networkType, raid;
2039 u32 mask, rate_bitmap;
2040 u8 shortGIrate = false;
2041 int supportRateNum = 0;
2042 struct sta_info *psta;
2043 struct hal_data_8188e *haldata = GET_HAL_DATA(adapt);
2044 struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
2045 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2046 struct wlan_bssid_ex *cur_network = &(pmlmeinfo->network);
2047
2048 if (mac_id >= NUM_STA)
2049 return;
2050 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2051 if (psta == NULL)
2052 return;
2053 switch (mac_id) {
2054 case 0:
2055 supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates);
2056 networkType = judge_network_type(adapt, cur_network->SupportedRates, supportRateNum) & 0xf;
2057 raid = networktype_to_raid(networkType);
2058 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2059 mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&(pmlmeinfo->HT_caps)) : 0;
2060 if (support_short_GI(adapt, &(pmlmeinfo->HT_caps)))
2061 shortGIrate = true;
2062 break;
2063 case 1:
2064 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2065 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
2066 networkType = WIRELESS_11B;
2067 else
2068 networkType = WIRELESS_11G;
2069 raid = networktype_to_raid(networkType);
2070 mask = update_basic_rate(cur_network->SupportedRates, supportRateNum);
2071 break;
2072 default:
2073 supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
2074 networkType = judge_network_type(adapt, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf;
2075 raid = networktype_to_raid(networkType);
2076 mask = update_supported_rate(cur_network->SupportedRates, supportRateNum);
2077
2078
2079 break;
2080 }
2081
2082 rate_bitmap = 0x0fffffff;
2083 rate_bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, mac_id, mask, rssi_level);
2084 DBG_88E("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2085 __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
2086
2087 mask &= rate_bitmap;
2088
2089 init_rate = get_highest_rate_idx(mask)&0x3f;
2090
2091 if (haldata->fw_ractrl) {
2092 u8 arg;
2093
2094 arg = mac_id & 0x1f;
2095 arg |= BIT(7);
2096 if (shortGIrate)
2097 arg |= BIT(5);
2098 mask |= ((raid << 28) & 0xf0000000);
2099 DBG_88E("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg);
2100 psta->ra_mask = mask;
2101 mask |= ((raid << 28) & 0xf0000000);
2102
2103
2104 rtl8188e_set_raid_cmd(adapt, mask);
2105 } else {
2106 ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv),
2107 mac_id,
2108 raid,
2109 mask,
2110 shortGIrate
2111 );
2112 }
2113
2114 psta->raid = raid;
2115 psta->init_rate = init_rate;
2116}
2117
2118static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
2119{
2120 u32 value32;
2121 struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv);
2122 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2123 u32 bcn_ctrl_reg = REG_BCN_CTRL;
2124
2125
2126
2127 usb_write16(adapt, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2128 usb_write8(adapt, REG_ATIMWND, 0x02);
2129
2130 _InitBeaconParameters(adapt);
2131
2132 usb_write8(adapt, REG_SLOT, 0x09);
2133
2134 value32 = usb_read32(adapt, REG_TCR);
2135 value32 &= ~TSFRST;
2136 usb_write32(adapt, REG_TCR, value32);
2137
2138 value32 |= TSFRST;
2139 usb_write32(adapt, REG_TCR, value32);
2140
2141
2142 usb_write8(adapt, REG_RXTSF_OFFSET_CCK, 0x50);
2143 usb_write8(adapt, REG_RXTSF_OFFSET_OFDM, 0x50);
2144
2145 _BeaconFunctionEnable(adapt, true, true);
2146
2147 ResumeTxBeacon(adapt);
2148
2149 usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg)|BIT(1));
2150}
2151
2152static void rtl8188eu_init_default_value(struct adapter *adapt)
2153{
2154 struct hal_data_8188e *haldata;
2155 struct pwrctrl_priv *pwrctrlpriv;
2156 u8 i;
2157
2158 haldata = GET_HAL_DATA(adapt);
2159 pwrctrlpriv = &adapt->pwrctrlpriv;
2160
2161
2162 haldata->fw_ractrl = false;
2163 if (!pwrctrlpriv->bkeepfwalive)
2164 haldata->LastHMEBoxNum = 0;
2165
2166
2167 haldata->odmpriv.RFCalibrateInfo.bIQKInitialized = false;
2168 haldata->odmpriv.RFCalibrateInfo.TM_Trigger = 0;
2169 haldata->pwrGroupCnt = 0;
2170 haldata->PGMaxGroup = 13;
2171 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
2172 for (i = 0; i < HP_THERMAL_NUM; i++)
2173 haldata->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
2174}
2175
2176void rtl8188eu_set_hal_ops(struct adapter *adapt)
2177{
2178 struct hal_ops *halfunc = &adapt->HalFunc;
2179
2180
2181 adapt->HalData = kzalloc(sizeof(struct hal_data_8188e), GFP_KERNEL);
2182 if (adapt->HalData == NULL)
2183 DBG_88E("cant not alloc memory for HAL DATA\n");
2184
2185 halfunc->hal_power_on = rtl8188eu_InitPowerOn;
2186 halfunc->hal_init = &rtl8188eu_hal_init;
2187 halfunc->hal_deinit = &rtl8188eu_hal_deinit;
2188
2189 halfunc->inirp_init = &rtl8188eu_inirp_init;
2190 halfunc->inirp_deinit = &rtl8188eu_inirp_deinit;
2191
2192 halfunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
2193
2194 halfunc->init_recv_priv = &rtl8188eu_init_recv_priv;
2195 halfunc->free_recv_priv = &rtl8188eu_free_recv_priv;
2196 halfunc->InitSwLeds = &rtl8188eu_InitSwLeds;
2197 halfunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
2198
2199 halfunc->init_default_value = &rtl8188eu_init_default_value;
2200 halfunc->intf_chip_configure = &rtl8188eu_interface_configure;
2201 halfunc->read_adapter_info = &_ReadAdapterInfo8188EU;
2202
2203 halfunc->SetHwRegHandler = &SetHwReg8188EU;
2204 halfunc->GetHwRegHandler = &GetHwReg8188EU;
2205 halfunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
2206 halfunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
2207
2208 halfunc->UpdateRAMaskHandler = &UpdateHalRAMask8188EUsb;
2209 halfunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
2210
2211 halfunc->hal_xmit = &rtl8188eu_hal_xmit;
2212 halfunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
2213
2214 rtl8188e_set_hal_ops(halfunc);
2215}
2216