1#ifndef _R819XU_PHYREG_H 2#define _R819XU_PHYREG_H 3 4 5#define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 6 7/* Register duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 8 * page 1 9 */ 10#define rPMAC_Reset 0x100 11#define rPMAC_TxStart 0x104 12#define rPMAC_TxLegacySIG 0x108 13#define rPMAC_TxHTSIG1 0x10c 14#define rPMAC_TxHTSIG2 0x110 15#define rPMAC_PHYDebug 0x114 16#define rPMAC_TxPacketNum 0x118 17#define rPMAC_TxIdle 0x11c 18#define rPMAC_TxMACHeader0 0x120 19#define rPMAC_TxMACHeader1 0x124 20#define rPMAC_TxMACHeader2 0x128 21#define rPMAC_TxMACHeader3 0x12c 22#define rPMAC_TxMACHeader4 0x130 23#define rPMAC_TxMACHeader5 0x134 24#define rPMAC_TxDataType 0x138 25#define rPMAC_TxRandomSeed 0x13c 26#define rPMAC_CCKPLCPPreamble 0x140 27#define rPMAC_CCKPLCPHeader 0x144 28#define rPMAC_CCKCRC16 0x148 29#define rPMAC_OFDMRxCRC32OK 0x170 30#define rPMAC_OFDMRxCRC32Er 0x174 31#define rPMAC_OFDMRxParityEr 0x178 32#define rPMAC_OFDMRxCRC8Er 0x17c 33#define rPMAC_CCKCRxRC16Er 0x180 34#define rPMAC_CCKCRxRC32Er 0x184 35#define rPMAC_CCKCRxRC32OK 0x188 36#define rPMAC_TxStatus 0x18c 37 38/* page8 */ 39#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 40#define rFPGA0_TxInfo 0x804 41#define rFPGA0_PSDFunction 0x808 42#define rFPGA0_TxGainStage 0x80c 43#define rFPGA0_RFTiming1 0x810 44#define rFPGA0_RFTiming2 0x814 45/* #define rFPGA0_XC_RFTiming 0x818 46 * #define rFPGA0_XD_RFTiming 0x81c 47 */ 48#define rFPGA0_XA_HSSIParameter1 0x820 49#define rFPGA0_XA_HSSIParameter2 0x824 50#define rFPGA0_XB_HSSIParameter1 0x828 51#define rFPGA0_XB_HSSIParameter2 0x82c 52#define rFPGA0_XC_HSSIParameter1 0x830 53#define rFPGA0_XC_HSSIParameter2 0x834 54#define rFPGA0_XD_HSSIParameter1 0x838 55#define rFPGA0_XD_HSSIParameter2 0x83c 56#define rFPGA0_XA_LSSIParameter 0x840 57#define rFPGA0_XB_LSSIParameter 0x844 58#define rFPGA0_XC_LSSIParameter 0x848 59#define rFPGA0_XD_LSSIParameter 0x84c 60#define rFPGA0_RFWakeUpParameter 0x850 61#define rFPGA0_RFSleepUpParameter 0x854 62#define rFPGA0_XAB_SwitchControl 0x858 63#define rFPGA0_XCD_SwitchControl 0x85c 64#define rFPGA0_XA_RFInterfaceOE 0x860 65#define rFPGA0_XB_RFInterfaceOE 0x864 66#define rFPGA0_XC_RFInterfaceOE 0x868 67#define rFPGA0_XD_RFInterfaceOE 0x86c 68#define rFPGA0_XAB_RFInterfaceSW 0x870 69#define rFPGA0_XCD_RFInterfaceSW 0x874 70#define rFPGA0_XAB_RFParameter 0x878 71#define rFPGA0_XCD_RFParameter 0x87c 72#define rFPGA0_AnalogParameter1 0x880 73#define rFPGA0_AnalogParameter2 0x884 74#define rFPGA0_AnalogParameter3 0x888 75#define rFPGA0_AnalogParameter4 0x88c 76#define rFPGA0_XA_LSSIReadBack 0x8a0 77#define rFPGA0_XB_LSSIReadBack 0x8a4 78#define rFPGA0_XC_LSSIReadBack 0x8a8 79#define rFPGA0_XD_LSSIReadBack 0x8ac 80#define rFPGA0_PSDReport 0x8b4 81#define rFPGA0_XAB_RFInterfaceRB 0x8e0 82#define rFPGA0_XCD_RFInterfaceRB 0x8e4 83 84/* page 9 */ 85#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ 86#define rFPGA1_TxBlock 0x904 87#define rFPGA1_DebugSelect 0x908 88#define rFPGA1_TxInfo 0x90c 89 90/* page a */ 91#define rCCK0_System 0xa00 92#define rCCK0_AFESetting 0xa04 93#define rCCK0_CCA 0xa08 94#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ 95#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 96#define rCCK0_RxHP 0xa14 97#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 98#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 99#define rCCK0_TxFilter1 0xa20 100#define rCCK0_TxFilter2 0xa24 101#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 102#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d */ 103#define rCCK0_TRSSIReport 0xa50 104#define rCCK0_RxReport 0xa54 /* 0xa57 */ 105#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 106#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 107 108/* page c */ 109#define rOFDM0_LSTF 0xc00 110#define rOFDM0_TRxPathEnable 0xc04 111#define rOFDM0_TRMuxPar 0xc08 112#define rOFDM0_TRSWIsolation 0xc0c 113#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 114#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 115#define rOFDM0_XBRxAFE 0xc18 116#define rOFDM0_XBRxIQImbalance 0xc1c 117#define rOFDM0_XCRxAFE 0xc20 118#define rOFDM0_XCRxIQImbalance 0xc24 119#define rOFDM0_XDRxAFE 0xc28 120#define rOFDM0_XDRxIQImbalance 0xc2c 121#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */ 122#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/ 123#define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/ 124#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 125#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 126#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 127#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 128#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 129#define rOFDM0_XAAGCCore1 0xc50 130#define rOFDM0_XAAGCCore2 0xc54 131#define rOFDM0_XBAGCCore1 0xc58 132#define rOFDM0_XBAGCCore2 0xc5c 133#define rOFDM0_XCAGCCore1 0xc60 134#define rOFDM0_XCAGCCore2 0xc64 135#define rOFDM0_XDAGCCore1 0xc68 136#define rOFDM0_XDAGCCore2 0xc6c 137#define rOFDM0_AGCParameter1 0xc70 138#define rOFDM0_AGCParameter2 0xc74 139#define rOFDM0_AGCRSSITable 0xc78 140#define rOFDM0_HTSTFAGC 0xc7c 141#define rOFDM0_XATxIQImbalance 0xc80 142#define rOFDM0_XATxAFE 0xc84 143#define rOFDM0_XBTxIQImbalance 0xc88 144#define rOFDM0_XBTxAFE 0xc8c 145#define rOFDM0_XCTxIQImbalance 0xc90 146#define rOFDM0_XCTxAFE 0xc94 147#define rOFDM0_XDTxIQImbalance 0xc98 148#define rOFDM0_XDTxAFE 0xc9c 149#define rOFDM0_RxHPParameter 0xce0 150#define rOFDM0_TxPseudoNoiseWgt 0xce4 151#define rOFDM0_FrameSync 0xcf0 152#define rOFDM0_DFSReport 0xcf4 153#define rOFDM0_TxCoeff1 0xca4 154#define rOFDM0_TxCoeff2 0xca8 155#define rOFDM0_TxCoeff3 0xcac 156#define rOFDM0_TxCoeff4 0xcb0 157#define rOFDM0_TxCoeff5 0xcb4 158#define rOFDM0_TxCoeff6 0xcb8 159 160 161/* page d */ 162#define rOFDM1_LSTF 0xd00 163#define rOFDM1_TRxPathEnable 0xd04 164#define rOFDM1_CFO 0xd08 165#define rOFDM1_CSI1 0xd10 166#define rOFDM1_SBD 0xd14 167#define rOFDM1_CSI2 0xd18 168#define rOFDM1_CFOTracking 0xd2c 169#define rOFDM1_TRxMesaure1 0xd34 170#define rOFDM1_IntfDet 0xd3c 171#define rOFDM1_PseudoNoiseStateAB 0xd50 172#define rOFDM1_PseudoNoiseStateCD 0xd54 173#define rOFDM1_RxPseudoNoiseWgt 0xd58 174#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 175#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 176 177#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 178#define rOFDM_ShortCFOAB 0xdac 179#define rOFDM_ShortCFOCD 0xdb0 180#define rOFDM_LongCFOAB 0xdb4 181#define rOFDM_LongCFOCD 0xdb8 182#define rOFDM_TailCFOAB 0xdbc 183#define rOFDM_TailCFOCD 0xdc0 184#define rOFDM_PWMeasure1 0xdc4 185#define rOFDM_PWMeasure2 0xdc8 186#define rOFDM_BWReport 0xdcc 187#define rOFDM_AGCReport 0xdd0 188#define rOFDM_RxSNR 0xdd4 189#define rOFDM_RxEVMCSI 0xdd8 190#define rOFDM_SIGReport 0xddc 191 192/* page e */ 193#define rTxAGC_Rate18_06 0xe00 194#define rTxAGC_Rate54_24 0xe04 195#define rTxAGC_CCK_Mcs32 0xe08 196#define rTxAGC_Mcs03_Mcs00 0xe10 197#define rTxAGC_Mcs07_Mcs04 0xe14 198#define rTxAGC_Mcs11_Mcs08 0xe18 199#define rTxAGC_Mcs15_Mcs12 0xe1c 200 201 202/* RF 203 * Zebra1 204 */ 205#define rZebra1_HSSIEnable 0x0 206#define rZebra1_TRxEnable1 0x1 207#define rZebra1_TRxEnable2 0x2 208#define rZebra1_AGC 0x4 209#define rZebra1_ChargePump 0x5 210#define rZebra1_Channel 0x7 211#define rZebra1_TxGain 0x8 212#define rZebra1_TxLPF 0x9 213#define rZebra1_RxLPF 0xb 214#define rZebra1_RxHPFCorner 0xc 215 216/* Zebra4 */ 217#define rGlobalCtrl 0 218#define rRTL8256_TxLPF 19 219#define rRTL8256_RxLPF 11 220 221/* RTL8258 */ 222#define rRTL8258_TxLPF 0x11 223#define rRTL8258_RxLPF 0x13 224#define rRTL8258_RSSILPF 0xa 225 226/* Bit Mask 227 * page-1 228 */ 229#define bBBResetB 0x100 230#define bGlobalResetB 0x200 231#define bOFDMTxStart 0x4 232#define bCCKTxStart 0x8 233#define bCRC32Debug 0x100 234#define bPMACLoopback 0x10 235#define bTxLSIG 0xffffff 236#define bOFDMTxRate 0xf 237#define bOFDMTxReserved 0x10 238#define bOFDMTxLength 0x1ffe0 239#define bOFDMTxParity 0x20000 240#define bTxHTSIG1 0xffffff 241#define bTxHTMCSRate 0x7f 242#define bTxHTBW 0x80 243#define bTxHTLength 0xffff00 244#define bTxHTSIG2 0xffffff 245#define bTxHTSmoothing 0x1 246#define bTxHTSounding 0x2 247#define bTxHTReserved 0x4 248#define bTxHTAggreation 0x8 249#define bTxHTSTBC 0x30 250#define bTxHTAdvanceCoding 0x40 251#define bTxHTShortGI 0x80 252#define bTxHTNumberHT_LTF 0x300 253#define bTxHTCRC8 0x3fc00 254#define bCounterReset 0x10000 255#define bNumOfOFDMTx 0xffff 256#define bNumOfCCKTx 0xffff0000 257#define bTxIdleInterval 0xffff 258#define bOFDMService 0xffff0000 259#define bTxMACHeader 0xffffffff 260#define bTxDataInit 0xff 261#define bTxHTMode 0x100 262#define bTxDataType 0x30000 263#define bTxRandomSeed 0xffffffff 264#define bCCKTxPreamble 0x1 265#define bCCKTxSFD 0xffff0000 266#define bCCKTxSIG 0xff 267#define bCCKTxService 0xff00 268#define bCCKLengthExt 0x8000 269#define bCCKTxLength 0xffff0000 270#define bCCKTxCRC16 0xffff 271#define bCCKTxStatus 0x1 272#define bOFDMTxStatus 0x2 273 274/* page-8 */ 275#define bRFMOD 0x1 276#define bJapanMode 0x2 277#define bCCKTxSC 0x30 278#define bCCKEn 0x1000000 279#define bOFDMEn 0x2000000 280#define bOFDMRxADCPhase 0x10000 281#define bOFDMTxDACPhase 0x40000 282#define bXATxAGC 0x3f 283#define bXBTxAGC 0xf00 284#define bXCTxAGC 0xf000 285#define bXDTxAGC 0xf0000 286#define bPAStart 0xf0000000 287#define bTRStart 0x00f00000 288#define bRFStart 0x0000f000 289#define bBBStart 0x000000f0 290#define bBBCCKStart 0x0000000f 291#define bPAEnd 0xf /* Reg0x814 */ 292#define bTREnd 0x0f000000 293#define bRFEnd 0x000f0000 294#define bCCAMask 0x000000f0 /* T2R */ 295#define bR2RCCAMask 0x00000f00 296#define bHSSI_R2TDelay 0xf8000000 297#define bHSSI_T2RDelay 0xf80000 298#define bContTxHSSI 0x400 /* chane gain at continue Tx */ 299#define bIGFromCCK 0x200 300#define bAGCAddress 0x3f 301#define bRxHPTx 0x7000 302#define bRxHPT2R 0x38000 303#define bRxHPCCKIni 0xc0000 304#define bAGCTxCode 0xc00000 305#define bAGCRxCode 0x300000 306#define b3WireDataLength 0x800 307#define b3WireAddressLength 0x400 308#define b3WireRFPowerDown 0x1 309/* #define bHWSISelect 0x8 */ 310#define b5GPAPEPolarity 0x40000000 311#define b2GPAPEPolarity 0x80000000 312#define bRFSW_TxDefaultAnt 0x3 313#define bRFSW_TxOptionAnt 0x30 314#define bRFSW_RxDefaultAnt 0x300 315#define bRFSW_RxOptionAnt 0x3000 316#define bRFSI_3WireData 0x1 317#define bRFSI_3WireClock 0x2 318#define bRFSI_3WireLoad 0x4 319#define bRFSI_3WireRW 0x8 320#define bRFSI_3Wire 0xf /* 3-wire total control */ 321#define bRFSI_RFENV 0x10 322#define bRFSI_TRSW 0x20 323#define bRFSI_TRSWB 0x40 324#define bRFSI_ANTSW 0x100 325#define bRFSI_ANTSWB 0x200 326#define bRFSI_PAPE 0x400 327#define bRFSI_PAPE5G 0x800 328#define bBandSelect 0x1 329#define bHTSIG2_GI 0x80 330#define bHTSIG2_Smoothing 0x01 331#define bHTSIG2_Sounding 0x02 332#define bHTSIG2_Aggreaton 0x08 333#define bHTSIG2_STBC 0x30 334#define bHTSIG2_AdvCoding 0x40 335#define bHTSIG2_NumOfHTLTF 0x300 336#define bHTSIG2_CRC8 0x3fc 337#define bHTSIG1_MCS 0x7f 338#define bHTSIG1_BandWidth 0x80 339#define bHTSIG1_HTLength 0xffff 340#define bLSIG_Rate 0xf 341#define bLSIG_Reserved 0x10 342#define bLSIG_Length 0x1fffe 343#define bLSIG_Parity 0x20 344#define bCCKRxPhase 0x4 345#define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */ 346#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 347#define bLSSIReadBackData 0xfff 348#define bLSSIReadOKFlag 0x1000 349#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 350#define bRegulator0Standby 0x1 351#define bRegulatorPLLStandby 0x2 352#define bRegulator1Standby 0x4 353#define bPLLPowerUp 0x8 354#define bDPLLPowerUp 0x10 355#define bDA10PowerUp 0x20 356#define bAD7PowerUp 0x200 357#define bDA6PowerUp 0x2000 358#define bXtalPowerUp 0x4000 359#define b40MDClkPowerUP 0x8000 360#define bDA6DebugMode 0x20000 361#define bDA6Swing 0x380000 362#define bADClkPhase 0x4000000 363#define b80MClkDelay 0x18000000 364#define bAFEWatchDogEnable 0x20000000 365#define bXtalCap 0x0f000000 366#define bIntDifClkEnable 0x400 367#define bExtSigClkEnable 0x800 368#define bBandgapMbiasPowerUp 0x10000 369#define bAD11SHGain 0xc0000 370#define bAD11InputRange 0x700000 371#define bAD11OPCurrent 0x3800000 372#define bIPathLoopback 0x4000000 373#define bQPathLoopback 0x8000000 374#define bAFELoopback 0x10000000 375#define bDA10Swing 0x7e0 376#define bDA10Reverse 0x800 377#define bDAClkSource 0x1000 378#define bAD7InputRange 0x6000 379#define bAD7Gain 0x38000 380#define bAD7OutputCMMode 0x40000 381#define bAD7InputCMMode 0x380000 382#define bAD7Current 0xc00000 383#define bRegulatorAdjust 0x7000000 384#define bAD11PowerUpAtTx 0x1 385#define bDA10PSAtTx 0x10 386#define bAD11PowerUpAtRx 0x100 387#define bDA10PSAtRx 0x1000 388 389#define bCCKRxAGCFormat 0x200 390 391#define bPSDFFTSamplepPoint 0xc000 392#define bPSDAverageNum 0x3000 393#define bIQPathControl 0xc00 394#define bPSDFreq 0x3ff 395#define bPSDAntennaPath 0x30 396#define bPSDIQSwitch 0x40 397#define bPSDRxTrigger 0x400000 398#define bPSDTxTrigger 0x80000000 399#define bPSDSineToneScale 0x7f000000 400#define bPSDReport 0xffff 401 402/* page-9 */ 403#define bOFDMTxSC 0x30000000 404#define bCCKTxOn 0x1 405#define bOFDMTxOn 0x2 406#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 407#define bDebugItem 0xff /* reset debug page and LWord */ 408#define bAntL 0x10 409#define bAntNonHT 0x100 410#define bAntHT1 0x1000 411#define bAntHT2 0x10000 412#define bAntHT1S1 0x100000 413#define bAntNonHTS1 0x1000000 414 415/* page-a */ 416#define bCCKBBMode 0x3 417#define bCCKTxPowerSaving 0x80 418#define bCCKRxPowerSaving 0x40 419#define bCCKSideBand 0x10 420#define bCCKScramble 0x8 421#define bCCKAntDiversity 0x8000 422#define bCCKCarrierRecovery 0x4000 423#define bCCKTxRate 0x3000 424#define bCCKDCCancel 0x0800 425#define bCCKISICancel 0x0400 426#define bCCKMatchFilter 0x0200 427#define bCCKEqualizer 0x0100 428#define bCCKPreambleDetect 0x800000 429#define bCCKFastFalseCCA 0x400000 430#define bCCKChEstStart 0x300000 431#define bCCKCCACount 0x080000 432#define bCCKcs_lim 0x070000 433#define bCCKBistMode 0x80000000 434#define bCCKCCAMask 0x40000000 435#define bCCKTxDACPhase 0x4 436#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 437#define bCCKr_cp_mode0 0x0100 438#define bCCKTxDCOffset 0xf0 439#define bCCKRxDCOffset 0xf 440#define bCCKCCAMode 0xc000 441#define bCCKFalseCS_lim 0x3f00 442#define bCCKCS_ratio 0xc00000 443#define bCCKCorgBit_sel 0x300000 444#define bCCKPD_lim 0x0f0000 445#define bCCKNewCCA 0x80000000 446#define bCCKRxHPofIG 0x8000 447#define bCCKRxIG 0x7f00 448#define bCCKLNAPolarity 0x800000 449#define bCCKRx1stGain 0x7f0000 450#define bCCKRFExtend 0x20000000 /* CCK Rx initial gain polarity */ 451#define bCCKRxAGCSatLevel 0x1f000000 452#define bCCKRxAGCSatCount 0xe0 453#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 454#define bCCKFixedRxAGC 0x8000 455/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 456#define bCCKAntennaPolarity 0x2000 457#define bCCKTxFilterType 0x0c00 458#define bCCKRxAGCReportType 0x0300 459#define bCCKRxDAGCEn 0x80000000 460#define bCCKRxDAGCPeriod 0x20000000 461#define bCCKRxDAGCSatLevel 0x1f000000 462#define bCCKTimingRecovery 0x800000 463#define bCCKTxC0 0x3f0000 464#define bCCKTxC1 0x3f000000 465#define bCCKTxC2 0x3f 466#define bCCKTxC3 0x3f00 467#define bCCKTxC4 0x3f0000 468#define bCCKTxC5 0x3f000000 469#define bCCKTxC6 0x3f 470#define bCCKTxC7 0x3f00 471#define bCCKDebugPort 0xff0000 472#define bCCKDACDebug 0x0f000000 473#define bCCKFalseAlarmEnable 0x8000 474#define bCCKFalseAlarmRead 0x4000 475#define bCCKTRSSI 0x7f 476#define bCCKRxAGCReport 0xfe 477#define bCCKRxReport_AntSel 0x80000000 478#define bCCKRxReport_MFOff 0x40000000 479#define bCCKRxRxReport_SQLoss 0x20000000 480#define bCCKRxReport_Pktloss 0x10000000 481#define bCCKRxReport_Lockedbit 0x08000000 482#define bCCKRxReport_RateError 0x04000000 483#define bCCKRxReport_RxRate 0x03000000 484#define bCCKRxFACounterLower 0xff 485#define bCCKRxFACounterUpper 0xff000000 486#define bCCKRxHPAGCStart 0xe000 487#define bCCKRxHPAGCFinal 0x1c00 488 489#define bCCKRxFalseAlarmEnable 0x8000 490#define bCCKFACounterFreeze 0x4000 491 492#define bCCKTxPathSel 0x10000000 493#define bCCKDefaultRxPath 0xc000000 494#define bCCKOptionRxPath 0x3000000 495 496/* page c */ 497#define bNumOfSTF 0x3 498#define bShift_L 0xc0 499#define bGI_TH 0xc 500#define bRxPathA 0x1 501#define bRxPathB 0x2 502#define bRxPathC 0x4 503#define bRxPathD 0x8 504#define bTxPathA 0x1 505#define bTxPathB 0x2 506#define bTxPathC 0x4 507#define bTxPathD 0x8 508#define bTRSSIFreq 0x200 509#define bADCBackoff 0x3000 510#define bDFIRBackoff 0xc000 511#define bTRSSILatchPhase 0x10000 512#define bRxIDCOffset 0xff 513#define bRxQDCOffset 0xff00 514#define bRxDFIRMode 0x1800000 515#define bRxDCNFType 0xe000000 516#define bRXIQImb_A 0x3ff 517#define bRXIQImb_B 0xfc00 518#define bRXIQImb_C 0x3f0000 519#define bRXIQImb_D 0xffc00000 520#define bDC_dc_Notch 0x60000 521#define bRxNBINotch 0x1f000000 522#define bPD_TH 0xf 523#define bPD_TH_Opt2 0xc000 524#define bPWED_TH 0x700 525#define bIfMF_Win_L 0x800 526#define bPD_Option 0x1000 527#define bMF_Win_L 0xe000 528#define bBW_Search_L 0x30000 529#define bwin_enh_L 0xc0000 530#define bBW_TH 0x700000 531#define bED_TH2 0x3800000 532#define bBW_option 0x4000000 533#define bRatio_TH 0x18000000 534#define bWindow_L 0xe0000000 535#define bSBD_Option 0x1 536#define bFrame_TH 0x1c 537#define bFS_Option 0x60 538#define bDC_Slope_check 0x80 539#define bFGuard_Counter_DC_L 0xe00 540#define bFrame_Weight_Short 0x7000 541#define bSub_Tune 0xe00000 542#define bFrame_DC_Length 0xe000000 543#define bSBD_start_offset 0x30000000 544#define bFrame_TH_2 0x7 545#define bFrame_GI2_TH 0x38 546#define bGI2_Sync_en 0x40 547#define bSarch_Short_Early 0x300 548#define bSarch_Short_Late 0xc00 549#define bSarch_GI2_Late 0x70000 550#define bCFOAntSum 0x1 551#define bCFOAcc 0x2 552#define bCFOStartOffset 0xc 553#define bCFOLookBack 0x70 554#define bCFOSumWeight 0x80 555#define bDAGCEnable 0x10000 556#define bTXIQImb_A 0x3ff 557#define bTXIQImb_B 0xfc00 558#define bTXIQImb_C 0x3f0000 559#define bTXIQImb_D 0xffc00000 560#define bTxIDCOffset 0xff 561#define bTxQDCOffset 0xff00 562#define bTxDFIRMode 0x10000 563#define bTxPesudoNoiseOn 0x4000000 564#define bTxPesudoNoise_A 0xff 565#define bTxPesudoNoise_B 0xff00 566#define bTxPesudoNoise_C 0xff0000 567#define bTxPesudoNoise_D 0xff000000 568#define bCCADropOption 0x20000 569#define bCCADropThres 0xfff00000 570#define bEDCCA_H 0xf 571#define bEDCCA_L 0xf0 572#define bLambda_ED 0x300 573#define bRxInitialGain 0x7f 574#define bRxAntDivEn 0x80 575#define bRxAGCAddressForLNA 0x7f00 576#define bRxHighPowerFlow 0x8000 577#define bRxAGCFreezeThres 0xc0000 578#define bRxFreezeStep_AGC1 0x300000 579#define bRxFreezeStep_AGC2 0xc00000 580#define bRxFreezeStep_AGC3 0x3000000 581#define bRxFreezeStep_AGC0 0xc000000 582#define bRxRssi_Cmp_En 0x10000000 583#define bRxQuickAGCEn 0x20000000 584#define bRxAGCFreezeThresMode 0x40000000 585#define bRxOverFlowCheckType 0x80000000 586#define bRxAGCShift 0x7f 587#define bTRSW_Tri_Only 0x80 588#define bPowerThres 0x300 589#define bRxAGCEn 0x1 590#define bRxAGCTogetherEn 0x2 591#define bRxAGCMin 0x4 592#define bRxHP_Ini 0x7 593#define bRxHP_TRLNA 0x70 594#define bRxHP_RSSI 0x700 595#define bRxHP_BBP1 0x7000 596#define bRxHP_BBP2 0x70000 597#define bRxHP_BBP3 0x700000 598#define bRSSI_H 0x7f0000 /* the threshold for high power */ 599#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 600#define bRxSettle_TRSW 0x7 601#define bRxSettle_LNA 0x38 602#define bRxSettle_RSSI 0x1c0 603#define bRxSettle_BBP 0xe00 604#define bRxSettle_RxHP 0x7000 605#define bRxSettle_AntSW_RSSI 0x38000 606#define bRxSettle_AntSW 0xc0000 607#define bRxProcessTime_DAGC 0x300000 608#define bRxSettle_HSSI 0x400000 609#define bRxProcessTime_BBPPW 0x800000 610#define bRxAntennaPowerShift 0x3000000 611#define bRSSITableSelect 0xc000000 612#define bRxHP_Final 0x7000000 613#define bRxHTSettle_BBP 0x7 614#define bRxHTSettle_HSSI 0x8 615#define bRxHTSettle_RxHP 0x70 616#define bRxHTSettle_BBPPW 0x80 617#define bRxHTSettle_Idle 0x300 618#define bRxHTSettle_Reserved 0x1c00 619#define bRxHTRxHPEn 0x8000 620#define bRxHTAGCFreezeThres 0x30000 621#define bRxHTAGCTogetherEn 0x40000 622#define bRxHTAGCMin 0x80000 623#define bRxHTAGCEn 0x100000 624#define bRxHTDAGCEn 0x200000 625#define bRxHTRxHP_BBP 0x1c00000 626#define bRxHTRxHP_Final 0xe0000000 627#define bRxPWRatioTH 0x3 628#define bRxPWRatioEn 0x4 629#define bRxMFHold 0x3800 630#define bRxPD_Delay_TH1 0x38 631#define bRxPD_Delay_TH2 0x1c0 632#define bRxPD_DC_COUNT_MAX 0x600 633/* #define bRxMF_Hold 0x3800 */ 634#define bRxPD_Delay_TH 0x8000 635#define bRxProcess_Delay 0xf0000 636#define bRxSearchrange_GI2_Early 0x700000 637#define bRxFrame_Guard_Counter_L 0x3800000 638#define bRxSGI_Guard_L 0xc000000 639#define bRxSGI_Search_L 0x30000000 640#define bRxSGI_TH 0xc0000000 641#define bDFSCnt0 0xff 642#define bDFSCnt1 0xff00 643#define bDFSFlag 0xf0000 644 645#define bMFWeightSum 0x300000 646#define bMinIdxTH 0x7f000000 647 648#define bDAFormat 0x40000 649 650#define bTxChEmuEnable 0x01000000 651 652#define bTRSWIsolation_A 0x7f 653#define bTRSWIsolation_B 0x7f00 654#define bTRSWIsolation_C 0x7f0000 655#define bTRSWIsolation_D 0x7f000000 656 657#define bExtLNAGain 0x7c00 658 659/* page d */ 660#define bSTBCEn 0x4 661#define bAntennaMapping 0x10 662#define bNss 0x20 663#define bCFOAntSumD 0x200 664#define bPHYCounterReset 0x8000000 665#define bCFOReportGet 0x4000000 666#define bOFDMContinueTx 0x10000000 667#define bOFDMSingleCarrier 0x20000000 668#define bOFDMSingleTone 0x40000000 669/* #define bRxPath1 0x01 670 * #define bRxPath2 0x02 671 * #define bRxPath3 0x04 672 * #define bRxPath4 0x08 673 * #define bTxPath1 0x10 674 * #define bTxPath2 0x20 675 */ 676#define bHTDetect 0x100 677#define bCFOEn 0x10000 678#define bCFOValue 0xfff00000 679#define bSigTone_Re 0x3f 680#define bSigTone_Im 0x7f00 681#define bCounter_CCA 0xffff 682#define bCounter_ParityFail 0xffff0000 683#define bCounter_RateIllegal 0xffff 684#define bCounter_CRC8Fail 0xffff0000 685#define bCounter_MCSNoSupport 0xffff 686#define bCounter_FastSync 0xffff 687#define bShortCFO 0xfff 688#define bShortCFOTLength 12 /* total */ 689#define bShortCFOFLength 11 /* fraction */ 690#define bLongCFO 0x7ff 691#define bLongCFOTLength 11 692#define bLongCFOFLength 11 693#define bTailCFO 0x1fff 694#define bTailCFOTLength 13 695#define bTailCFOFLength 12 696 697#define bmax_en_pwdB 0xffff 698#define bCC_power_dB 0xffff0000 699#define bnoise_pwdB 0xffff 700#define bPowerMeasTLength 10 701#define bPowerMeasFLength 3 702#define bRx_HT_BW 0x1 703#define bRxSC 0x6 704#define bRx_HT 0x8 705 706#define bNB_intf_det_on 0x1 707#define bIntf_win_len_cfg 0x30 708#define bNB_Intf_TH_cfg 0x1c0 709 710#define bRFGain 0x3f 711#define bTableSel 0x40 712#define bTRSW 0x80 713 714#define bRxSNR_A 0xff 715#define bRxSNR_B 0xff00 716#define bRxSNR_C 0xff0000 717#define bRxSNR_D 0xff000000 718#define bSNREVMTLength 8 719#define bSNREVMFLength 1 720 721#define bCSI1st 0xff 722#define bCSI2nd 0xff00 723#define bRxEVM1st 0xff0000 724#define bRxEVM2nd 0xff000000 725 726#define bSIGEVM 0xff 727#define bPWDB 0xff00 728#define bSGIEN 0x10000 729 730#define bSFactorQAM1 0xf 731#define bSFactorQAM2 0xf0 732#define bSFactorQAM3 0xf00 733#define bSFactorQAM4 0xf000 734#define bSFactorQAM5 0xf0000 735#define bSFactorQAM6 0xf0000 736#define bSFactorQAM7 0xf00000 737#define bSFactorQAM8 0xf000000 738#define bSFactorQAM9 0xf0000000 739#define bCSIScheme 0x100000 740 741#define bNoiseLvlTopSet 0x3 742#define bChSmooth 0x4 743#define bChSmoothCfg1 0x38 744#define bChSmoothCfg2 0x1c0 745#define bChSmoothCfg3 0xe00 746#define bChSmoothCfg4 0x7000 747#define bMRCMode 0x800000 748#define bTHEVMCfg 0x7000000 749 750#define bLoopFitType 0x1 751#define bUpdCFO 0x40 752#define bUpdCFOOffData 0x80 753#define bAdvUpdCFO 0x100 754#define bAdvTimeCtrl 0x800 755#define bUpdClko 0x1000 756#define bFC 0x6000 757#define bTrackingMode 0x8000 758#define bPhCmpEnable 0x10000 759#define bUpdClkoLTF 0x20000 760#define bComChCFO 0x40000 761#define bCSIEstiMode 0x80000 762#define bAdvUpdEqz 0x100000 763#define bUChCfg 0x7000000 764#define bUpdEqz 0x8000000 765 766/* page e */ 767#define bTxAGCRate18_06 0x7f7f7f7f 768#define bTxAGCRate54_24 0x7f7f7f7f 769#define bTxAGCRateMCS32 0x7f 770#define bTxAGCRateCCK 0x7f00 771#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 772#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 773#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 774#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 775 776 777/* Rx Pseduo noise */ 778#define bRxPesudoNoiseOn 0x20000000 779#define bRxPesudoNoise_A 0xff 780#define bRxPesudoNoise_B 0xff00 781#define bRxPesudoNoise_C 0xff0000 782#define bRxPesudoNoise_D 0xff000000 783#define bPesudoNoiseState_A 0xffff 784#define bPesudoNoiseState_B 0xffff0000 785#define bPesudoNoiseState_C 0xffff 786#define bPesudoNoiseState_D 0xffff0000 787 788/* RF 789 * Zebra1 790 */ 791#define bZebra1_HSSIEnable 0x8 792#define bZebra1_TRxControl 0xc00 793#define bZebra1_TRxGainSetting 0x07f 794#define bZebra1_RxCorner 0xc00 795#define bZebra1_TxChargePump 0x38 796#define bZebra1_RxChargePump 0x7 797#define bZebra1_ChannelNum 0xf80 798#define bZebra1_TxLPFBW 0x400 799#define bZebra1_RxLPFBW 0x600 800 801/* Zebra4 */ 802#define bRTL8256RegModeCtrl1 0x100 803#define bRTL8256RegModeCtrl0 0x40 804#define bRTL8256_TxLPFBW 0x18 805#define bRTL8256_RxLPFBW 0x600 806 807/* RTL8258 */ 808#define bRTL8258_TxLPFBW 0xc 809#define bRTL8258_RxLPFBW 0xc00 810#define bRTL8258_RSSILPFBW 0xc0 811 812/* byte endable for sb_write */ 813#define bByte0 0x1 814#define bByte1 0x2 815#define bByte2 0x4 816#define bByte3 0x8 817#define bWord0 0x3 818#define bWord1 0xc 819#define bDWord 0xf 820 821/* for PutRegsetting & GetRegSetting BitMask */ 822#define bMaskByte0 0xff 823#define bMaskByte1 0xff00 824#define bMaskByte2 0xff0000 825#define bMaskByte3 0xff000000 826#define bMaskHWord 0xffff0000 827#define bMaskLWord 0x0000ffff 828#define bMaskDWord 0xffffffff 829 830/* for PutRFRegsetting & GetRFRegSetting BitMask */ 831#define bMask12Bits 0xfff 832 833#define bEnable 0x1 834#define bDisable 0x0 835 836#define LeftAntenna 0x0 837#define RightAntenna 0x1 838 839#define tCheckTxStatus 500 /* 500ms */ 840#define tUpdateRxCounter 100 /* 100ms */ 841 842#define rateCCK 0 843#define rateOFDM 1 844#define rateHT 2 845 846/* define Register-End */ 847#define bPMAC_End 0x1ff 848#define bFPGAPHY0_End 0x8ff 849#define bFPGAPHY1_End 0x9ff 850#define bCCKPHY0_End 0xaff 851#define bOFDMPHY0_End 0xcff 852#define bOFDMPHY1_End 0xdff 853 854/* define max debug item in each debug page 855 * #define bMaxItem_FPGA_PHY0 0x9 856 * #define bMaxItem_FPGA_PHY1 0x3 857 * #define bMaxItem_PHY_11B 0x16 858 * #define bMaxItem_OFDM_PHY0 0x29 859 * #define bMaxItem_OFDM_PHY1 0x0 860 */ 861 862#define bPMACControl 0x0 863#define bWMACControl 0x1 864#define bWNICControl 0x2 865 866#define PathA 0x0 867#define PathB 0x1 868#define PathC 0x2 869#define PathD 0x3 870 871#define rRTL8256RxMixerPole 0xb 872#define bZebraRxMixerPole 0x6 873#define rRTL8256TxBBOPBias 0x9 874#define bRTL8256TxBBOPBias 0x400 875#define rRTL8256TxBBBW 19 876#define bRTL8256TxBBBW 0x18 877 878#endif /* __INC_HAL8190PCIPHYREG_H */ 879