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23#include <linux/blkdev.h>
24#include <linux/kthread.h>
25#include <linux/sched.h>
26#include <linux/vmalloc.h>
27
28#include "rtsx.h"
29#include "rtsx_transport.h"
30#include "rtsx_scsi.h"
31#include "rtsx_card.h"
32#include "ms.h"
33
34static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
35{
36 struct ms_info *ms_card = &(chip->ms_card);
37
38 ms_card->err_code = err_code;
39}
40
41static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
42{
43 struct ms_info *ms_card = &(chip->ms_card);
44
45 return (ms_card->err_code == err_code);
46}
47
48static int ms_parse_err_code(struct rtsx_chip *chip)
49{
50 TRACE_RET(chip, STATUS_FAIL);
51}
52
53static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
54 u8 tpc, u8 cnt, u8 cfg)
55{
56 struct ms_info *ms_card = &(chip->ms_card);
57 int retval;
58 u8 *ptr;
59
60 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc);
61
62 rtsx_init_cmd(chip);
63
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
65 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
66 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
67 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
68 0x01, PINGPONG_BUFFER);
69
70 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
71 0xFF, MS_TRANSFER_START | trans_mode);
72 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
73 MS_TRANSFER_END, MS_TRANSFER_END);
74
75 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
76
77 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
78 if (retval < 0) {
79 rtsx_clear_ms_error(chip);
80 ms_set_err_code(chip, MS_TO_ERROR);
81 TRACE_RET(chip, ms_parse_err_code(chip));
82 }
83
84 ptr = rtsx_get_cmd_data(chip) + 1;
85
86 if (!(tpc & 0x08)) {
87 if (*ptr & MS_CRC16_ERR) {
88 ms_set_err_code(chip, MS_CRC16_ERROR);
89 TRACE_RET(chip, ms_parse_err_code(chip));
90 }
91 } else {
92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
94 ms_set_err_code(chip, MS_CMD_NK);
95 TRACE_RET(chip, ms_parse_err_code(chip));
96 }
97 }
98 }
99
100 if (*ptr & MS_RDY_TIMEOUT) {
101 rtsx_clear_ms_error(chip);
102 ms_set_err_code(chip, MS_TO_ERROR);
103 TRACE_RET(chip, ms_parse_err_code(chip));
104 }
105
106 return STATUS_SUCCESS;
107}
108
109static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
110 u8 tpc, u16 sec_cnt, u8 cfg, int mode_2k,
111 int use_sg, void *buf, int buf_len)
112{
113 int retval;
114 u8 val, err_code = 0;
115 enum dma_data_direction dir;
116
117 if (!buf || !buf_len)
118 TRACE_RET(chip, STATUS_FAIL);
119
120 if (trans_mode == MS_TM_AUTO_READ) {
121 dir = DMA_FROM_DEVICE;
122 err_code = MS_FLASH_READ_ERROR;
123 } else if (trans_mode == MS_TM_AUTO_WRITE) {
124 dir = DMA_TO_DEVICE;
125 err_code = MS_FLASH_WRITE_ERROR;
126 } else {
127 TRACE_RET(chip, STATUS_FAIL);
128 }
129
130 rtsx_init_cmd(chip);
131
132 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
133 rtsx_add_cmd(chip, WRITE_REG_CMD,
134 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
135 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
136 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
137
138 if (mode_2k) {
139 rtsx_add_cmd(chip, WRITE_REG_CMD,
140 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
141 } else {
142 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
143 }
144
145 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
146
147 rtsx_add_cmd(chip, WRITE_REG_CMD,
148 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
149 rtsx_add_cmd(chip, CHECK_REG_CMD,
150 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
151
152 rtsx_send_cmd_no_wait(chip);
153
154 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
155 use_sg, dir, chip->mspro_timeout);
156 if (retval < 0) {
157 ms_set_err_code(chip, err_code);
158 if (retval == -ETIMEDOUT)
159 retval = STATUS_TIMEDOUT;
160 else
161 retval = STATUS_FAIL;
162
163 TRACE_RET(chip, retval);
164 }
165
166 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
167 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
168 TRACE_RET(chip, STATUS_FAIL);
169
170 return STATUS_SUCCESS;
171}
172
173static int ms_write_bytes(struct rtsx_chip *chip,
174 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
175{
176 struct ms_info *ms_card = &(chip->ms_card);
177 int retval, i;
178
179 if (!data || (data_len < cnt))
180 TRACE_RET(chip, STATUS_ERROR);
181
182 rtsx_init_cmd(chip);
183
184 for (i = 0; i < cnt; i++) {
185 rtsx_add_cmd(chip, WRITE_REG_CMD,
186 PPBUF_BASE2 + i, 0xFF, data[i]);
187 }
188 if (cnt % 2)
189 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
190
191 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
192 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
193 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
194 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
195 0x01, PINGPONG_BUFFER);
196
197 rtsx_add_cmd(chip, WRITE_REG_CMD,
198 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
199 rtsx_add_cmd(chip, CHECK_REG_CMD,
200 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
201
202 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
203 if (retval < 0) {
204 u8 val = 0;
205
206 rtsx_read_register(chip, MS_TRANS_CFG, &val);
207 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val);
208
209 rtsx_clear_ms_error(chip);
210
211 if (!(tpc & 0x08)) {
212 if (val & MS_CRC16_ERR) {
213 ms_set_err_code(chip, MS_CRC16_ERROR);
214 TRACE_RET(chip, ms_parse_err_code(chip));
215 }
216 } else {
217 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
218 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
219 ms_set_err_code(chip, MS_CMD_NK);
220 TRACE_RET(chip,
221 ms_parse_err_code(chip));
222 }
223 }
224 }
225
226 if (val & MS_RDY_TIMEOUT) {
227 ms_set_err_code(chip, MS_TO_ERROR);
228 TRACE_RET(chip, ms_parse_err_code(chip));
229 }
230
231 ms_set_err_code(chip, MS_TO_ERROR);
232 TRACE_RET(chip, ms_parse_err_code(chip));
233 }
234
235 return STATUS_SUCCESS;
236}
237
238static int ms_read_bytes(struct rtsx_chip *chip,
239 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
240{
241 struct ms_info *ms_card = &(chip->ms_card);
242 int retval, i;
243 u8 *ptr;
244
245 if (!data)
246 TRACE_RET(chip, STATUS_ERROR);
247
248 rtsx_init_cmd(chip);
249
250 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
251 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
252 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
253 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
254 0x01, PINGPONG_BUFFER);
255
256 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
257 MS_TRANSFER_START | MS_TM_READ_BYTES);
258 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
259 MS_TRANSFER_END, MS_TRANSFER_END);
260
261 for (i = 0; i < data_len - 1; i++)
262 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
263
264 if (data_len % 2)
265 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
266 else
267 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
268 0, 0);
269
270 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
271 if (retval < 0) {
272 u8 val = 0;
273
274 rtsx_read_register(chip, MS_TRANS_CFG, &val);
275 rtsx_clear_ms_error(chip);
276
277 if (!(tpc & 0x08)) {
278 if (val & MS_CRC16_ERR) {
279 ms_set_err_code(chip, MS_CRC16_ERROR);
280 TRACE_RET(chip, ms_parse_err_code(chip));
281 }
282 } else {
283 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
284 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
285 ms_set_err_code(chip, MS_CMD_NK);
286 TRACE_RET(chip,
287 ms_parse_err_code(chip));
288 }
289 }
290 }
291
292 if (val & MS_RDY_TIMEOUT) {
293 ms_set_err_code(chip, MS_TO_ERROR);
294 TRACE_RET(chip, ms_parse_err_code(chip));
295 }
296
297 ms_set_err_code(chip, MS_TO_ERROR);
298 TRACE_RET(chip, ms_parse_err_code(chip));
299 }
300
301 ptr = rtsx_get_cmd_data(chip) + 1;
302
303 for (i = 0; i < data_len; i++)
304 data[i] = ptr[i];
305
306 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
307 dev_dbg(rtsx_dev(chip), "Read format progress:\n");
308 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr,
309 cnt);
310 }
311
312 return STATUS_SUCCESS;
313}
314
315static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
316 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
317{
318 int retval, i;
319 u8 data[4];
320
321 data[0] = read_start;
322 data[1] = read_cnt;
323 data[2] = write_start;
324 data[3] = write_cnt;
325
326 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
327 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
328 NO_WAIT_INT, data, 4);
329 if (retval == STATUS_SUCCESS)
330 return STATUS_SUCCESS;
331 rtsx_clear_ms_error(chip);
332 }
333
334 TRACE_RET(chip, STATUS_FAIL);
335}
336
337static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
338{
339 u8 data[2];
340
341 data[0] = cmd;
342 data[1] = 0;
343
344 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
345}
346
347static int ms_set_init_para(struct rtsx_chip *chip)
348{
349 struct ms_info *ms_card = &(chip->ms_card);
350 int retval;
351
352 if (CHK_HG8BIT(ms_card)) {
353 if (chip->asic_code)
354 ms_card->ms_clock = chip->asic_ms_hg_clk;
355 else
356 ms_card->ms_clock = chip->fpga_ms_hg_clk;
357
358 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
359 if (chip->asic_code)
360 ms_card->ms_clock = chip->asic_ms_4bit_clk;
361 else
362 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
363
364 } else {
365 if (chip->asic_code)
366 ms_card->ms_clock = chip->asic_ms_1bit_clk;
367 else
368 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
369 }
370
371 retval = switch_clock(chip, ms_card->ms_clock);
372 if (retval != STATUS_SUCCESS)
373 TRACE_RET(chip, STATUS_FAIL);
374
375 retval = select_card(chip, MS_CARD);
376 if (retval != STATUS_SUCCESS)
377 TRACE_RET(chip, STATUS_FAIL);
378
379 return STATUS_SUCCESS;
380}
381
382static int ms_switch_clock(struct rtsx_chip *chip)
383{
384 struct ms_info *ms_card = &(chip->ms_card);
385 int retval;
386
387 retval = select_card(chip, MS_CARD);
388 if (retval != STATUS_SUCCESS)
389 TRACE_RET(chip, STATUS_FAIL);
390
391 retval = switch_clock(chip, ms_card->ms_clock);
392 if (retval != STATUS_SUCCESS)
393 TRACE_RET(chip, STATUS_FAIL);
394
395 return STATUS_SUCCESS;
396}
397
398static int ms_pull_ctl_disable(struct rtsx_chip *chip)
399{
400 if (CHECK_PID(chip, 0x5208)) {
401 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
402 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
403 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
404 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
405 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
406 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
407 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
408 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
409 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
410 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
411 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,
412 MS_D5_PD | MS_D4_PD);
413 } else if (CHECK_PID(chip, 0x5288)) {
414 if (CHECK_BARO_PKG(chip, QFN)) {
415 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
416 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
417 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
418 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
419 }
420 }
421
422 return STATUS_SUCCESS;
423}
424
425static int ms_pull_ctl_enable(struct rtsx_chip *chip)
426{
427 int retval;
428
429 rtsx_init_cmd(chip);
430
431 if (CHECK_PID(chip, 0x5208)) {
432 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
433 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
434 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
435 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
436 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
437 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
438 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
439 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
440 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
441 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
442 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
443 MS_D5_PD | MS_D4_PD);
444 } else if (CHECK_PID(chip, 0x5288)) {
445 if (CHECK_BARO_PKG(chip, QFN)) {
446 rtsx_add_cmd(chip, WRITE_REG_CMD,
447 CARD_PULL_CTL1, 0xFF, 0x55);
448 rtsx_add_cmd(chip, WRITE_REG_CMD,
449 CARD_PULL_CTL2, 0xFF, 0x45);
450 rtsx_add_cmd(chip, WRITE_REG_CMD,
451 CARD_PULL_CTL3, 0xFF, 0x4B);
452 rtsx_add_cmd(chip, WRITE_REG_CMD,
453 CARD_PULL_CTL4, 0xFF, 0x29);
454 }
455 }
456
457 retval = rtsx_send_cmd(chip, MS_CARD, 100);
458 if (retval < 0)
459 TRACE_RET(chip, STATUS_FAIL);
460
461 return STATUS_SUCCESS;
462}
463
464static int ms_prepare_reset(struct rtsx_chip *chip)
465{
466 struct ms_info *ms_card = &(chip->ms_card);
467 int retval;
468 u8 oc_mask = 0;
469
470 ms_card->ms_type = 0;
471 ms_card->check_ms_flow = 0;
472 ms_card->switch_8bit_fail = 0;
473 ms_card->delay_write.delay_write_flag = 0;
474
475 ms_card->pro_under_formatting = 0;
476
477 retval = ms_power_off_card3v3(chip);
478 if (retval != STATUS_SUCCESS)
479 TRACE_RET(chip, STATUS_FAIL);
480
481 if (!chip->ft2_fast_mode)
482 wait_timeout(250);
483
484 retval = enable_card_clock(chip, MS_CARD);
485 if (retval != STATUS_SUCCESS)
486 TRACE_RET(chip, STATUS_FAIL);
487
488 if (chip->asic_code) {
489 retval = ms_pull_ctl_enable(chip);
490 if (retval != STATUS_SUCCESS)
491 TRACE_RET(chip, STATUS_FAIL);
492 } else {
493 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
494 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
495 }
496
497 if (!chip->ft2_fast_mode) {
498 retval = card_power_on(chip, MS_CARD);
499 if (retval != STATUS_SUCCESS)
500 TRACE_RET(chip, STATUS_FAIL);
501
502 wait_timeout(150);
503
504#ifdef SUPPORT_OCP
505 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
506 oc_mask = MS_OC_NOW | MS_OC_EVER;
507 else
508 oc_mask = SD_OC_NOW | SD_OC_EVER;
509
510 if (chip->ocp_stat & oc_mask) {
511 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
512 chip->ocp_stat);
513 TRACE_RET(chip, STATUS_FAIL);
514 }
515#endif
516 }
517
518 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
519
520 if (chip->asic_code) {
521 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
522 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
523 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
524 } else {
525 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
526 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
527 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
528 }
529 RTSX_WRITE_REG(chip, MS_TRANS_CFG,
530 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
531 RTSX_WRITE_REG(chip, CARD_STOP,
532 MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
533
534 retval = ms_set_init_para(chip);
535 if (retval != STATUS_SUCCESS)
536 TRACE_RET(chip, STATUS_FAIL);
537
538 return STATUS_SUCCESS;
539}
540
541static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
542{
543 struct ms_info *ms_card = &(chip->ms_card);
544 int retval, i;
545 u8 val;
546
547 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
548 if (retval != STATUS_SUCCESS)
549 TRACE_RET(chip, STATUS_FAIL);
550
551 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
552 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
553 6, NO_WAIT_INT);
554 if (retval == STATUS_SUCCESS)
555 break;
556 }
557 if (i == MS_MAX_RETRY_COUNT)
558 TRACE_RET(chip, STATUS_FAIL);
559
560 RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
561 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);
562 if (val != 0x01) {
563 if (val != 0x02)
564 ms_card->check_ms_flow = 1;
565
566 TRACE_RET(chip, STATUS_FAIL);
567 }
568
569 RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
570 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);
571 if (val != 0) {
572 ms_card->check_ms_flow = 1;
573 TRACE_RET(chip, STATUS_FAIL);
574 }
575
576 RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
577 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);
578 if (val == 0) {
579 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
580 if (val & WRT_PRTCT)
581 chip->card_wp |= MS_CARD;
582 else
583 chip->card_wp &= ~MS_CARD;
584
585 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
586 chip->card_wp |= MS_CARD;
587 } else {
588 ms_card->check_ms_flow = 1;
589 TRACE_RET(chip, STATUS_FAIL);
590 }
591
592 ms_card->ms_type |= TYPE_MSPRO;
593
594 RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
595 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);
596 if (val == 0) {
597 ms_card->ms_type &= 0x0F;
598 } else if (val == 7) {
599 if (switch_8bit_bus)
600 ms_card->ms_type |= MS_HG;
601 else
602 ms_card->ms_type &= 0x0F;
603
604 } else {
605 TRACE_RET(chip, STATUS_FAIL);
606 }
607
608 return STATUS_SUCCESS;
609}
610
611static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
612{
613 int retval, i, k;
614 u8 val;
615
616
617 k = 0;
618 do {
619 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
620 ms_set_err_code(chip, MS_NO_CARD);
621 TRACE_RET(chip, STATUS_FAIL);
622 }
623
624 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
625 retval = ms_read_bytes(chip, GET_INT, 1,
626 NO_WAIT_INT, &val, 1);
627 if (retval == STATUS_SUCCESS)
628 break;
629 }
630 if (i == MS_MAX_RETRY_COUNT)
631 TRACE_RET(chip, STATUS_FAIL);
632
633 if (k > 100)
634 TRACE_RET(chip, STATUS_FAIL);
635
636 k++;
637 wait_timeout(100);
638 } while (!(val & INT_REG_CED));
639
640 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
641 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
642 if (retval == STATUS_SUCCESS)
643 break;
644 }
645 if (i == MS_MAX_RETRY_COUNT)
646 TRACE_RET(chip, STATUS_FAIL);
647
648 if (val & INT_REG_ERR) {
649 if (val & INT_REG_CMDNK)
650 chip->card_wp |= (MS_CARD);
651 else
652 TRACE_RET(chip, STATUS_FAIL);
653 }
654
655
656 return STATUS_SUCCESS;
657}
658
659static int ms_switch_parallel_bus(struct rtsx_chip *chip)
660{
661 int retval, i;
662 u8 data[2];
663
664 data[0] = PARALLEL_4BIT_IF;
665 data[1] = 0;
666 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
667 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
668 data, 2);
669 if (retval == STATUS_SUCCESS)
670 break;
671 }
672 if (retval != STATUS_SUCCESS)
673 TRACE_RET(chip, STATUS_FAIL);
674
675 return STATUS_SUCCESS;
676}
677
678static int ms_switch_8bit_bus(struct rtsx_chip *chip)
679{
680 struct ms_info *ms_card = &(chip->ms_card);
681 int retval, i;
682 u8 data[2];
683
684 data[0] = PARALLEL_8BIT_IF;
685 data[1] = 0;
686 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
687 retval = ms_write_bytes(chip, WRITE_REG, 1,
688 NO_WAIT_INT, data, 2);
689 if (retval == STATUS_SUCCESS)
690 break;
691 }
692 if (retval != STATUS_SUCCESS)
693 TRACE_RET(chip, STATUS_FAIL);
694
695 RTSX_WRITE_REG(chip, MS_CFG, 0x98,
696 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
697 ms_card->ms_type |= MS_8BIT;
698 retval = ms_set_init_para(chip);
699 if (retval != STATUS_SUCCESS)
700 TRACE_RET(chip, STATUS_FAIL);
701
702 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
703 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
704 1, NO_WAIT_INT);
705 if (retval != STATUS_SUCCESS)
706 TRACE_RET(chip, STATUS_FAIL);
707 }
708
709 return STATUS_SUCCESS;
710}
711
712static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
713{
714 struct ms_info *ms_card = &(chip->ms_card);
715 int retval, i;
716
717 for (i = 0; i < 3; i++) {
718 retval = ms_prepare_reset(chip);
719 if (retval != STATUS_SUCCESS)
720 TRACE_RET(chip, STATUS_FAIL);
721
722 retval = ms_identify_media_type(chip, switch_8bit_bus);
723 if (retval != STATUS_SUCCESS)
724 TRACE_RET(chip, STATUS_FAIL);
725
726 retval = ms_confirm_cpu_startup(chip);
727 if (retval != STATUS_SUCCESS)
728 TRACE_RET(chip, STATUS_FAIL);
729
730 retval = ms_switch_parallel_bus(chip);
731 if (retval != STATUS_SUCCESS) {
732 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
733 ms_set_err_code(chip, MS_NO_CARD);
734 TRACE_RET(chip, STATUS_FAIL);
735 }
736 continue;
737 } else {
738 break;
739 }
740 }
741
742 if (retval != STATUS_SUCCESS)
743 TRACE_RET(chip, STATUS_FAIL);
744
745
746 RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
747 RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
748
749 retval = ms_set_init_para(chip);
750 if (retval != STATUS_SUCCESS)
751 TRACE_RET(chip, STATUS_FAIL);
752
753
754 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
755 retval = ms_switch_8bit_bus(chip);
756 if (retval != STATUS_SUCCESS) {
757 ms_card->switch_8bit_fail = 1;
758 TRACE_RET(chip, STATUS_FAIL);
759 }
760 }
761
762 return STATUS_SUCCESS;
763}
764
765#ifdef XC_POWERCLASS
766static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
767{
768 int retval;
769 u8 buf[6];
770
771 ms_cleanup_work(chip);
772
773 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
774 if (retval != STATUS_SUCCESS)
775 TRACE_RET(chip, STATUS_FAIL);
776
777 buf[0] = 0;
778 buf[1] = mode;
779 buf[2] = 0;
780 buf[3] = 0;
781 buf[4] = 0;
782 buf[5] = 0;
783
784 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
785 if (retval != STATUS_SUCCESS)
786 TRACE_RET(chip, STATUS_FAIL);
787
788 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
789 if (retval != STATUS_SUCCESS)
790 TRACE_RET(chip, STATUS_FAIL);
791
792 RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
793 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
794 TRACE_RET(chip, STATUS_FAIL);
795
796 return STATUS_SUCCESS;
797}
798#endif
799
800static int ms_read_attribute_info(struct rtsx_chip *chip)
801{
802 struct ms_info *ms_card = &(chip->ms_card);
803 int retval, i;
804 u8 val, *buf, class_code, device_type, sub_class, data[16];
805 u16 total_blk = 0, blk_size = 0;
806#ifdef SUPPORT_MSXC
807 u32 xc_total_blk = 0, xc_blk_size = 0;
808#endif
809 u32 sys_info_addr = 0, sys_info_size;
810#ifdef SUPPORT_PCGL_1P18
811 u32 model_name_addr = 0, model_name_size;
812 int found_sys_info = 0, found_model_name = 0;
813#endif
814
815 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
816 if (retval != STATUS_SUCCESS)
817 TRACE_RET(chip, STATUS_FAIL);
818
819 if (CHK_MS8BIT(ms_card))
820 data[0] = PARALLEL_8BIT_IF;
821 else
822 data[0] = PARALLEL_4BIT_IF;
823
824 data[1] = 0;
825
826 data[2] = 0x40;
827 data[3] = 0;
828 data[4] = 0;
829 data[5] = 0;
830 data[6] = 0;
831 data[7] = 0;
832
833 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
834 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
835 data, 8);
836 if (retval == STATUS_SUCCESS)
837 break;
838 }
839 if (retval != STATUS_SUCCESS)
840 TRACE_RET(chip, STATUS_FAIL);
841
842 buf = kmalloc(64 * 512, GFP_KERNEL);
843 if (buf == NULL)
844 TRACE_RET(chip, STATUS_ERROR);
845
846 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
847 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
848 if (retval != STATUS_SUCCESS)
849 continue;
850
851 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
852 if (retval != STATUS_SUCCESS) {
853 kfree(buf);
854 TRACE_RET(chip, STATUS_FAIL);
855 }
856 if (!(val & MS_INT_BREQ)) {
857 kfree(buf);
858 TRACE_RET(chip, STATUS_FAIL);
859 }
860 retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
861 PRO_READ_LONG_DATA, 0x40, WAIT_INT,
862 0, 0, buf, 64 * 512);
863 if (retval == STATUS_SUCCESS)
864 break;
865
866 rtsx_clear_ms_error(chip);
867 }
868 if (retval != STATUS_SUCCESS) {
869 kfree(buf);
870 TRACE_RET(chip, STATUS_FAIL);
871 }
872
873 i = 0;
874 do {
875 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
876 if (retval != STATUS_SUCCESS) {
877 kfree(buf);
878 TRACE_RET(chip, STATUS_FAIL);
879 }
880
881 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
882 break;
883
884 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
885 PRO_READ_LONG_DATA, 0, WAIT_INT);
886 if (retval != STATUS_SUCCESS) {
887 kfree(buf);
888 TRACE_RET(chip, STATUS_FAIL);
889 }
890
891 i++;
892 } while (i < 1024);
893
894 if (retval != STATUS_SUCCESS) {
895 kfree(buf);
896 TRACE_RET(chip, STATUS_FAIL);
897 }
898
899 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
900
901 kfree(buf);
902 TRACE_RET(chip, STATUS_FAIL);
903 }
904
905 if ((buf[4] < 1) || (buf[4] > 12)) {
906 kfree(buf);
907 TRACE_RET(chip, STATUS_FAIL);
908 }
909
910 for (i = 0; i < buf[4]; i++) {
911 int cur_addr_off = 16 + i * 12;
912
913#ifdef SUPPORT_MSXC
914 if ((buf[cur_addr_off + 8] == 0x10) ||
915 (buf[cur_addr_off + 8] == 0x13))
916#else
917 if (buf[cur_addr_off + 8] == 0x10)
918#endif
919 {
920 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
921 ((u32)buf[cur_addr_off + 1] << 16) |
922 ((u32)buf[cur_addr_off + 2] << 8) |
923 buf[cur_addr_off + 3];
924 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
925 ((u32)buf[cur_addr_off + 5] << 16) |
926 ((u32)buf[cur_addr_off + 6] << 8) |
927 buf[cur_addr_off + 7];
928 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
929 sys_info_addr, sys_info_size);
930 if (sys_info_size != 96) {
931 kfree(buf);
932 TRACE_RET(chip, STATUS_FAIL);
933 }
934 if (sys_info_addr < 0x1A0) {
935 kfree(buf);
936 TRACE_RET(chip, STATUS_FAIL);
937 }
938 if ((sys_info_size + sys_info_addr) > 0x8000) {
939 kfree(buf);
940 TRACE_RET(chip, STATUS_FAIL);
941 }
942
943#ifdef SUPPORT_MSXC
944 if (buf[cur_addr_off + 8] == 0x13)
945 ms_card->ms_type |= MS_XC;
946#endif
947#ifdef SUPPORT_PCGL_1P18
948 found_sys_info = 1;
949#else
950 break;
951#endif
952 }
953#ifdef SUPPORT_PCGL_1P18
954 if (buf[cur_addr_off + 8] == 0x15) {
955 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
956 ((u32)buf[cur_addr_off + 1] << 16) |
957 ((u32)buf[cur_addr_off + 2] << 8) |
958 buf[cur_addr_off + 3];
959 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
960 ((u32)buf[cur_addr_off + 5] << 16) |
961 ((u32)buf[cur_addr_off + 6] << 8) |
962 buf[cur_addr_off + 7];
963 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n",
964 model_name_addr, model_name_size);
965 if (model_name_size != 48) {
966 kfree(buf);
967 TRACE_RET(chip, STATUS_FAIL);
968 }
969 if (model_name_addr < 0x1A0) {
970 kfree(buf);
971 TRACE_RET(chip, STATUS_FAIL);
972 }
973 if ((model_name_size + model_name_addr) > 0x8000) {
974 kfree(buf);
975 TRACE_RET(chip, STATUS_FAIL);
976 }
977
978 found_model_name = 1;
979 }
980
981 if (found_sys_info && found_model_name)
982 break;
983#endif
984 }
985
986 if (i == buf[4]) {
987 kfree(buf);
988 TRACE_RET(chip, STATUS_FAIL);
989 }
990
991 class_code = buf[sys_info_addr + 0];
992 device_type = buf[sys_info_addr + 56];
993 sub_class = buf[sys_info_addr + 46];
994#ifdef SUPPORT_MSXC
995 if (CHK_MSXC(ms_card)) {
996 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
997 ((u32)buf[sys_info_addr + 7] << 16) |
998 ((u32)buf[sys_info_addr + 8] << 8) |
999 buf[sys_info_addr + 9];
1000 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1001 ((u32)buf[sys_info_addr + 33] << 16) |
1002 ((u32)buf[sys_info_addr + 34] << 8) |
1003 buf[sys_info_addr + 35];
1004 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1005 xc_total_blk, xc_blk_size);
1006 } else {
1007 total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
1008 buf[sys_info_addr + 7];
1009 blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
1010 buf[sys_info_addr + 3];
1011 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1012 total_blk, blk_size);
1013 }
1014#else
1015 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1016 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1017 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1018 total_blk, blk_size);
1019#endif
1020
1021 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1022 class_code, device_type, sub_class);
1023
1024 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1025#ifdef SUPPORT_PCGL_1P18
1026 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1027#endif
1028
1029 kfree(buf);
1030
1031#ifdef SUPPORT_MSXC
1032 if (CHK_MSXC(ms_card)) {
1033 if (class_code != 0x03)
1034 TRACE_RET(chip, STATUS_FAIL);
1035 } else {
1036 if (class_code != 0x02)
1037 TRACE_RET(chip, STATUS_FAIL);
1038 }
1039#else
1040 if (class_code != 0x02)
1041 TRACE_RET(chip, STATUS_FAIL);
1042#endif
1043
1044 if (device_type != 0x00) {
1045 if ((device_type == 0x01) || (device_type == 0x02) ||
1046 (device_type == 0x03)) {
1047 chip->card_wp |= MS_CARD;
1048 } else {
1049 TRACE_RET(chip, STATUS_FAIL);
1050 }
1051 }
1052
1053 if (sub_class & 0xC0)
1054 TRACE_RET(chip, STATUS_FAIL);
1055
1056 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1057 class_code, device_type, sub_class);
1058
1059#ifdef SUPPORT_MSXC
1060 if (CHK_MSXC(ms_card)) {
1061 chip->capacity[chip->card2lun[MS_CARD]] =
1062 ms_card->capacity = xc_total_blk * xc_blk_size;
1063 } else {
1064 chip->capacity[chip->card2lun[MS_CARD]] =
1065 ms_card->capacity = total_blk * blk_size;
1066 }
1067#else
1068 ms_card->capacity = total_blk * blk_size;
1069 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1070#endif
1071
1072 return STATUS_SUCCESS;
1073}
1074
1075#ifdef SUPPORT_MAGIC_GATE
1076static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
1077 int type, u8 mg_entry_num);
1078#endif
1079
1080static int reset_ms_pro(struct rtsx_chip *chip)
1081{
1082 struct ms_info *ms_card = &(chip->ms_card);
1083 int retval;
1084#ifdef XC_POWERCLASS
1085 u8 change_power_class;
1086
1087 if (chip->ms_power_class_en & 0x02)
1088 change_power_class = 2;
1089 else if (chip->ms_power_class_en & 0x01)
1090 change_power_class = 1;
1091 else
1092 change_power_class = 0;
1093#endif
1094
1095#ifdef XC_POWERCLASS
1096Retry:
1097#endif
1098 retval = ms_pro_reset_flow(chip, 1);
1099 if (retval != STATUS_SUCCESS) {
1100 if (ms_card->switch_8bit_fail) {
1101 retval = ms_pro_reset_flow(chip, 0);
1102 if (retval != STATUS_SUCCESS)
1103 TRACE_RET(chip, STATUS_FAIL);
1104 } else {
1105 TRACE_RET(chip, STATUS_FAIL);
1106 }
1107 }
1108
1109 retval = ms_read_attribute_info(chip);
1110 if (retval != STATUS_SUCCESS)
1111 TRACE_RET(chip, STATUS_FAIL);
1112
1113#ifdef XC_POWERCLASS
1114 if (CHK_HG8BIT(ms_card))
1115 change_power_class = 0;
1116
1117 if (change_power_class && CHK_MSXC(ms_card)) {
1118 u8 power_class_en = chip->ms_power_class_en;
1119
1120 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n",
1121 power_class_en);
1122 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n",
1123 change_power_class);
1124
1125 if (change_power_class)
1126 power_class_en &= (1 << (change_power_class - 1));
1127 else
1128 power_class_en = 0;
1129
1130 if (power_class_en) {
1131 u8 power_class_mode =
1132 (ms_card->raw_sys_info[46] & 0x18) >> 3;
1133 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x",
1134 power_class_mode);
1135 if (change_power_class > power_class_mode)
1136 change_power_class = power_class_mode;
1137 if (change_power_class) {
1138 retval = msxc_change_power(chip,
1139 change_power_class);
1140 if (retval != STATUS_SUCCESS) {
1141 change_power_class--;
1142 goto Retry;
1143 }
1144 }
1145 }
1146 }
1147#endif
1148
1149#ifdef SUPPORT_MAGIC_GATE
1150 retval = mg_set_tpc_para_sub(chip, 0, 0);
1151 if (retval != STATUS_SUCCESS)
1152 TRACE_RET(chip, STATUS_FAIL);
1153#endif
1154
1155 if (CHK_HG8BIT(ms_card))
1156 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1157 else
1158 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1159
1160 return STATUS_SUCCESS;
1161}
1162
1163static int ms_read_status_reg(struct rtsx_chip *chip)
1164{
1165 int retval;
1166 u8 val[2];
1167
1168 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1169 if (retval != STATUS_SUCCESS)
1170 TRACE_RET(chip, STATUS_FAIL);
1171
1172 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1173 if (retval != STATUS_SUCCESS)
1174 TRACE_RET(chip, STATUS_FAIL);
1175
1176 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1177 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1178 TRACE_RET(chip, STATUS_FAIL);
1179 }
1180
1181 return STATUS_SUCCESS;
1182}
1183
1184
1185static int ms_read_extra_data(struct rtsx_chip *chip,
1186 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1187{
1188 struct ms_info *ms_card = &(chip->ms_card);
1189 int retval, i;
1190 u8 val, data[10];
1191
1192 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1193 SystemParm, 6);
1194 if (retval != STATUS_SUCCESS)
1195 TRACE_RET(chip, STATUS_FAIL);
1196
1197 if (CHK_MS4BIT(ms_card)) {
1198
1199 data[0] = 0x88;
1200 } else {
1201
1202 data[0] = 0x80;
1203 }
1204 data[1] = 0;
1205 data[2] = (u8)(block_addr >> 8);
1206 data[3] = (u8)block_addr;
1207 data[4] = 0x40;
1208 data[5] = page_num;
1209
1210 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1211 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1212 data, 6);
1213 if (retval == STATUS_SUCCESS)
1214 break;
1215 }
1216 if (i == MS_MAX_RETRY_COUNT)
1217 TRACE_RET(chip, STATUS_FAIL);
1218
1219 ms_set_err_code(chip, MS_NO_ERROR);
1220
1221 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1222 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1223 if (retval == STATUS_SUCCESS)
1224 break;
1225 }
1226 if (i == MS_MAX_RETRY_COUNT)
1227 TRACE_RET(chip, STATUS_FAIL);
1228
1229 ms_set_err_code(chip, MS_NO_ERROR);
1230 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1231 if (retval != STATUS_SUCCESS)
1232 TRACE_RET(chip, STATUS_FAIL);
1233
1234 if (val & INT_REG_CMDNK) {
1235 ms_set_err_code(chip, MS_CMD_NK);
1236 TRACE_RET(chip, STATUS_FAIL);
1237 }
1238 if (val & INT_REG_CED) {
1239 if (val & INT_REG_ERR) {
1240 retval = ms_read_status_reg(chip);
1241 if (retval != STATUS_SUCCESS)
1242 TRACE_RET(chip, STATUS_FAIL);
1243
1244 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1245 MS_EXTRA_SIZE, SystemParm, 6);
1246 if (retval != STATUS_SUCCESS)
1247 TRACE_RET(chip, STATUS_FAIL);
1248 }
1249 }
1250
1251 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
1252 data, MS_EXTRA_SIZE);
1253 if (retval != STATUS_SUCCESS)
1254 TRACE_RET(chip, STATUS_FAIL);
1255
1256 if (buf && buf_len) {
1257 if (buf_len > MS_EXTRA_SIZE)
1258 buf_len = MS_EXTRA_SIZE;
1259 memcpy(buf, data, buf_len);
1260 }
1261
1262 return STATUS_SUCCESS;
1263}
1264
1265static int ms_write_extra_data(struct rtsx_chip *chip,
1266 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1267{
1268 struct ms_info *ms_card = &(chip->ms_card);
1269 int retval, i;
1270 u8 val, data[16];
1271
1272 if (!buf || (buf_len < MS_EXTRA_SIZE))
1273 TRACE_RET(chip, STATUS_FAIL);
1274
1275 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1276 SystemParm, 6 + MS_EXTRA_SIZE);
1277 if (retval != STATUS_SUCCESS)
1278 TRACE_RET(chip, STATUS_FAIL);
1279
1280 if (CHK_MS4BIT(ms_card))
1281 data[0] = 0x88;
1282 else
1283 data[0] = 0x80;
1284
1285 data[1] = 0;
1286 data[2] = (u8)(block_addr >> 8);
1287 data[3] = (u8)block_addr;
1288 data[4] = 0x40;
1289 data[5] = page_num;
1290
1291 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1292 data[i] = buf[i - 6];
1293
1294 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1295 NO_WAIT_INT, data, 16);
1296 if (retval != STATUS_SUCCESS)
1297 TRACE_RET(chip, STATUS_FAIL);
1298
1299 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1300 if (retval != STATUS_SUCCESS)
1301 TRACE_RET(chip, STATUS_FAIL);
1302
1303 ms_set_err_code(chip, MS_NO_ERROR);
1304 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1305 if (retval != STATUS_SUCCESS)
1306 TRACE_RET(chip, STATUS_FAIL);
1307
1308 if (val & INT_REG_CMDNK) {
1309 ms_set_err_code(chip, MS_CMD_NK);
1310 TRACE_RET(chip, STATUS_FAIL);
1311 }
1312 if (val & INT_REG_CED) {
1313 if (val & INT_REG_ERR) {
1314 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1315 TRACE_RET(chip, STATUS_FAIL);
1316 }
1317 }
1318
1319 return STATUS_SUCCESS;
1320}
1321
1322
1323static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1324{
1325 struct ms_info *ms_card = &(chip->ms_card);
1326 int retval;
1327 u8 val, data[6];
1328
1329 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1330 SystemParm, 6);
1331 if (retval != STATUS_SUCCESS)
1332 TRACE_RET(chip, STATUS_FAIL);
1333
1334 if (CHK_MS4BIT(ms_card))
1335 data[0] = 0x88;
1336 else
1337 data[0] = 0x80;
1338
1339 data[1] = 0;
1340 data[2] = (u8)(block_addr >> 8);
1341 data[3] = (u8)block_addr;
1342 data[4] = 0x20;
1343 data[5] = page_num;
1344
1345 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1346 if (retval != STATUS_SUCCESS)
1347 TRACE_RET(chip, STATUS_FAIL);
1348
1349 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1350 if (retval != STATUS_SUCCESS)
1351 TRACE_RET(chip, STATUS_FAIL);
1352
1353 ms_set_err_code(chip, MS_NO_ERROR);
1354 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1355 if (retval != STATUS_SUCCESS)
1356 TRACE_RET(chip, STATUS_FAIL);
1357
1358 if (val & INT_REG_CMDNK) {
1359 ms_set_err_code(chip, MS_CMD_NK);
1360 TRACE_RET(chip, STATUS_FAIL);
1361 }
1362
1363 if (val & INT_REG_CED) {
1364 if (val & INT_REG_ERR) {
1365 if (!(val & INT_REG_BREQ)) {
1366 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1367 TRACE_RET(chip, STATUS_FAIL);
1368 }
1369 retval = ms_read_status_reg(chip);
1370 if (retval != STATUS_SUCCESS)
1371 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1372
1373 } else {
1374 if (!(val & INT_REG_BREQ)) {
1375 ms_set_err_code(chip, MS_BREQ_ERROR);
1376 TRACE_RET(chip, STATUS_FAIL);
1377 }
1378 }
1379 }
1380
1381 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
1382 0, NO_WAIT_INT);
1383 if (retval != STATUS_SUCCESS)
1384 TRACE_RET(chip, STATUS_FAIL);
1385
1386 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
1387 TRACE_RET(chip, STATUS_FAIL);
1388
1389 return STATUS_SUCCESS;
1390}
1391
1392
1393static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1394{
1395 struct ms_info *ms_card = &(chip->ms_card);
1396 int retval;
1397 u8 val, data[8], extra[MS_EXTRA_SIZE];
1398
1399 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1400 if (retval != STATUS_SUCCESS)
1401 TRACE_RET(chip, STATUS_FAIL);
1402
1403 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1404 SystemParm, 7);
1405 if (retval != STATUS_SUCCESS)
1406 TRACE_RET(chip, STATUS_FAIL);
1407
1408 ms_set_err_code(chip, MS_NO_ERROR);
1409
1410 if (CHK_MS4BIT(ms_card))
1411 data[0] = 0x88;
1412 else
1413 data[0] = 0x80;
1414
1415 data[1] = 0;
1416 data[2] = (u8)(phy_blk >> 8);
1417 data[3] = (u8)phy_blk;
1418 data[4] = 0x80;
1419 data[5] = 0;
1420 data[6] = extra[0] & 0x7F;
1421 data[7] = 0xFF;
1422
1423 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1424 if (retval != STATUS_SUCCESS)
1425 TRACE_RET(chip, STATUS_FAIL);
1426
1427 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1428 if (retval != STATUS_SUCCESS)
1429 TRACE_RET(chip, STATUS_FAIL);
1430
1431 ms_set_err_code(chip, MS_NO_ERROR);
1432 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1433 if (retval != STATUS_SUCCESS)
1434 TRACE_RET(chip, STATUS_FAIL);
1435
1436 if (val & INT_REG_CMDNK) {
1437 ms_set_err_code(chip, MS_CMD_NK);
1438 TRACE_RET(chip, STATUS_FAIL);
1439 }
1440
1441 if (val & INT_REG_CED) {
1442 if (val & INT_REG_ERR) {
1443 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1444 TRACE_RET(chip, STATUS_FAIL);
1445 }
1446 }
1447
1448 return STATUS_SUCCESS;
1449}
1450
1451
1452static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1453{
1454 struct ms_info *ms_card = &(chip->ms_card);
1455 int retval, i = 0;
1456 u8 val, data[6];
1457
1458 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1459 SystemParm, 6);
1460 if (retval != STATUS_SUCCESS)
1461 TRACE_RET(chip, STATUS_FAIL);
1462
1463 ms_set_err_code(chip, MS_NO_ERROR);
1464
1465 if (CHK_MS4BIT(ms_card))
1466 data[0] = 0x88;
1467 else
1468 data[0] = 0x80;
1469
1470 data[1] = 0;
1471 data[2] = (u8)(phy_blk >> 8);
1472 data[3] = (u8)phy_blk;
1473 data[4] = 0;
1474 data[5] = 0;
1475
1476 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1477 if (retval != STATUS_SUCCESS)
1478 TRACE_RET(chip, STATUS_FAIL);
1479
1480ERASE_RTY:
1481 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1482 if (retval != STATUS_SUCCESS)
1483 TRACE_RET(chip, STATUS_FAIL);
1484
1485 ms_set_err_code(chip, MS_NO_ERROR);
1486 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1487 if (retval != STATUS_SUCCESS)
1488 TRACE_RET(chip, STATUS_FAIL);
1489
1490 if (val & INT_REG_CMDNK) {
1491 if (i < 3) {
1492 i++;
1493 goto ERASE_RTY;
1494 }
1495
1496 ms_set_err_code(chip, MS_CMD_NK);
1497 ms_set_bad_block(chip, phy_blk);
1498 TRACE_RET(chip, STATUS_FAIL);
1499 }
1500
1501 if (val & INT_REG_CED) {
1502 if (val & INT_REG_ERR) {
1503 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1504 TRACE_RET(chip, STATUS_FAIL);
1505 }
1506 }
1507
1508 return STATUS_SUCCESS;
1509}
1510
1511
1512static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1513{
1514 if (!extra || (extra_len < MS_EXTRA_SIZE))
1515 return;
1516
1517 memset(extra, 0xFF, MS_EXTRA_SIZE);
1518
1519 if (type == setPS_NG) {
1520
1521 extra[0] = 0xB8;
1522 } else {
1523
1524 extra[0] = 0x98;
1525 }
1526
1527 extra[2] = (u8)(log_blk >> 8);
1528 extra[3] = (u8)log_blk;
1529}
1530
1531static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
1532 u8 start_page, u8 end_page)
1533{
1534 int retval;
1535 u8 extra[MS_EXTRA_SIZE], i;
1536
1537 memset(extra, 0xff, MS_EXTRA_SIZE);
1538
1539 extra[0] = 0xf8;
1540 extra[1] = 0xff;
1541 extra[2] = (u8)(log_blk >> 8);
1542 extra[3] = (u8)log_blk;
1543
1544 for (i = start_page; i < end_page; i++) {
1545 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1546 ms_set_err_code(chip, MS_NO_CARD);
1547 TRACE_RET(chip, STATUS_FAIL);
1548 }
1549
1550 retval = ms_write_extra_data(chip, phy_blk, i,
1551 extra, MS_EXTRA_SIZE);
1552 if (retval != STATUS_SUCCESS)
1553 TRACE_RET(chip, STATUS_FAIL);
1554 }
1555
1556 return STATUS_SUCCESS;
1557}
1558
1559static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1560 u16 log_blk, u8 start_page, u8 end_page)
1561{
1562 struct ms_info *ms_card = &(chip->ms_card);
1563 int retval, rty_cnt, uncorrect_flag = 0;
1564 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1565
1566 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1567 old_blk, new_blk, log_blk);
1568 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n",
1569 start_page, end_page);
1570
1571 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1572 if (retval != STATUS_SUCCESS)
1573 TRACE_RET(chip, STATUS_FAIL);
1574
1575 retval = ms_read_status_reg(chip);
1576 if (retval != STATUS_SUCCESS)
1577 TRACE_RET(chip, STATUS_FAIL);
1578
1579 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1580
1581 if (val & BUF_FULL) {
1582 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1583 if (retval != STATUS_SUCCESS)
1584 TRACE_RET(chip, STATUS_FAIL);
1585
1586 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1587 if (retval != STATUS_SUCCESS)
1588 TRACE_RET(chip, STATUS_FAIL);
1589
1590 if (!(val & INT_REG_CED)) {
1591 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1592 TRACE_RET(chip, STATUS_FAIL);
1593 }
1594 }
1595
1596 for (i = start_page; i < end_page; i++) {
1597 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1598 ms_set_err_code(chip, MS_NO_CARD);
1599 TRACE_RET(chip, STATUS_FAIL);
1600 }
1601
1602 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1603
1604 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1605 MS_EXTRA_SIZE, SystemParm, 6);
1606 if (retval != STATUS_SUCCESS)
1607 TRACE_RET(chip, STATUS_FAIL);
1608
1609 ms_set_err_code(chip, MS_NO_ERROR);
1610
1611 if (CHK_MS4BIT(ms_card))
1612 data[0] = 0x88;
1613 else
1614 data[0] = 0x80;
1615
1616 data[1] = 0;
1617 data[2] = (u8)(old_blk >> 8);
1618 data[3] = (u8)old_blk;
1619 data[4] = 0x20;
1620 data[5] = i;
1621
1622 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1623 data, 6);
1624 if (retval != STATUS_SUCCESS)
1625 TRACE_RET(chip, STATUS_FAIL);
1626
1627 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1628 if (retval != STATUS_SUCCESS)
1629 TRACE_RET(chip, STATUS_FAIL);
1630
1631 ms_set_err_code(chip, MS_NO_ERROR);
1632 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1633 if (retval != STATUS_SUCCESS)
1634 TRACE_RET(chip, STATUS_FAIL);
1635
1636 if (val & INT_REG_CMDNK) {
1637 ms_set_err_code(chip, MS_CMD_NK);
1638 TRACE_RET(chip, STATUS_FAIL);
1639 }
1640
1641 if (val & INT_REG_CED) {
1642 if (val & INT_REG_ERR) {
1643 retval = ms_read_status_reg(chip);
1644 if (retval != STATUS_SUCCESS) {
1645 uncorrect_flag = 1;
1646 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n");
1647 } else {
1648 uncorrect_flag = 0;
1649 }
1650
1651 retval = ms_transfer_tpc(chip,
1652 MS_TM_NORMAL_READ,
1653 READ_PAGE_DATA,
1654 0, NO_WAIT_INT);
1655 if (retval != STATUS_SUCCESS)
1656 TRACE_RET(chip, STATUS_FAIL);
1657
1658 if (uncorrect_flag) {
1659 ms_set_page_status(log_blk, setPS_NG,
1660 extra, MS_EXTRA_SIZE);
1661 if (i == 0)
1662 extra[0] &= 0xEF;
1663
1664 ms_write_extra_data(chip, old_blk, i,
1665 extra, MS_EXTRA_SIZE);
1666 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n",
1667 i, extra[0]);
1668 MS_SET_BAD_BLOCK_FLG(ms_card);
1669
1670 ms_set_page_status(log_blk, setPS_Error,
1671 extra, MS_EXTRA_SIZE);
1672 ms_write_extra_data(chip, new_blk, i,
1673 extra, MS_EXTRA_SIZE);
1674 continue;
1675 }
1676
1677 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
1678 rty_cnt++) {
1679 retval = ms_transfer_tpc(
1680 chip,
1681 MS_TM_NORMAL_WRITE,
1682 WRITE_PAGE_DATA,
1683 0, NO_WAIT_INT);
1684 if (retval == STATUS_SUCCESS)
1685 break;
1686 }
1687 if (rty_cnt == MS_MAX_RETRY_COUNT)
1688 TRACE_RET(chip, STATUS_FAIL);
1689 }
1690
1691 if (!(val & INT_REG_BREQ)) {
1692 ms_set_err_code(chip, MS_BREQ_ERROR);
1693 TRACE_RET(chip, STATUS_FAIL);
1694 }
1695 }
1696
1697 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1698 MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE));
1699
1700 ms_set_err_code(chip, MS_NO_ERROR);
1701
1702 if (CHK_MS4BIT(ms_card))
1703 data[0] = 0x88;
1704 else
1705 data[0] = 0x80;
1706
1707 data[1] = 0;
1708 data[2] = (u8)(new_blk >> 8);
1709 data[3] = (u8)new_blk;
1710 data[4] = 0x20;
1711 data[5] = i;
1712
1713 if ((extra[0] & 0x60) != 0x60)
1714 data[6] = extra[0];
1715 else
1716 data[6] = 0xF8;
1717
1718 data[6 + 1] = 0xFF;
1719 data[6 + 2] = (u8)(log_blk >> 8);
1720 data[6 + 3] = (u8)log_blk;
1721
1722 for (j = 4; j <= MS_EXTRA_SIZE; j++)
1723 data[6 + j] = 0xFF;
1724
1725 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1726 NO_WAIT_INT, data, 16);
1727 if (retval != STATUS_SUCCESS)
1728 TRACE_RET(chip, STATUS_FAIL);
1729
1730 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1731 if (retval != STATUS_SUCCESS)
1732 TRACE_RET(chip, STATUS_FAIL);
1733
1734 ms_set_err_code(chip, MS_NO_ERROR);
1735 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1736 if (retval != STATUS_SUCCESS)
1737 TRACE_RET(chip, STATUS_FAIL);
1738
1739 if (val & INT_REG_CMDNK) {
1740 ms_set_err_code(chip, MS_CMD_NK);
1741 TRACE_RET(chip, STATUS_FAIL);
1742 }
1743
1744 if (val & INT_REG_CED) {
1745 if (val & INT_REG_ERR) {
1746 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1747 TRACE_RET(chip, STATUS_FAIL);
1748 }
1749 }
1750
1751 if (i == 0) {
1752 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1753 MS_EXTRA_SIZE, SystemParm, 7);
1754 if (retval != STATUS_SUCCESS)
1755 TRACE_RET(chip, STATUS_FAIL);
1756
1757 ms_set_err_code(chip, MS_NO_ERROR);
1758
1759 if (CHK_MS4BIT(ms_card))
1760 data[0] = 0x88;
1761 else
1762 data[0] = 0x80;
1763
1764 data[1] = 0;
1765 data[2] = (u8)(old_blk >> 8);
1766 data[3] = (u8)old_blk;
1767 data[4] = 0x80;
1768 data[5] = 0;
1769 data[6] = 0xEF;
1770 data[7] = 0xFF;
1771
1772 retval = ms_write_bytes(chip, WRITE_REG, 7,
1773 NO_WAIT_INT, data, 8);
1774 if (retval != STATUS_SUCCESS)
1775 TRACE_RET(chip, STATUS_FAIL);
1776
1777 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1778 if (retval != STATUS_SUCCESS)
1779 TRACE_RET(chip, STATUS_FAIL);
1780
1781 ms_set_err_code(chip, MS_NO_ERROR);
1782 retval = ms_read_bytes(chip, GET_INT, 1,
1783 NO_WAIT_INT, &val, 1);
1784 if (retval != STATUS_SUCCESS)
1785 TRACE_RET(chip, STATUS_FAIL);
1786
1787 if (val & INT_REG_CMDNK) {
1788 ms_set_err_code(chip, MS_CMD_NK);
1789 TRACE_RET(chip, STATUS_FAIL);
1790 }
1791
1792 if (val & INT_REG_CED) {
1793 if (val & INT_REG_ERR) {
1794 ms_set_err_code(chip,
1795 MS_FLASH_WRITE_ERROR);
1796 TRACE_RET(chip, STATUS_FAIL);
1797 }
1798 }
1799 }
1800 }
1801
1802 return STATUS_SUCCESS;
1803}
1804
1805
1806static int reset_ms(struct rtsx_chip *chip)
1807{
1808 struct ms_info *ms_card = &(chip->ms_card);
1809 int retval;
1810 u16 i, reg_addr, block_size;
1811 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
1812#ifndef SUPPORT_MAGIC_GATE
1813 u16 eblock_cnt;
1814#endif
1815
1816 retval = ms_prepare_reset(chip);
1817 if (retval != STATUS_SUCCESS)
1818 TRACE_RET(chip, STATUS_FAIL);
1819
1820 ms_card->ms_type |= TYPE_MS;
1821
1822 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
1823 if (retval != STATUS_SUCCESS)
1824 TRACE_RET(chip, STATUS_FAIL);
1825
1826 retval = ms_read_status_reg(chip);
1827 if (retval != STATUS_SUCCESS)
1828 TRACE_RET(chip, STATUS_FAIL);
1829
1830 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1831 if (val & WRT_PRTCT)
1832 chip->card_wp |= MS_CARD;
1833 else
1834 chip->card_wp &= ~MS_CARD;
1835
1836 i = 0;
1837
1838RE_SEARCH:
1839
1840 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
1841 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1842 ms_set_err_code(chip, MS_NO_CARD);
1843 TRACE_RET(chip, STATUS_FAIL);
1844 }
1845
1846 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
1847 if (retval != STATUS_SUCCESS) {
1848 i++;
1849 continue;
1850 }
1851
1852 if (extra[0] & BLOCK_OK) {
1853 if (!(extra[1] & NOT_BOOT_BLOCK)) {
1854 ms_card->boot_block = i;
1855 break;
1856 }
1857 }
1858 i++;
1859 }
1860
1861 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
1862 dev_dbg(rtsx_dev(chip), "No boot block found!");
1863 TRACE_RET(chip, STATUS_FAIL);
1864 }
1865
1866 for (j = 0; j < 3; j++) {
1867 retval = ms_read_page(chip, ms_card->boot_block, j);
1868 if (retval != STATUS_SUCCESS) {
1869 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1870 i = ms_card->boot_block + 1;
1871 ms_set_err_code(chip, MS_NO_ERROR);
1872 goto RE_SEARCH;
1873 }
1874 }
1875 }
1876
1877 retval = ms_read_page(chip, ms_card->boot_block, 0);
1878 if (retval != STATUS_SUCCESS)
1879 TRACE_RET(chip, STATUS_FAIL);
1880
1881
1882 rtsx_init_cmd(chip);
1883
1884 for (i = 0; i < 96; i++)
1885 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
1886
1887 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1888 if (retval < 0)
1889 TRACE_RET(chip, STATUS_FAIL);
1890
1891 ptr = rtsx_get_cmd_data(chip);
1892 memcpy(ms_card->raw_sys_info, ptr, 96);
1893
1894
1895 rtsx_init_cmd(chip);
1896
1897 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
1898 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
1899
1900 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
1901 reg_addr++)
1902 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1903
1904 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
1905 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1906
1907 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
1908 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
1909
1910 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1911 if (retval < 0)
1912 TRACE_RET(chip, STATUS_FAIL);
1913
1914 ptr = rtsx_get_cmd_data(chip);
1915
1916 dev_dbg(rtsx_dev(chip), "Boot block data:\n");
1917 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr);
1918
1919
1920
1921
1922 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
1923 i = ms_card->boot_block + 1;
1924 goto RE_SEARCH;
1925 }
1926
1927
1928
1929
1930 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
1931 i = ms_card->boot_block + 1;
1932 goto RE_SEARCH;
1933 }
1934
1935 if ((ptr[14] == 1) || (ptr[14] == 3))
1936 chip->card_wp |= MS_CARD;
1937
1938
1939 block_size = ((u16)ptr[6] << 8) | ptr[7];
1940 if (block_size == 0x0010) {
1941
1942 ms_card->block_shift = 5;
1943 ms_card->page_off = 0x1F;
1944 } else if (block_size == 0x0008) {
1945
1946 ms_card->block_shift = 4;
1947 ms_card->page_off = 0x0F;
1948 }
1949
1950
1951 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
1952
1953#ifdef SUPPORT_MAGIC_GATE
1954 j = ptr[10];
1955
1956 if (ms_card->block_shift == 4) {
1957 if (j < 2) {
1958 ms_card->capacity = 0x1EE0;
1959 } else {
1960 ms_card->capacity = 0x3DE0;
1961 }
1962 } else {
1963 if (j < 5) {
1964 ms_card->capacity = 0x7BC0;
1965 } else if (j < 0xA) {
1966 ms_card->capacity = 0xF7C0;
1967 } else if (j < 0x11) {
1968 ms_card->capacity = 0x1EF80;
1969 } else {
1970 ms_card->capacity = 0x3DF00;
1971 }
1972 }
1973#else
1974
1975 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
1976
1977 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
1978#endif
1979
1980 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1981
1982
1983 if (ptr[15]) {
1984 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
1985 if (retval != STATUS_SUCCESS)
1986 TRACE_RET(chip, STATUS_FAIL);
1987
1988 RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
1989 RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
1990
1991 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
1992 NO_WAIT_INT);
1993 if (retval != STATUS_SUCCESS)
1994 TRACE_RET(chip, STATUS_FAIL);
1995
1996 RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
1997 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
1998
1999 ms_card->ms_type |= MS_4BIT;
2000 }
2001
2002 if (CHK_MS4BIT(ms_card))
2003 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2004 else
2005 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2006
2007 return STATUS_SUCCESS;
2008}
2009
2010static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2011{
2012 struct ms_info *ms_card = &(chip->ms_card);
2013 int size, i, seg_no, retval;
2014 u16 defect_block, reg_addr;
2015 u8 val1, val2;
2016
2017 ms_card->segment_cnt = ms_card->total_block >> 9;
2018 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n",
2019 ms_card->segment_cnt);
2020
2021 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2022 ms_card->segment = vzalloc(size);
2023 if (ms_card->segment == NULL)
2024 TRACE_RET(chip, STATUS_FAIL);
2025
2026 retval = ms_read_page(chip, ms_card->boot_block, 1);
2027 if (retval != STATUS_SUCCESS)
2028 TRACE_GOTO(chip, INIT_FAIL);
2029
2030 reg_addr = PPBUF_BASE2;
2031 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2032 retval = rtsx_read_register(chip, reg_addr++, &val1);
2033 if (retval != STATUS_SUCCESS)
2034 TRACE_GOTO(chip, INIT_FAIL);
2035
2036 retval = rtsx_read_register(chip, reg_addr++, &val2);
2037 if (retval != STATUS_SUCCESS)
2038 TRACE_GOTO(chip, INIT_FAIL);
2039
2040 defect_block = ((u16)val1 << 8) | val2;
2041 if (defect_block == 0xFFFF)
2042 break;
2043
2044 seg_no = defect_block / 512;
2045 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].disable_count++] = defect_block;
2046 }
2047
2048 for (i = 0; i < ms_card->segment_cnt; i++) {
2049 ms_card->segment[i].build_flag = 0;
2050 ms_card->segment[i].l2p_table = NULL;
2051 ms_card->segment[i].free_table = NULL;
2052 ms_card->segment[i].get_index = 0;
2053 ms_card->segment[i].set_index = 0;
2054 ms_card->segment[i].unused_blk_cnt = 0;
2055
2056 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n",
2057 i, ms_card->segment[i].disable_count);
2058 }
2059
2060 return STATUS_SUCCESS;
2061
2062INIT_FAIL:
2063 if (ms_card->segment) {
2064 vfree(ms_card->segment);
2065 ms_card->segment = NULL;
2066 }
2067
2068 return STATUS_FAIL;
2069}
2070
2071static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2072{
2073 struct ms_info *ms_card = &(chip->ms_card);
2074 struct zone_entry *segment;
2075
2076 if (ms_card->segment == NULL)
2077 return 0xFFFF;
2078
2079 segment = &(ms_card->segment[seg_no]);
2080
2081 if (segment->l2p_table)
2082 return segment->l2p_table[log_off];
2083
2084 return 0xFFFF;
2085}
2086
2087static void ms_set_l2p_tbl(struct rtsx_chip *chip,
2088 int seg_no, u16 log_off, u16 phy_blk)
2089{
2090 struct ms_info *ms_card = &(chip->ms_card);
2091 struct zone_entry *segment;
2092
2093 if (ms_card->segment == NULL)
2094 return;
2095
2096 segment = &(ms_card->segment[seg_no]);
2097 if (segment->l2p_table)
2098 segment->l2p_table[log_off] = phy_blk;
2099}
2100
2101static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2102{
2103 struct ms_info *ms_card = &(chip->ms_card);
2104 struct zone_entry *segment;
2105 int seg_no;
2106
2107 seg_no = (int)phy_blk >> 9;
2108 segment = &(ms_card->segment[seg_no]);
2109
2110 segment->free_table[segment->set_index++] = phy_blk;
2111 if (segment->set_index >= MS_FREE_TABLE_CNT)
2112 segment->set_index = 0;
2113
2114 segment->unused_blk_cnt++;
2115}
2116
2117static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2118{
2119 struct ms_info *ms_card = &(chip->ms_card);
2120 struct zone_entry *segment;
2121 u16 phy_blk;
2122
2123 segment = &(ms_card->segment[seg_no]);
2124
2125 if (segment->unused_blk_cnt <= 0)
2126 return 0xFFFF;
2127
2128 phy_blk = segment->free_table[segment->get_index];
2129 segment->free_table[segment->get_index++] = 0xFFFF;
2130 if (segment->get_index >= MS_FREE_TABLE_CNT)
2131 segment->get_index = 0;
2132
2133 segment->unused_blk_cnt--;
2134
2135 return phy_blk;
2136}
2137
2138static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
2139 2974, 3470, 3966, 4462, 4958,
2140 5454, 5950, 6446, 6942, 7438,
2141 7934};
2142
2143static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
2144 u16 log_off, u8 us1, u8 us2)
2145{
2146 struct ms_info *ms_card = &(chip->ms_card);
2147 struct zone_entry *segment;
2148 int seg_no;
2149 u16 tmp_blk;
2150
2151 seg_no = (int)phy_blk >> 9;
2152 segment = &(ms_card->segment[seg_no]);
2153 tmp_blk = segment->l2p_table[log_off];
2154
2155 if (us1 != us2) {
2156 if (us1 == 0) {
2157 if (!(chip->card_wp & MS_CARD))
2158 ms_erase_block(chip, tmp_blk);
2159
2160 ms_set_unused_block(chip, tmp_blk);
2161 segment->l2p_table[log_off] = phy_blk;
2162 } else {
2163 if (!(chip->card_wp & MS_CARD))
2164 ms_erase_block(chip, phy_blk);
2165
2166 ms_set_unused_block(chip, phy_blk);
2167 }
2168 } else {
2169 if (phy_blk < tmp_blk) {
2170 if (!(chip->card_wp & MS_CARD))
2171 ms_erase_block(chip, phy_blk);
2172
2173 ms_set_unused_block(chip, phy_blk);
2174 } else {
2175 if (!(chip->card_wp & MS_CARD))
2176 ms_erase_block(chip, tmp_blk);
2177
2178 ms_set_unused_block(chip, tmp_blk);
2179 segment->l2p_table[log_off] = phy_blk;
2180 }
2181 }
2182
2183 return STATUS_SUCCESS;
2184}
2185
2186static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2187{
2188 struct ms_info *ms_card = &(chip->ms_card);
2189 struct zone_entry *segment;
2190 int retval, table_size, disable_cnt, defect_flag, i;
2191 u16 start, end, phy_blk, log_blk, tmp_blk;
2192 u8 extra[MS_EXTRA_SIZE], us1, us2;
2193
2194 dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no);
2195
2196 if (ms_card->segment == NULL) {
2197 retval = ms_init_l2p_tbl(chip);
2198 if (retval != STATUS_SUCCESS)
2199 TRACE_RET(chip, retval);
2200 }
2201
2202 if (ms_card->segment[seg_no].build_flag) {
2203 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n",
2204 seg_no);
2205 return STATUS_SUCCESS;
2206 }
2207
2208 if (seg_no == 0)
2209 table_size = 494;
2210 else
2211 table_size = 496;
2212
2213 segment = &(ms_card->segment[seg_no]);
2214
2215 if (segment->l2p_table == NULL) {
2216 segment->l2p_table = vmalloc(table_size * 2);
2217 if (segment->l2p_table == NULL)
2218 TRACE_GOTO(chip, BUILD_FAIL);
2219 }
2220 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2221
2222 if (segment->free_table == NULL) {
2223 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2224 if (segment->free_table == NULL)
2225 TRACE_GOTO(chip, BUILD_FAIL);
2226 }
2227 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2228
2229 start = (u16)seg_no << 9;
2230 end = (u16)(seg_no + 1) << 9;
2231
2232 disable_cnt = segment->disable_count;
2233
2234 segment->get_index = segment->set_index = 0;
2235 segment->unused_blk_cnt = 0;
2236
2237 for (phy_blk = start; phy_blk < end; phy_blk++) {
2238 if (disable_cnt) {
2239 defect_flag = 0;
2240 for (i = 0; i < segment->disable_count; i++) {
2241 if (phy_blk == segment->defect_list[i]) {
2242 defect_flag = 1;
2243 break;
2244 }
2245 }
2246 if (defect_flag) {
2247 disable_cnt--;
2248 continue;
2249 }
2250 }
2251
2252 retval = ms_read_extra_data(chip, phy_blk, 0,
2253 extra, MS_EXTRA_SIZE);
2254 if (retval != STATUS_SUCCESS) {
2255 dev_dbg(rtsx_dev(chip), "read extra data fail\n");
2256 ms_set_bad_block(chip, phy_blk);
2257 continue;
2258 }
2259
2260 if (seg_no == ms_card->segment_cnt - 1) {
2261 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2262 if (!(chip->card_wp & MS_CARD)) {
2263 retval = ms_erase_block(chip, phy_blk);
2264 if (retval != STATUS_SUCCESS)
2265 continue;
2266 extra[2] = 0xff;
2267 extra[3] = 0xff;
2268 }
2269 }
2270 }
2271
2272 if (!(extra[0] & BLOCK_OK))
2273 continue;
2274 if (!(extra[1] & NOT_BOOT_BLOCK))
2275 continue;
2276 if ((extra[0] & PAGE_OK) != PAGE_OK)
2277 continue;
2278
2279 log_blk = ((u16)extra[2] << 8) | extra[3];
2280
2281 if (log_blk == 0xFFFF) {
2282 if (!(chip->card_wp & MS_CARD)) {
2283 retval = ms_erase_block(chip, phy_blk);
2284 if (retval != STATUS_SUCCESS)
2285 continue;
2286 }
2287 ms_set_unused_block(chip, phy_blk);
2288 continue;
2289 }
2290
2291 if ((log_blk < ms_start_idx[seg_no]) ||
2292 (log_blk >= ms_start_idx[seg_no+1])) {
2293 if (!(chip->card_wp & MS_CARD)) {
2294 retval = ms_erase_block(chip, phy_blk);
2295 if (retval != STATUS_SUCCESS)
2296 continue;
2297 }
2298 ms_set_unused_block(chip, phy_blk);
2299 continue;
2300 }
2301
2302 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] == 0xFFFF) {
2303 segment->l2p_table[log_blk - ms_start_idx[seg_no]] = phy_blk;
2304 continue;
2305 }
2306
2307 us1 = extra[0] & 0x10;
2308 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2309 retval = ms_read_extra_data(chip, tmp_blk, 0,
2310 extra, MS_EXTRA_SIZE);
2311 if (retval != STATUS_SUCCESS)
2312 continue;
2313 us2 = extra[0] & 0x10;
2314
2315 (void)ms_arbitrate_l2p(chip, phy_blk,
2316 log_blk-ms_start_idx[seg_no], us1, us2);
2317 continue;
2318 }
2319
2320 segment->build_flag = 1;
2321
2322 dev_dbg(rtsx_dev(chip), "unused block count: %d\n",
2323 segment->unused_blk_cnt);
2324
2325
2326 if (seg_no == ms_card->segment_cnt - 1) {
2327 if (segment->unused_blk_cnt < 2)
2328 chip->card_wp |= MS_CARD;
2329 } else {
2330 if (segment->unused_blk_cnt < 1)
2331 chip->card_wp |= MS_CARD;
2332 }
2333
2334 if (chip->card_wp & MS_CARD)
2335 return STATUS_SUCCESS;
2336
2337 for (log_blk = ms_start_idx[seg_no];
2338 log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2339 if (segment->l2p_table[log_blk-ms_start_idx[seg_no]] == 0xFFFF) {
2340 phy_blk = ms_get_unused_block(chip, seg_no);
2341 if (phy_blk == 0xFFFF) {
2342 chip->card_wp |= MS_CARD;
2343 return STATUS_SUCCESS;
2344 }
2345 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2346 if (retval != STATUS_SUCCESS)
2347 TRACE_GOTO(chip, BUILD_FAIL);
2348
2349 segment->l2p_table[log_blk-ms_start_idx[seg_no]] = phy_blk;
2350 if (seg_no == ms_card->segment_cnt - 1) {
2351 if (segment->unused_blk_cnt < 2) {
2352 chip->card_wp |= MS_CARD;
2353 return STATUS_SUCCESS;
2354 }
2355 } else {
2356 if (segment->unused_blk_cnt < 1) {
2357 chip->card_wp |= MS_CARD;
2358 return STATUS_SUCCESS;
2359 }
2360 }
2361 }
2362 }
2363
2364
2365 if (seg_no == 0) {
2366 for (log_blk = 0; log_blk < 494; log_blk++) {
2367 tmp_blk = segment->l2p_table[log_blk];
2368 if (tmp_blk < ms_card->boot_block) {
2369 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n");
2370
2371 if (chip->card_wp & MS_CARD)
2372 break;
2373
2374 phy_blk = ms_get_unused_block(chip, 0);
2375 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2376 log_blk, 0, ms_card->page_off + 1);
2377 if (retval != STATUS_SUCCESS)
2378 TRACE_RET(chip, STATUS_FAIL);
2379
2380 segment->l2p_table[log_blk] = phy_blk;
2381
2382 retval = ms_set_bad_block(chip, tmp_blk);
2383 if (retval != STATUS_SUCCESS)
2384 TRACE_RET(chip, STATUS_FAIL);
2385 }
2386 }
2387 }
2388
2389 return STATUS_SUCCESS;
2390
2391BUILD_FAIL:
2392 segment->build_flag = 0;
2393 if (segment->l2p_table) {
2394 vfree(segment->l2p_table);
2395 segment->l2p_table = NULL;
2396 }
2397 if (segment->free_table) {
2398 vfree(segment->free_table);
2399 segment->free_table = NULL;
2400 }
2401
2402 return STATUS_FAIL;
2403}
2404
2405
2406int reset_ms_card(struct rtsx_chip *chip)
2407{
2408 struct ms_info *ms_card = &(chip->ms_card);
2409 int retval;
2410
2411 memset(ms_card, 0, sizeof(struct ms_info));
2412
2413 retval = enable_card_clock(chip, MS_CARD);
2414 if (retval != STATUS_SUCCESS)
2415 TRACE_RET(chip, STATUS_FAIL);
2416
2417 retval = select_card(chip, MS_CARD);
2418 if (retval != STATUS_SUCCESS)
2419 TRACE_RET(chip, STATUS_FAIL);
2420
2421 ms_card->ms_type = 0;
2422
2423 retval = reset_ms_pro(chip);
2424 if (retval != STATUS_SUCCESS) {
2425 if (ms_card->check_ms_flow) {
2426 retval = reset_ms(chip);
2427 if (retval != STATUS_SUCCESS)
2428 TRACE_RET(chip, STATUS_FAIL);
2429 } else {
2430 TRACE_RET(chip, STATUS_FAIL);
2431 }
2432 }
2433
2434 retval = ms_set_init_para(chip);
2435 if (retval != STATUS_SUCCESS)
2436 TRACE_RET(chip, STATUS_FAIL);
2437
2438 if (!CHK_MSPRO(ms_card)) {
2439
2440
2441
2442 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2443 if (retval != STATUS_SUCCESS)
2444 TRACE_RET(chip, STATUS_FAIL);
2445 }
2446
2447 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2448
2449 return STATUS_SUCCESS;
2450}
2451
2452static int mspro_set_rw_cmd(struct rtsx_chip *chip,
2453 u32 start_sec, u16 sec_cnt, u8 cmd)
2454{
2455 int retval, i;
2456 u8 data[8];
2457
2458 data[0] = cmd;
2459 data[1] = (u8)(sec_cnt >> 8);
2460 data[2] = (u8)sec_cnt;
2461 data[3] = (u8)(start_sec >> 24);
2462 data[4] = (u8)(start_sec >> 16);
2463 data[5] = (u8)(start_sec >> 8);
2464 data[6] = (u8)start_sec;
2465 data[7] = 0;
2466
2467 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2468 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
2469 WAIT_INT, data, 8);
2470 if (retval == STATUS_SUCCESS)
2471 break;
2472 }
2473 if (i == MS_MAX_RETRY_COUNT)
2474 TRACE_RET(chip, STATUS_FAIL);
2475
2476 return STATUS_SUCCESS;
2477}
2478
2479
2480void mspro_stop_seq_mode(struct rtsx_chip *chip)
2481{
2482 struct ms_info *ms_card = &(chip->ms_card);
2483 int retval;
2484
2485 if (ms_card->seq_mode) {
2486 retval = ms_switch_clock(chip);
2487 if (retval != STATUS_SUCCESS)
2488 return;
2489
2490 ms_card->seq_mode = 0;
2491 ms_card->total_sec_cnt = 0;
2492 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2493
2494 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2495 }
2496}
2497
2498static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2499{
2500 struct ms_info *ms_card = &(chip->ms_card);
2501 int retval;
2502
2503 if (chip->asic_code) {
2504 if (ms_card->ms_clock > 30)
2505 ms_card->ms_clock -= 20;
2506 } else {
2507 if (ms_card->ms_clock == CLK_80)
2508 ms_card->ms_clock = CLK_60;
2509 else if (ms_card->ms_clock == CLK_60)
2510 ms_card->ms_clock = CLK_40;
2511 }
2512
2513 retval = ms_switch_clock(chip);
2514 if (retval != STATUS_SUCCESS)
2515 TRACE_RET(chip, STATUS_FAIL);
2516
2517 return STATUS_SUCCESS;
2518}
2519
2520static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2521 struct rtsx_chip *chip, u32 start_sector,
2522 u16 sector_cnt)
2523{
2524 struct ms_info *ms_card = &(chip->ms_card);
2525 int retval, mode_2k = 0;
2526 u16 count;
2527 u8 val, trans_mode, rw_tpc, rw_cmd;
2528
2529 ms_set_err_code(chip, MS_NO_ERROR);
2530
2531 ms_card->cleanup_counter = 0;
2532
2533 if (CHK_MSHG(ms_card)) {
2534 if ((start_sector % 4) || (sector_cnt % 4)) {
2535 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2536 rw_tpc = PRO_READ_LONG_DATA;
2537 rw_cmd = PRO_READ_DATA;
2538 } else {
2539 rw_tpc = PRO_WRITE_LONG_DATA;
2540 rw_cmd = PRO_WRITE_DATA;
2541 }
2542 } else {
2543 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2544 rw_tpc = PRO_READ_QUAD_DATA;
2545 rw_cmd = PRO_READ_2K_DATA;
2546 } else {
2547 rw_tpc = PRO_WRITE_QUAD_DATA;
2548 rw_cmd = PRO_WRITE_2K_DATA;
2549 }
2550 mode_2k = 1;
2551 }
2552 } else {
2553 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2554 rw_tpc = PRO_READ_LONG_DATA;
2555 rw_cmd = PRO_READ_DATA;
2556 } else {
2557 rw_tpc = PRO_WRITE_LONG_DATA;
2558 rw_cmd = PRO_WRITE_DATA;
2559 }
2560 }
2561
2562 retval = ms_switch_clock(chip);
2563 if (retval != STATUS_SUCCESS)
2564 TRACE_RET(chip, STATUS_FAIL);
2565
2566 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2567 trans_mode = MS_TM_AUTO_READ;
2568 else
2569 trans_mode = MS_TM_AUTO_WRITE;
2570
2571 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
2572
2573 if (ms_card->seq_mode) {
2574 if ((ms_card->pre_dir != srb->sc_data_direction)
2575 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
2576 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2577 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2578 || !(val & MS_INT_BREQ)
2579 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2580 ms_card->seq_mode = 0;
2581 ms_card->total_sec_cnt = 0;
2582 if (val & MS_INT_BREQ) {
2583 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2584 if (retval != STATUS_SUCCESS)
2585 TRACE_RET(chip, STATUS_FAIL);
2586
2587 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2588 }
2589 }
2590 }
2591
2592 if (!ms_card->seq_mode) {
2593 ms_card->total_sec_cnt = 0;
2594 if (sector_cnt >= SEQ_START_CRITERIA) {
2595 if ((ms_card->capacity - start_sector) > 0xFE00)
2596 count = 0xFE00;
2597 else
2598 count = (u16)(ms_card->capacity - start_sector);
2599
2600 if (count > sector_cnt) {
2601 if (mode_2k)
2602 ms_card->seq_mode = MODE_2K_SEQ;
2603 else
2604 ms_card->seq_mode = MODE_512_SEQ;
2605 }
2606 } else {
2607 count = sector_cnt;
2608 }
2609 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2610 if (retval != STATUS_SUCCESS) {
2611 ms_card->seq_mode = 0;
2612 TRACE_RET(chip, STATUS_FAIL);
2613 }
2614 }
2615
2616 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
2617 WAIT_INT, mode_2k, scsi_sg_count(srb),
2618 scsi_sglist(srb), scsi_bufflen(srb));
2619 if (retval != STATUS_SUCCESS) {
2620 ms_card->seq_mode = 0;
2621 rtsx_read_register(chip, MS_TRANS_CFG, &val);
2622 rtsx_clear_ms_error(chip);
2623
2624 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2625 chip->rw_need_retry = 0;
2626 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n");
2627 TRACE_RET(chip, STATUS_FAIL);
2628 }
2629
2630 if (val & MS_INT_BREQ)
2631 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2632
2633 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2634 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n");
2635 chip->rw_need_retry = 1;
2636 ms_auto_tune_clock(chip);
2637 }
2638
2639 TRACE_RET(chip, retval);
2640 }
2641
2642 if (ms_card->seq_mode) {
2643 ms_card->pre_sec_addr = start_sector;
2644 ms_card->pre_sec_cnt = sector_cnt;
2645 ms_card->pre_dir = srb->sc_data_direction;
2646 ms_card->total_sec_cnt += sector_cnt;
2647 }
2648
2649 return STATUS_SUCCESS;
2650}
2651
2652static int mspro_read_format_progress(struct rtsx_chip *chip,
2653 const int short_data_len)
2654{
2655 struct ms_info *ms_card = &(chip->ms_card);
2656 int retval, i;
2657 u32 total_progress, cur_progress;
2658 u8 cnt, tmp;
2659 u8 data[8];
2660
2661 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n",
2662 short_data_len);
2663
2664 retval = ms_switch_clock(chip);
2665 if (retval != STATUS_SUCCESS) {
2666 ms_card->format_status = FORMAT_FAIL;
2667 TRACE_RET(chip, STATUS_FAIL);
2668 }
2669
2670 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2671 if (retval != STATUS_SUCCESS) {
2672 ms_card->format_status = FORMAT_FAIL;
2673 TRACE_RET(chip, STATUS_FAIL);
2674 }
2675
2676 if (!(tmp & MS_INT_BREQ)) {
2677 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2678 ms_card->format_status = FORMAT_SUCCESS;
2679 return STATUS_SUCCESS;
2680 }
2681 ms_card->format_status = FORMAT_FAIL;
2682 TRACE_RET(chip, STATUS_FAIL);
2683 }
2684
2685 if (short_data_len >= 256)
2686 cnt = 0;
2687 else
2688 cnt = (u8)short_data_len;
2689
2690 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
2691 MS_NO_CHECK_INT);
2692 if (retval != STATUS_SUCCESS) {
2693 ms_card->format_status = FORMAT_FAIL;
2694 TRACE_RET(chip, STATUS_FAIL);
2695 }
2696
2697 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
2698 data, 8);
2699 if (retval != STATUS_SUCCESS) {
2700 ms_card->format_status = FORMAT_FAIL;
2701 TRACE_RET(chip, STATUS_FAIL);
2702 }
2703
2704 total_progress = (data[0] << 24) | (data[1] << 16) |
2705 (data[2] << 8) | data[3];
2706 cur_progress = (data[4] << 24) | (data[5] << 16) |
2707 (data[6] << 8) | data[7];
2708
2709 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n",
2710 total_progress, cur_progress);
2711
2712 if (total_progress == 0) {
2713 ms_card->progress = 0;
2714 } else {
2715 u64 ulltmp = (u64)cur_progress * (u64)65535;
2716
2717 do_div(ulltmp, total_progress);
2718 ms_card->progress = (u16)ulltmp;
2719 }
2720 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress);
2721
2722 for (i = 0; i < 5000; i++) {
2723 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2724 if (retval != STATUS_SUCCESS) {
2725 ms_card->format_status = FORMAT_FAIL;
2726 TRACE_RET(chip, STATUS_FAIL);
2727 }
2728 if (tmp & (MS_INT_CED | MS_INT_CMDNK |
2729 MS_INT_BREQ | MS_INT_ERR))
2730 break;
2731
2732 wait_timeout(1);
2733 }
2734
2735 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
2736 if (retval != STATUS_SUCCESS) {
2737 ms_card->format_status = FORMAT_FAIL;
2738 TRACE_RET(chip, STATUS_FAIL);
2739 }
2740
2741 if (i == 5000) {
2742 ms_card->format_status = FORMAT_FAIL;
2743 TRACE_RET(chip, STATUS_FAIL);
2744 }
2745
2746 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2747 ms_card->format_status = FORMAT_FAIL;
2748 TRACE_RET(chip, STATUS_FAIL);
2749 }
2750
2751 if (tmp & MS_INT_CED) {
2752 ms_card->format_status = FORMAT_SUCCESS;
2753 ms_card->pro_under_formatting = 0;
2754 } else if (tmp & MS_INT_BREQ) {
2755 ms_card->format_status = FORMAT_IN_PROGRESS;
2756 } else {
2757 ms_card->format_status = FORMAT_FAIL;
2758 ms_card->pro_under_formatting = 0;
2759 TRACE_RET(chip, STATUS_FAIL);
2760 }
2761
2762 return STATUS_SUCCESS;
2763}
2764
2765void mspro_polling_format_status(struct rtsx_chip *chip)
2766{
2767 struct ms_info *ms_card = &(chip->ms_card);
2768 int i;
2769
2770 if (ms_card->pro_under_formatting &&
2771 (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
2772 rtsx_set_stat(chip, RTSX_STAT_RUN);
2773
2774 for (i = 0; i < 65535; i++) {
2775 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2776 if (ms_card->format_status != FORMAT_IN_PROGRESS)
2777 break;
2778 }
2779 }
2780}
2781
2782int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
2783 int short_data_len, int quick_format)
2784{
2785 struct ms_info *ms_card = &(chip->ms_card);
2786 int retval, i;
2787 u8 buf[8], tmp;
2788 u16 para;
2789
2790 retval = ms_switch_clock(chip);
2791 if (retval != STATUS_SUCCESS)
2792 TRACE_RET(chip, STATUS_FAIL);
2793
2794 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2795 if (retval != STATUS_SUCCESS)
2796 TRACE_RET(chip, STATUS_FAIL);
2797
2798 memset(buf, 0, 2);
2799 switch (short_data_len) {
2800 case 32:
2801 buf[0] = 0;
2802 break;
2803 case 64:
2804 buf[0] = 1;
2805 break;
2806 case 128:
2807 buf[0] = 2;
2808 break;
2809 case 256:
2810 default:
2811 buf[0] = 3;
2812 break;
2813 }
2814
2815 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2816 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
2817 NO_WAIT_INT, buf, 2);
2818 if (retval == STATUS_SUCCESS)
2819 break;
2820 }
2821 if (i == MS_MAX_RETRY_COUNT)
2822 TRACE_RET(chip, STATUS_FAIL);
2823
2824 if (quick_format)
2825 para = 0x0000;
2826 else
2827 para = 0x0001;
2828
2829 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
2830 if (retval != STATUS_SUCCESS)
2831 TRACE_RET(chip, STATUS_FAIL);
2832
2833 RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);
2834
2835 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
2836 TRACE_RET(chip, STATUS_FAIL);
2837
2838 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
2839 ms_card->pro_under_formatting = 1;
2840 ms_card->progress = 0;
2841 ms_card->format_status = FORMAT_IN_PROGRESS;
2842 return STATUS_SUCCESS;
2843 }
2844
2845 if (tmp & MS_INT_CED) {
2846 ms_card->pro_under_formatting = 0;
2847 ms_card->progress = 0;
2848 ms_card->format_status = FORMAT_SUCCESS;
2849 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
2850 return STATUS_SUCCESS;
2851 }
2852
2853 TRACE_RET(chip, STATUS_FAIL);
2854}
2855
2856
2857static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
2858 u16 log_blk, u8 start_page, u8 end_page,
2859 u8 *buf, unsigned int *index,
2860 unsigned int *offset)
2861{
2862 struct ms_info *ms_card = &(chip->ms_card);
2863 int retval, i;
2864 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
2865 u8 *ptr;
2866
2867 retval = ms_read_extra_data(chip, phy_blk, start_page,
2868 extra, MS_EXTRA_SIZE);
2869 if (retval == STATUS_SUCCESS) {
2870 if ((extra[1] & 0x30) != 0x30) {
2871 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2872 TRACE_RET(chip, STATUS_FAIL);
2873 }
2874 }
2875
2876 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
2877 SystemParm, 6);
2878 if (retval != STATUS_SUCCESS)
2879 TRACE_RET(chip, STATUS_FAIL);
2880
2881 if (CHK_MS4BIT(ms_card))
2882 data[0] = 0x88;
2883 else
2884 data[0] = 0x80;
2885
2886 data[1] = 0;
2887 data[2] = (u8)(phy_blk >> 8);
2888 data[3] = (u8)phy_blk;
2889 data[4] = 0;
2890 data[5] = start_page;
2891
2892 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2893 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
2894 data, 6);
2895 if (retval == STATUS_SUCCESS)
2896 break;
2897 }
2898 if (i == MS_MAX_RETRY_COUNT)
2899 TRACE_RET(chip, STATUS_FAIL);
2900
2901 ms_set_err_code(chip, MS_NO_ERROR);
2902
2903 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
2904 if (retval != STATUS_SUCCESS)
2905 TRACE_RET(chip, STATUS_FAIL);
2906
2907 ptr = buf;
2908
2909 for (page_addr = start_page; page_addr < end_page; page_addr++) {
2910 ms_set_err_code(chip, MS_NO_ERROR);
2911
2912 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2913 ms_set_err_code(chip, MS_NO_CARD);
2914 TRACE_RET(chip, STATUS_FAIL);
2915 }
2916
2917 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2918 if (retval != STATUS_SUCCESS)
2919 TRACE_RET(chip, STATUS_FAIL);
2920
2921 if (val & INT_REG_CMDNK) {
2922 ms_set_err_code(chip, MS_CMD_NK);
2923 TRACE_RET(chip, STATUS_FAIL);
2924 }
2925 if (val & INT_REG_ERR) {
2926 if (val & INT_REG_BREQ) {
2927 retval = ms_read_status_reg(chip);
2928 if (retval != STATUS_SUCCESS) {
2929 if (!(chip->card_wp & MS_CARD)) {
2930 reset_ms(chip);
2931 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
2932 ms_write_extra_data(chip, phy_blk,
2933 page_addr, extra, MS_EXTRA_SIZE);
2934 }
2935 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2936 TRACE_RET(chip, STATUS_FAIL);
2937 }
2938 } else {
2939 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2940 TRACE_RET(chip, STATUS_FAIL);
2941 }
2942 } else {
2943 if (!(val & INT_REG_BREQ)) {
2944 ms_set_err_code(chip, MS_BREQ_ERROR);
2945 TRACE_RET(chip, STATUS_FAIL);
2946 }
2947 }
2948
2949 if (page_addr == (end_page - 1)) {
2950 if (!(val & INT_REG_CED)) {
2951 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
2952 if (retval != STATUS_SUCCESS)
2953 TRACE_RET(chip, STATUS_FAIL);
2954 }
2955
2956 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
2957 &val, 1);
2958 if (retval != STATUS_SUCCESS)
2959 TRACE_RET(chip, STATUS_FAIL);
2960
2961 if (!(val & INT_REG_CED)) {
2962 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2963 TRACE_RET(chip, STATUS_FAIL);
2964 }
2965
2966 trans_cfg = NO_WAIT_INT;
2967 } else {
2968 trans_cfg = WAIT_INT;
2969 }
2970
2971 rtsx_init_cmd(chip);
2972
2973 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
2974 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
2975 0xFF, trans_cfg);
2976 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
2977 0x01, RING_BUFFER);
2978
2979 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
2980
2981 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
2982 MS_TRANSFER_START | MS_TM_NORMAL_READ);
2983 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
2984 MS_TRANSFER_END, MS_TRANSFER_END);
2985
2986 rtsx_send_cmd_no_wait(chip);
2987
2988 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
2989 512, scsi_sg_count(chip->srb),
2990 index, offset, DMA_FROM_DEVICE,
2991 chip->ms_timeout);
2992 if (retval < 0) {
2993 if (retval == -ETIMEDOUT) {
2994 ms_set_err_code(chip, MS_TO_ERROR);
2995 rtsx_clear_ms_error(chip);
2996 TRACE_RET(chip, STATUS_TIMEDOUT);
2997 }
2998
2999 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3000 if (retval != STATUS_SUCCESS) {
3001 ms_set_err_code(chip, MS_TO_ERROR);
3002 rtsx_clear_ms_error(chip);
3003 TRACE_RET(chip, STATUS_TIMEDOUT);
3004 }
3005 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3006 ms_set_err_code(chip, MS_CRC16_ERROR);
3007 rtsx_clear_ms_error(chip);
3008 TRACE_RET(chip, STATUS_FAIL);
3009 }
3010 }
3011
3012 if (scsi_sg_count(chip->srb) == 0)
3013 ptr += 512;
3014 }
3015
3016 return STATUS_SUCCESS;
3017}
3018
3019static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
3020 u16 new_blk, u16 log_blk, u8 start_page,
3021 u8 end_page, u8 *buf, unsigned int *index,
3022 unsigned int *offset)
3023{
3024 struct ms_info *ms_card = &(chip->ms_card);
3025 int retval, i;
3026 u8 page_addr, val, data[16];
3027 u8 *ptr;
3028
3029 if (!start_page) {
3030 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3031 SystemParm, 7);
3032 if (retval != STATUS_SUCCESS)
3033 TRACE_RET(chip, STATUS_FAIL);
3034
3035 if (CHK_MS4BIT(ms_card))
3036 data[0] = 0x88;
3037 else
3038 data[0] = 0x80;
3039
3040 data[1] = 0;
3041 data[2] = (u8)(old_blk >> 8);
3042 data[3] = (u8)old_blk;
3043 data[4] = 0x80;
3044 data[5] = 0;
3045 data[6] = 0xEF;
3046 data[7] = 0xFF;
3047
3048 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
3049 data, 8);
3050 if (retval != STATUS_SUCCESS)
3051 TRACE_RET(chip, STATUS_FAIL);
3052
3053 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3054 if (retval != STATUS_SUCCESS)
3055 TRACE_RET(chip, STATUS_FAIL);
3056
3057 ms_set_err_code(chip, MS_NO_ERROR);
3058 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3059 NO_WAIT_INT);
3060 if (retval != STATUS_SUCCESS)
3061 TRACE_RET(chip, STATUS_FAIL);
3062 }
3063
3064 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3065 SystemParm, (6 + MS_EXTRA_SIZE));
3066 if (retval != STATUS_SUCCESS)
3067 TRACE_RET(chip, STATUS_FAIL);
3068
3069 ms_set_err_code(chip, MS_NO_ERROR);
3070
3071 if (CHK_MS4BIT(ms_card))
3072 data[0] = 0x88;
3073 else
3074 data[0] = 0x80;
3075
3076 data[1] = 0;
3077 data[2] = (u8)(new_blk >> 8);
3078 data[3] = (u8)new_blk;
3079 if ((end_page - start_page) == 1)
3080 data[4] = 0x20;
3081 else
3082 data[4] = 0;
3083
3084 data[5] = start_page;
3085 data[6] = 0xF8;
3086 data[7] = 0xFF;
3087 data[8] = (u8)(log_blk >> 8);
3088 data[9] = (u8)log_blk;
3089
3090 for (i = 0x0A; i < 0x10; i++)
3091 data[i] = 0xFF;
3092
3093 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3094 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3095 NO_WAIT_INT, data, 16);
3096 if (retval == STATUS_SUCCESS)
3097 break;
3098 }
3099 if (i == MS_MAX_RETRY_COUNT)
3100 TRACE_RET(chip, STATUS_FAIL);
3101
3102 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3103 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3104 if (retval == STATUS_SUCCESS)
3105 break;
3106 }
3107 if (i == MS_MAX_RETRY_COUNT)
3108 TRACE_RET(chip, STATUS_FAIL);
3109
3110 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3111 if (retval != STATUS_SUCCESS)
3112 TRACE_RET(chip, STATUS_FAIL);
3113
3114 ptr = buf;
3115 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3116 ms_set_err_code(chip, MS_NO_ERROR);
3117
3118 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3119 ms_set_err_code(chip, MS_NO_CARD);
3120 TRACE_RET(chip, STATUS_FAIL);
3121 }
3122
3123 if (val & INT_REG_CMDNK) {
3124 ms_set_err_code(chip, MS_CMD_NK);
3125 TRACE_RET(chip, STATUS_FAIL);
3126 }
3127 if (val & INT_REG_ERR) {
3128 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3129 TRACE_RET(chip, STATUS_FAIL);
3130 }
3131 if (!(val & INT_REG_BREQ)) {
3132 ms_set_err_code(chip, MS_BREQ_ERROR);
3133 TRACE_RET(chip, STATUS_FAIL);
3134 }
3135
3136 udelay(30);
3137
3138 rtsx_init_cmd(chip);
3139
3140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
3141 0xFF, WRITE_PAGE_DATA);
3142 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3143 0xFF, WAIT_INT);
3144 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3145 0x01, RING_BUFFER);
3146
3147 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3148
3149 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3150 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3151 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3152 MS_TRANSFER_END, MS_TRANSFER_END);
3153
3154 rtsx_send_cmd_no_wait(chip);
3155
3156 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
3157 512, scsi_sg_count(chip->srb),
3158 index, offset, DMA_TO_DEVICE,
3159 chip->ms_timeout);
3160 if (retval < 0) {
3161 ms_set_err_code(chip, MS_TO_ERROR);
3162 rtsx_clear_ms_error(chip);
3163
3164 if (retval == -ETIMEDOUT)
3165 TRACE_RET(chip, STATUS_TIMEDOUT);
3166 else
3167 TRACE_RET(chip, STATUS_FAIL);
3168 }
3169
3170 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3171 if (retval != STATUS_SUCCESS)
3172 TRACE_RET(chip, STATUS_FAIL);
3173
3174 if ((end_page - start_page) == 1) {
3175 if (!(val & INT_REG_CED)) {
3176 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3177 TRACE_RET(chip, STATUS_FAIL);
3178 }
3179 } else {
3180 if (page_addr == (end_page - 1)) {
3181 if (!(val & INT_REG_CED)) {
3182 retval = ms_send_cmd(chip, BLOCK_END,
3183 WAIT_INT);
3184 if (retval != STATUS_SUCCESS)
3185 TRACE_RET(chip, STATUS_FAIL);
3186 }
3187
3188 retval = ms_read_bytes(chip, GET_INT, 1,
3189 NO_WAIT_INT, &val, 1);
3190 if (retval != STATUS_SUCCESS)
3191 TRACE_RET(chip, STATUS_FAIL);
3192 }
3193
3194 if ((page_addr == (end_page - 1)) ||
3195 (page_addr == ms_card->page_off)) {
3196 if (!(val & INT_REG_CED)) {
3197 ms_set_err_code(chip,
3198 MS_FLASH_WRITE_ERROR);
3199 TRACE_RET(chip, STATUS_FAIL);
3200 }
3201 }
3202 }
3203
3204 if (scsi_sg_count(chip->srb) == 0)
3205 ptr += 512;
3206 }
3207
3208 return STATUS_SUCCESS;
3209}
3210
3211
3212static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3213 u16 log_blk, u8 page_off)
3214{
3215 struct ms_info *ms_card = &(chip->ms_card);
3216 int retval, seg_no;
3217
3218 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3219 page_off, ms_card->page_off + 1);
3220 if (retval != STATUS_SUCCESS)
3221 TRACE_RET(chip, STATUS_FAIL);
3222
3223 seg_no = old_blk >> 9;
3224
3225 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3226 MS_CLR_BAD_BLOCK_FLG(ms_card);
3227 ms_set_bad_block(chip, old_blk);
3228 } else {
3229 retval = ms_erase_block(chip, old_blk);
3230 if (retval == STATUS_SUCCESS)
3231 ms_set_unused_block(chip, old_blk);
3232 }
3233
3234 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3235
3236 return STATUS_SUCCESS;
3237}
3238
3239static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3240 u16 log_blk, u8 start_page)
3241{
3242 int retval;
3243
3244 if (start_page) {
3245 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3246 0, start_page);
3247 if (retval != STATUS_SUCCESS)
3248 TRACE_RET(chip, STATUS_FAIL);
3249 }
3250
3251 return STATUS_SUCCESS;
3252}
3253
3254#ifdef MS_DELAY_WRITE
3255int ms_delay_write(struct rtsx_chip *chip)
3256{
3257 struct ms_info *ms_card = &(chip->ms_card);
3258 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3259 int retval;
3260
3261 if (delay_write->delay_write_flag) {
3262 retval = ms_set_init_para(chip);
3263 if (retval != STATUS_SUCCESS)
3264 TRACE_RET(chip, STATUS_FAIL);
3265
3266 delay_write->delay_write_flag = 0;
3267 retval = ms_finish_write(chip,
3268 delay_write->old_phyblock,
3269 delay_write->new_phyblock,
3270 delay_write->logblock,
3271 delay_write->pageoff);
3272 if (retval != STATUS_SUCCESS)
3273 TRACE_RET(chip, STATUS_FAIL);
3274 }
3275
3276 return STATUS_SUCCESS;
3277}
3278#endif
3279
3280static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3281{
3282 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3283 set_sense_type(chip, SCSI_LUN(srb),
3284 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3285 else
3286 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3287}
3288
3289static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3290 u32 start_sector, u16 sector_cnt)
3291{
3292 struct ms_info *ms_card = &(chip->ms_card);
3293 unsigned int lun = SCSI_LUN(srb);
3294 int retval, seg_no;
3295 unsigned int index = 0, offset = 0;
3296 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3297 u8 start_page, end_page = 0, page_cnt;
3298 u8 *ptr;
3299#ifdef MS_DELAY_WRITE
3300 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3301#endif
3302
3303 ms_set_err_code(chip, MS_NO_ERROR);
3304
3305 ms_card->cleanup_counter = 0;
3306
3307 ptr = (u8 *)scsi_sglist(srb);
3308
3309 retval = ms_switch_clock(chip);
3310 if (retval != STATUS_SUCCESS) {
3311 ms_rw_fail(srb, chip);
3312 TRACE_RET(chip, STATUS_FAIL);
3313 }
3314
3315 log_blk = (u16)(start_sector >> ms_card->block_shift);
3316 start_page = (u8)(start_sector & ms_card->page_off);
3317
3318 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3319 if (log_blk < ms_start_idx[seg_no+1])
3320 break;
3321 }
3322
3323 if (ms_card->segment[seg_no].build_flag == 0) {
3324 retval = ms_build_l2p_tbl(chip, seg_no);
3325 if (retval != STATUS_SUCCESS) {
3326 chip->card_fail |= MS_CARD;
3327 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3328 TRACE_RET(chip, STATUS_FAIL);
3329 }
3330 }
3331
3332 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3333#ifdef MS_DELAY_WRITE
3334 if (delay_write->delay_write_flag &&
3335 (delay_write->logblock == log_blk) &&
3336 (start_page > delay_write->pageoff)) {
3337 delay_write->delay_write_flag = 0;
3338 retval = ms_copy_page(chip,
3339 delay_write->old_phyblock,
3340 delay_write->new_phyblock, log_blk,
3341 delay_write->pageoff, start_page);
3342 if (retval != STATUS_SUCCESS) {
3343 set_sense_type(chip, lun,
3344 SENSE_TYPE_MEDIA_WRITE_ERR);
3345 TRACE_RET(chip, STATUS_FAIL);
3346 }
3347 old_blk = delay_write->old_phyblock;
3348 new_blk = delay_write->new_phyblock;
3349 } else if (delay_write->delay_write_flag &&
3350 (delay_write->logblock == log_blk) &&
3351 (start_page == delay_write->pageoff)) {
3352 delay_write->delay_write_flag = 0;
3353 old_blk = delay_write->old_phyblock;
3354 new_blk = delay_write->new_phyblock;
3355 } else {
3356 retval = ms_delay_write(chip);
3357 if (retval != STATUS_SUCCESS) {
3358 set_sense_type(chip, lun,
3359 SENSE_TYPE_MEDIA_WRITE_ERR);
3360 TRACE_RET(chip, STATUS_FAIL);
3361 }
3362#endif
3363 old_blk = ms_get_l2p_tbl(chip, seg_no,
3364 log_blk - ms_start_idx[seg_no]);
3365 new_blk = ms_get_unused_block(chip, seg_no);
3366 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3367 set_sense_type(chip, lun,
3368 SENSE_TYPE_MEDIA_WRITE_ERR);
3369 TRACE_RET(chip, STATUS_FAIL);
3370 }
3371
3372 retval = ms_prepare_write(chip, old_blk, new_blk,
3373 log_blk, start_page);
3374 if (retval != STATUS_SUCCESS) {
3375 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3376 set_sense_type(chip, lun,
3377 SENSE_TYPE_MEDIA_NOT_PRESENT);
3378 TRACE_RET(chip, STATUS_FAIL);
3379 }
3380 set_sense_type(chip, lun,
3381 SENSE_TYPE_MEDIA_WRITE_ERR);
3382 TRACE_RET(chip, STATUS_FAIL);
3383 }
3384#ifdef MS_DELAY_WRITE
3385 }
3386#endif
3387 } else {
3388#ifdef MS_DELAY_WRITE
3389 retval = ms_delay_write(chip);
3390 if (retval != STATUS_SUCCESS) {
3391 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3392 set_sense_type(chip, lun,
3393 SENSE_TYPE_MEDIA_NOT_PRESENT);
3394 TRACE_RET(chip, STATUS_FAIL);
3395 }
3396 set_sense_type(chip, lun,
3397 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3398 TRACE_RET(chip, STATUS_FAIL);
3399 }
3400#endif
3401 old_blk = ms_get_l2p_tbl(chip, seg_no,
3402 log_blk - ms_start_idx[seg_no]);
3403 if (old_blk == 0xFFFF) {
3404 set_sense_type(chip, lun,
3405 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3406 TRACE_RET(chip, STATUS_FAIL);
3407 }
3408 }
3409
3410 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3411 seg_no, old_blk, new_blk);
3412
3413 while (total_sec_cnt) {
3414 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3415 end_page = ms_card->page_off + 1;
3416 else
3417 end_page = start_page + (u8)total_sec_cnt;
3418
3419 page_cnt = end_page - start_page;
3420
3421 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n",
3422 start_page, end_page, page_cnt);
3423
3424 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3425 retval = ms_read_multiple_pages(chip,
3426 old_blk, log_blk, start_page, end_page,
3427 ptr, &index, &offset);
3428 } else {
3429 retval = ms_write_multiple_pages(chip, old_blk,
3430 new_blk, log_blk, start_page, end_page,
3431 ptr, &index, &offset);
3432 }
3433
3434 if (retval != STATUS_SUCCESS) {
3435 toggle_gpio(chip, 1);
3436 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3437 set_sense_type(chip, lun,
3438 SENSE_TYPE_MEDIA_NOT_PRESENT);
3439 TRACE_RET(chip, STATUS_FAIL);
3440 }
3441 ms_rw_fail(srb, chip);
3442 TRACE_RET(chip, STATUS_FAIL);
3443 }
3444
3445 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3446 if (end_page == (ms_card->page_off + 1)) {
3447 retval = ms_erase_block(chip, old_blk);
3448 if (retval == STATUS_SUCCESS)
3449 ms_set_unused_block(chip, old_blk);
3450
3451 ms_set_l2p_tbl(chip, seg_no,
3452 log_blk - ms_start_idx[seg_no],
3453 new_blk);
3454 }
3455 }
3456
3457 total_sec_cnt -= page_cnt;
3458 if (scsi_sg_count(srb) == 0)
3459 ptr += page_cnt * 512;
3460
3461 if (total_sec_cnt == 0)
3462 break;
3463
3464 log_blk++;
3465
3466 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
3467 seg_no++) {
3468 if (log_blk < ms_start_idx[seg_no+1])
3469 break;
3470 }
3471
3472 if (ms_card->segment[seg_no].build_flag == 0) {
3473 retval = ms_build_l2p_tbl(chip, seg_no);
3474 if (retval != STATUS_SUCCESS) {
3475 chip->card_fail |= MS_CARD;
3476 set_sense_type(chip, lun,
3477 SENSE_TYPE_MEDIA_NOT_PRESENT);
3478 TRACE_RET(chip, STATUS_FAIL);
3479 }
3480 }
3481
3482 old_blk = ms_get_l2p_tbl(chip, seg_no,
3483 log_blk - ms_start_idx[seg_no]);
3484 if (old_blk == 0xFFFF) {
3485 ms_rw_fail(srb, chip);
3486 TRACE_RET(chip, STATUS_FAIL);
3487 }
3488
3489 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3490 new_blk = ms_get_unused_block(chip, seg_no);
3491 if (new_blk == 0xFFFF) {
3492 ms_rw_fail(srb, chip);
3493 TRACE_RET(chip, STATUS_FAIL);
3494 }
3495 }
3496
3497 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3498 seg_no, old_blk, new_blk);
3499
3500 start_page = 0;
3501 }
3502
3503 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3504 if (end_page < (ms_card->page_off + 1)) {
3505#ifdef MS_DELAY_WRITE
3506 delay_write->delay_write_flag = 1;
3507 delay_write->old_phyblock = old_blk;
3508 delay_write->new_phyblock = new_blk;
3509 delay_write->logblock = log_blk;
3510 delay_write->pageoff = end_page;
3511#else
3512 retval = ms_finish_write(chip, old_blk, new_blk,
3513 log_blk, end_page);
3514 if (retval != STATUS_SUCCESS) {
3515 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3516 set_sense_type(chip, lun,
3517 SENSE_TYPE_MEDIA_NOT_PRESENT);
3518 TRACE_RET(chip, STATUS_FAIL);
3519 }
3520
3521 ms_rw_fail(srb, chip);
3522 TRACE_RET(chip, STATUS_FAIL);
3523 }
3524#endif
3525 }
3526 }
3527
3528 scsi_set_resid(srb, 0);
3529
3530 return STATUS_SUCCESS;
3531}
3532
3533int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3534 u32 start_sector, u16 sector_cnt)
3535{
3536 struct ms_info *ms_card = &(chip->ms_card);
3537 int retval;
3538
3539 if (CHK_MSPRO(ms_card))
3540 retval = mspro_rw_multi_sector(srb, chip, start_sector,
3541 sector_cnt);
3542 else
3543 retval = ms_rw_multi_sector(srb, chip, start_sector,
3544 sector_cnt);
3545
3546 return retval;
3547}
3548
3549
3550void ms_free_l2p_tbl(struct rtsx_chip *chip)
3551{
3552 struct ms_info *ms_card = &(chip->ms_card);
3553 int i = 0;
3554
3555 if (ms_card->segment != NULL) {
3556 for (i = 0; i < ms_card->segment_cnt; i++) {
3557 if (ms_card->segment[i].l2p_table != NULL) {
3558 vfree(ms_card->segment[i].l2p_table);
3559 ms_card->segment[i].l2p_table = NULL;
3560 }
3561 if (ms_card->segment[i].free_table != NULL) {
3562 vfree(ms_card->segment[i].free_table);
3563 ms_card->segment[i].free_table = NULL;
3564 }
3565 }
3566 vfree(ms_card->segment);
3567 ms_card->segment = NULL;
3568 }
3569}
3570
3571#ifdef SUPPORT_MAGIC_GATE
3572
3573#ifdef READ_BYTES_WAIT_INT
3574static int ms_poll_int(struct rtsx_chip *chip)
3575{
3576 int retval;
3577 u8 val;
3578
3579 rtsx_init_cmd(chip);
3580
3581 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
3582
3583 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
3584 if (retval != STATUS_SUCCESS)
3585 TRACE_RET(chip, STATUS_FAIL);
3586
3587 val = *rtsx_get_cmd_data(chip);
3588 if (val & MS_INT_ERR)
3589 TRACE_RET(chip, STATUS_FAIL);
3590
3591 return STATUS_SUCCESS;
3592}
3593#endif
3594
3595#ifdef MS_SAMPLE_INT_ERR
3596static int check_ms_err(struct rtsx_chip *chip)
3597{
3598 int retval;
3599 u8 val;
3600
3601 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3602 if (retval != STATUS_SUCCESS)
3603 return 1;
3604 if (val & MS_TRANSFER_ERR)
3605 return 1;
3606
3607 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3608 if (retval != STATUS_SUCCESS)
3609 return 1;
3610
3611 if (val & (MS_INT_ERR | MS_INT_CMDNK))
3612 return 1;
3613
3614 return 0;
3615}
3616#else
3617static int check_ms_err(struct rtsx_chip *chip)
3618{
3619 int retval;
3620 u8 val;
3621
3622 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3623 if (retval != STATUS_SUCCESS)
3624 return 1;
3625 if (val & MS_TRANSFER_ERR)
3626 return 1;
3627
3628 return 0;
3629}
3630#endif
3631
3632static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
3633{
3634 int retval, i;
3635 u8 data[8];
3636
3637 data[0] = cmd;
3638 data[1] = 0;
3639 data[2] = 0;
3640 data[3] = 0;
3641 data[4] = 0;
3642 data[5] = 0;
3643 data[6] = entry_num;
3644 data[7] = 0;
3645
3646 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3647 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
3648 data, 8);
3649 if (retval == STATUS_SUCCESS)
3650 break;
3651 }
3652 if (i == MS_MAX_RETRY_COUNT)
3653 TRACE_RET(chip, STATUS_FAIL);
3654
3655 if (check_ms_err(chip)) {
3656 rtsx_clear_ms_error(chip);
3657 TRACE_RET(chip, STATUS_FAIL);
3658 }
3659
3660 return STATUS_SUCCESS;
3661}
3662
3663static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
3664 u8 mg_entry_num)
3665{
3666 int retval;
3667 u8 buf[6];
3668
3669 if (type == 0)
3670 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
3671 else
3672 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
3673
3674 if (retval != STATUS_SUCCESS)
3675 TRACE_RET(chip, STATUS_FAIL);
3676
3677 buf[0] = 0;
3678 buf[1] = 0;
3679 if (type == 1) {
3680 buf[2] = 0;
3681 buf[3] = 0;
3682 buf[4] = 0;
3683 buf[5] = mg_entry_num;
3684 }
3685 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
3686 NO_WAIT_INT, buf, 6);
3687 if (retval != STATUS_SUCCESS)
3688 TRACE_RET(chip, STATUS_FAIL);
3689
3690 return STATUS_SUCCESS;
3691}
3692
3693int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3694{
3695 int retval;
3696 int i;
3697 unsigned int lun = SCSI_LUN(srb);
3698 u8 buf1[32], buf2[12];
3699
3700 if (scsi_bufflen(srb) < 12) {
3701 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3702 TRACE_RET(chip, STATUS_FAIL);
3703 }
3704
3705 ms_cleanup_work(chip);
3706
3707 retval = ms_switch_clock(chip);
3708 if (retval != STATUS_SUCCESS)
3709 TRACE_RET(chip, STATUS_FAIL);
3710
3711 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
3712 if (retval != STATUS_SUCCESS) {
3713 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3714 TRACE_RET(chip, STATUS_FAIL);
3715 }
3716
3717 memset(buf1, 0, 32);
3718 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
3719 for (i = 0; i < 8; i++)
3720 buf1[8+i] = buf2[4+i];
3721
3722 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
3723 buf1, 32);
3724 if (retval != STATUS_SUCCESS) {
3725 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3726 TRACE_RET(chip, STATUS_FAIL);
3727 }
3728 if (check_ms_err(chip)) {
3729 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3730 rtsx_clear_ms_error(chip);
3731 TRACE_RET(chip, STATUS_FAIL);
3732 }
3733
3734 return STATUS_SUCCESS;
3735}
3736
3737int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3738{
3739 int retval = STATUS_FAIL;
3740 int bufflen;
3741 unsigned int lun = SCSI_LUN(srb);
3742 u8 *buf = NULL;
3743
3744 ms_cleanup_work(chip);
3745
3746 retval = ms_switch_clock(chip);
3747 if (retval != STATUS_SUCCESS)
3748 TRACE_RET(chip, STATUS_FAIL);
3749
3750 buf = kmalloc(1540, GFP_KERNEL);
3751 if (!buf)
3752 TRACE_RET(chip, STATUS_ERROR);
3753
3754 buf[0] = 0x04;
3755 buf[1] = 0x1A;
3756 buf[2] = 0x00;
3757 buf[3] = 0x00;
3758
3759 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
3760 if (retval != STATUS_SUCCESS) {
3761 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3762 TRACE_GOTO(chip, GetEKBFinish);
3763 }
3764
3765 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3766 3, WAIT_INT, 0, 0, buf + 4, 1536);
3767 if (retval != STATUS_SUCCESS) {
3768 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3769 rtsx_clear_ms_error(chip);
3770 TRACE_GOTO(chip, GetEKBFinish);
3771 }
3772 if (check_ms_err(chip)) {
3773 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3774 rtsx_clear_ms_error(chip);
3775 TRACE_RET(chip, STATUS_FAIL);
3776 }
3777
3778 bufflen = min_t(int, 1052, scsi_bufflen(srb));
3779 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
3780
3781GetEKBFinish:
3782 kfree(buf);
3783 return retval;
3784}
3785
3786int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3787{
3788 struct ms_info *ms_card = &(chip->ms_card);
3789 int retval;
3790 int bufflen;
3791 int i;
3792 unsigned int lun = SCSI_LUN(srb);
3793 u8 buf[32];
3794
3795 ms_cleanup_work(chip);
3796
3797 retval = ms_switch_clock(chip);
3798 if (retval != STATUS_SUCCESS)
3799 TRACE_RET(chip, STATUS_FAIL);
3800
3801 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
3802 if (retval != STATUS_SUCCESS) {
3803 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3804 TRACE_RET(chip, STATUS_FAIL);
3805 }
3806
3807 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
3808 buf, 32);
3809 if (retval != STATUS_SUCCESS) {
3810 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3811 TRACE_RET(chip, STATUS_FAIL);
3812 }
3813 if (check_ms_err(chip)) {
3814 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3815 rtsx_clear_ms_error(chip);
3816 TRACE_RET(chip, STATUS_FAIL);
3817 }
3818
3819 memcpy(ms_card->magic_gate_id, buf, 16);
3820
3821#ifdef READ_BYTES_WAIT_INT
3822 retval = ms_poll_int(chip);
3823 if (retval != STATUS_SUCCESS) {
3824 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3825 TRACE_RET(chip, STATUS_FAIL);
3826 }
3827#endif
3828
3829 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
3830 if (retval != STATUS_SUCCESS) {
3831 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3832 TRACE_RET(chip, STATUS_FAIL);
3833 }
3834
3835 bufflen = min_t(int, 12, scsi_bufflen(srb));
3836 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3837
3838 for (i = 0; i < 8; i++)
3839 buf[i] = buf[4+i];
3840
3841 for (i = 0; i < 24; i++)
3842 buf[8+i] = 0;
3843
3844 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
3845 32, WAIT_INT, buf, 32);
3846 if (retval != STATUS_SUCCESS) {
3847 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3848 TRACE_RET(chip, STATUS_FAIL);
3849 }
3850 if (check_ms_err(chip)) {
3851 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3852 rtsx_clear_ms_error(chip);
3853 TRACE_RET(chip, STATUS_FAIL);
3854 }
3855
3856 ms_card->mg_auth = 0;
3857
3858 return STATUS_SUCCESS;
3859}
3860
3861int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3862{
3863 struct ms_info *ms_card = &(chip->ms_card);
3864 int retval;
3865 int bufflen;
3866 unsigned int lun = SCSI_LUN(srb);
3867 u8 buf1[32], buf2[36];
3868
3869 ms_cleanup_work(chip);
3870
3871 retval = ms_switch_clock(chip);
3872 if (retval != STATUS_SUCCESS)
3873 TRACE_RET(chip, STATUS_FAIL);
3874
3875 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
3876 if (retval != STATUS_SUCCESS) {
3877 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3878 TRACE_RET(chip, STATUS_FAIL);
3879 }
3880
3881 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
3882 buf1, 32);
3883 if (retval != STATUS_SUCCESS) {
3884 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3885 TRACE_RET(chip, STATUS_FAIL);
3886 }
3887 if (check_ms_err(chip)) {
3888 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3889 rtsx_clear_ms_error(chip);
3890 TRACE_RET(chip, STATUS_FAIL);
3891 }
3892
3893 buf2[0] = 0x00;
3894 buf2[1] = 0x22;
3895 buf2[2] = 0x00;
3896 buf2[3] = 0x00;
3897
3898 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
3899 memcpy(buf2 + 20, buf1, 16);
3900
3901 bufflen = min_t(int, 36, scsi_bufflen(srb));
3902 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
3903
3904#ifdef READ_BYTES_WAIT_INT
3905 retval = ms_poll_int(chip);
3906 if (retval != STATUS_SUCCESS) {
3907 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3908 TRACE_RET(chip, STATUS_FAIL);
3909 }
3910#endif
3911
3912 return STATUS_SUCCESS;
3913}
3914
3915int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3916{
3917 struct ms_info *ms_card = &(chip->ms_card);
3918 int retval;
3919 int i;
3920 int bufflen;
3921 unsigned int lun = SCSI_LUN(srb);
3922 u8 buf[32];
3923
3924 ms_cleanup_work(chip);
3925
3926 retval = ms_switch_clock(chip);
3927 if (retval != STATUS_SUCCESS)
3928 TRACE_RET(chip, STATUS_FAIL);
3929
3930 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
3931 if (retval != STATUS_SUCCESS) {
3932 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3933 TRACE_RET(chip, STATUS_FAIL);
3934 }
3935
3936 bufflen = min_t(int, 12, scsi_bufflen(srb));
3937 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3938
3939 for (i = 0; i < 8; i++)
3940 buf[i] = buf[4+i];
3941
3942 for (i = 0; i < 24; i++)
3943 buf[8+i] = 0;
3944
3945 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
3946 buf, 32);
3947 if (retval != STATUS_SUCCESS) {
3948 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3949 TRACE_RET(chip, STATUS_FAIL);
3950 }
3951 if (check_ms_err(chip)) {
3952 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3953 rtsx_clear_ms_error(chip);
3954 TRACE_RET(chip, STATUS_FAIL);
3955 }
3956
3957 ms_card->mg_auth = 1;
3958
3959 return STATUS_SUCCESS;
3960}
3961
3962int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3963{
3964 struct ms_info *ms_card = &(chip->ms_card);
3965 int retval;
3966 int bufflen;
3967 unsigned int lun = SCSI_LUN(srb);
3968 u8 *buf = NULL;
3969
3970 ms_cleanup_work(chip);
3971
3972 retval = ms_switch_clock(chip);
3973 if (retval != STATUS_SUCCESS)
3974 TRACE_RET(chip, STATUS_FAIL);
3975
3976 buf = kmalloc(1028, GFP_KERNEL);
3977 if (!buf)
3978 TRACE_RET(chip, STATUS_ERROR);
3979
3980 buf[0] = 0x04;
3981 buf[1] = 0x02;
3982 buf[2] = 0x00;
3983 buf[3] = 0x00;
3984
3985 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
3986 if (retval != STATUS_SUCCESS) {
3987 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3988 TRACE_GOTO(chip, GetICVFinish);
3989 }
3990
3991 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3992 2, WAIT_INT, 0, 0, buf + 4, 1024);
3993 if (retval != STATUS_SUCCESS) {
3994 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3995 rtsx_clear_ms_error(chip);
3996 TRACE_GOTO(chip, GetICVFinish);
3997 }
3998 if (check_ms_err(chip)) {
3999 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4000 rtsx_clear_ms_error(chip);
4001 TRACE_RET(chip, STATUS_FAIL);
4002 }
4003
4004 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4005 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4006
4007GetICVFinish:
4008 kfree(buf);
4009 return retval;
4010}
4011
4012int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4013{
4014 struct ms_info *ms_card = &(chip->ms_card);
4015 int retval;
4016 int bufflen;
4017#ifdef MG_SET_ICV_SLOW
4018 int i;
4019#endif
4020 unsigned int lun = SCSI_LUN(srb);
4021 u8 *buf = NULL;
4022
4023 ms_cleanup_work(chip);
4024
4025 retval = ms_switch_clock(chip);
4026 if (retval != STATUS_SUCCESS)
4027 TRACE_RET(chip, STATUS_FAIL);
4028
4029 buf = kmalloc(1028, GFP_KERNEL);
4030 if (!buf)
4031 TRACE_RET(chip, STATUS_ERROR);
4032
4033 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4034 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4035
4036 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4037 if (retval != STATUS_SUCCESS) {
4038 if (ms_card->mg_auth == 0) {
4039 if ((buf[5] & 0xC0) != 0)
4040 set_sense_type(chip, lun,
4041 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4042 else
4043 set_sense_type(chip, lun,
4044 SENSE_TYPE_MG_WRITE_ERR);
4045 } else {
4046 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4047 }
4048 TRACE_GOTO(chip, SetICVFinish);
4049 }
4050
4051#ifdef MG_SET_ICV_SLOW
4052 for (i = 0; i < 2; i++) {
4053 udelay(50);
4054
4055 rtsx_init_cmd(chip);
4056
4057 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
4058 0xFF, PRO_WRITE_LONG_DATA);
4059 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4060 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4061 0x01, RING_BUFFER);
4062
4063 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4064
4065 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4066 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4067 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
4068 MS_TRANSFER_END, MS_TRANSFER_END);
4069
4070 rtsx_send_cmd_no_wait(chip);
4071
4072 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512,
4073 512, 0, DMA_TO_DEVICE, 3000);
4074 if ((retval < 0) || check_ms_err(chip)) {
4075 rtsx_clear_ms_error(chip);
4076 if (ms_card->mg_auth == 0) {
4077 if ((buf[5] & 0xC0) != 0)
4078 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4079 else
4080 set_sense_type(chip, lun,
4081 SENSE_TYPE_MG_WRITE_ERR);
4082 } else {
4083 set_sense_type(chip, lun,
4084 SENSE_TYPE_MG_WRITE_ERR);
4085 }
4086 retval = STATUS_FAIL;
4087 TRACE_GOTO(chip, SetICVFinish);
4088 }
4089 }
4090#else
4091 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4092 2, WAIT_INT, 0, 0, buf + 4, 1024);
4093 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
4094 rtsx_clear_ms_error(chip);
4095 if (ms_card->mg_auth == 0) {
4096 if ((buf[5] & 0xC0) != 0)
4097 set_sense_type(chip, lun,
4098 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4099 else
4100 set_sense_type(chip, lun,
4101 SENSE_TYPE_MG_WRITE_ERR);
4102 } else {
4103 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4104 }
4105 TRACE_GOTO(chip, SetICVFinish);
4106 }
4107#endif
4108
4109SetICVFinish:
4110 kfree(buf);
4111 return retval;
4112}
4113
4114#endif
4115
4116void ms_cleanup_work(struct rtsx_chip *chip)
4117{
4118 struct ms_info *ms_card = &(chip->ms_card);
4119
4120 if (CHK_MSPRO(ms_card)) {
4121 if (ms_card->seq_mode) {
4122 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n");
4123 mspro_stop_seq_mode(chip);
4124 ms_card->cleanup_counter = 0;
4125 }
4126 if (CHK_MSHG(ms_card)) {
4127 rtsx_write_register(chip, MS_CFG,
4128 MS_2K_SECTOR_MODE, 0x00);
4129 }
4130 }
4131#ifdef MS_DELAY_WRITE
4132 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
4133 dev_dbg(rtsx_dev(chip), "MS: delay write\n");
4134 ms_delay_write(chip);
4135 ms_card->cleanup_counter = 0;
4136 }
4137#endif
4138}
4139
4140int ms_power_off_card3v3(struct rtsx_chip *chip)
4141{
4142 int retval;
4143
4144 retval = disable_card_clock(chip, MS_CARD);
4145 if (retval != STATUS_SUCCESS)
4146 TRACE_RET(chip, STATUS_FAIL);
4147
4148 if (chip->asic_code) {
4149 retval = ms_pull_ctl_disable(chip);
4150 if (retval != STATUS_SUCCESS)
4151 TRACE_RET(chip, STATUS_FAIL);
4152 } else {
4153 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4154 FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);
4155 }
4156 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);
4157 if (!chip->ft2_fast_mode) {
4158 retval = card_power_off(chip, MS_CARD);
4159 if (retval != STATUS_SUCCESS)
4160 TRACE_RET(chip, STATUS_FAIL);
4161 }
4162
4163 return STATUS_SUCCESS;
4164}
4165
4166int release_ms_card(struct rtsx_chip *chip)
4167{
4168 struct ms_info *ms_card = &(chip->ms_card);
4169 int retval;
4170
4171#ifdef MS_DELAY_WRITE
4172 ms_card->delay_write.delay_write_flag = 0;
4173#endif
4174 ms_card->pro_under_formatting = 0;
4175
4176 chip->card_ready &= ~MS_CARD;
4177 chip->card_fail &= ~MS_CARD;
4178 chip->card_wp &= ~MS_CARD;
4179
4180 ms_free_l2p_tbl(chip);
4181
4182 memset(ms_card->raw_sys_info, 0, 96);
4183#ifdef SUPPORT_PCGL_1P18
4184 memset(ms_card->raw_model_name, 0, 48);
4185#endif
4186
4187 retval = ms_power_off_card3v3(chip);
4188 if (retval != STATUS_SUCCESS)
4189 TRACE_RET(chip, STATUS_FAIL);
4190
4191 return STATUS_SUCCESS;
4192}
4193
