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28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
69#include <linux/synclink.h>
70
71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <asm/uaccess.h>
83
84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC,
86 0,
87 HDLC_FLAG_UNDERRUN_ABORT15,
88 HDLC_ENCODING_NRZI_SPACE,
89 0,
90 0xff,
91 HDLC_CRC_16_CCITT,
92 HDLC_PREAMBLE_LENGTH_8BITS,
93 HDLC_PREAMBLE_PATTERN_NONE,
94 9600,
95 8,
96 1,
97 ASYNC_PARITY_NONE
98};
99
100
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110
111typedef struct _SCADESC
112{
113 u16 next;
114 u16 buf_ptr;
115 u8 buf_base;
116 u8 pad1;
117 u16 length;
118 u8 status;
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124
125 char *virt_addr;
126 u16 phys_entry;
127} SCADESC_EX, *PSCADESC_EX;
128
129
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148
149
150
151typedef struct _synclinkmp_info {
152 void *if_ptr;
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait;
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char;
163 u16 read_status_mask1;
164 u16 read_status_mask2;
165 unsigned char ignore_status_mask1;
166 unsigned char ignore_status_mask2;
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer;
175 struct _synclinkmp_info *next_device;
176 struct timer_list status_timer;
177
178 spinlock_t lock;
179 struct work_struct task;
180
181 u32 max_frame_size;
182
183 u32 pending_bh;
184
185 bool bh_running;
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount;
190 int cts_chkcount;
191 int dsr_chkcount;
192 int ri_chkcount;
193
194 char *buffer_list;
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count;
198 SCADESC *rx_buf_list;
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC];
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count;
203 SCADESC *tx_buf_list;
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC];
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25];
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type;
232
233 unsigned int irq_level;
234 unsigned long irq_flags;
235 bool irq_requested;
236
237 MGSL_PARAMS params;
238
239 unsigned char serial_signals;
240
241 bool irq_occurred;
242 unsigned int init_error;
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base;
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base;
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base;
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base;
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270
271 int netcount;
272 spinlock_t netlock;
273
274#if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276#endif
277
278} SLMP_INFO;
279
280#define MGSL_MAGIC 0x5401
281
282
283
284
285#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8)
286#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8)
287#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8)
288#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8)
289
290
291#define LPR 0x00
292#define PABR0 0x02
293#define PABR1 0x03
294#define WCRL 0x04
295#define WCRM 0x05
296#define WCRH 0x06
297#define DPCR 0x08
298#define DMER 0x09
299#define ISR0 0x10
300#define ISR1 0x11
301#define ISR2 0x12
302#define IER0 0x14
303#define IER1 0x15
304#define IER2 0x16
305#define ITCR 0x18
306#define INTVR 0x1a
307#define IMVR 0x1c
308
309
310#define TRB 0x20
311#define TRBL 0x20
312#define TRBH 0x21
313#define SR0 0x22
314#define SR1 0x23
315#define SR2 0x24
316#define SR3 0x25
317#define FST 0x26
318#define IE0 0x28
319#define IE1 0x29
320#define IE2 0x2a
321#define FIE 0x2b
322#define CMD 0x2c
323#define MD0 0x2e
324#define MD1 0x2f
325#define MD2 0x30
326#define CTL 0x31
327#define SA0 0x32
328#define SA1 0x33
329#define IDL 0x34
330#define TMC 0x35
331#define RXS 0x36
332#define TXS 0x37
333#define TRC0 0x38
334#define TRC1 0x39
335#define RRC 0x3a
336#define CST0 0x3c
337#define CST1 0x3d
338
339
340#define TCNT 0x60
341#define TCNTL 0x60
342#define TCNTH 0x61
343#define TCONR 0x62
344#define TCONRL 0x62
345#define TCONRH 0x63
346#define TMCS 0x64
347#define TEPR 0x65
348
349
350#define DARL 0x80
351#define DARH 0x81
352#define DARB 0x82
353#define BAR 0x80
354#define BARL 0x80
355#define BARH 0x81
356#define BARB 0x82
357#define SAR 0x84
358#define SARL 0x84
359#define SARH 0x85
360#define SARB 0x86
361#define CPB 0x86
362#define CDA 0x88
363#define CDAL 0x88
364#define CDAH 0x89
365#define EDA 0x8a
366#define EDAL 0x8a
367#define EDAH 0x8b
368#define BFL 0x8c
369#define BFLL 0x8c
370#define BFLH 0x8d
371#define BCR 0x8e
372#define BCRL 0x8e
373#define BCRH 0x8f
374#define DSR 0x90
375#define DMR 0x91
376#define FCT 0x93
377#define DIR 0x94
378#define DCMD 0x95
379
380
381#define TIMER0 0x00
382#define TIMER1 0x08
383#define TIMER2 0x10
384#define TIMER3 0x18
385#define RXDMA 0x00
386#define TXDMA 0x20
387
388
389#define NOOP 0x00
390#define TXRESET 0x01
391#define TXENABLE 0x02
392#define TXDISABLE 0x03
393#define TXCRCINIT 0x04
394#define TXCRCEXCL 0x05
395#define TXEOM 0x06
396#define TXABORT 0x07
397#define MPON 0x08
398#define TXBUFCLR 0x09
399#define RXRESET 0x11
400#define RXENABLE 0x12
401#define RXDISABLE 0x13
402#define RXCRCINIT 0x14
403#define RXREJECT 0x15
404#define SEARCHMP 0x16
405#define RXCRCEXCL 0x17
406#define RXCRCCALC 0x18
407#define CHRESET 0x21
408#define HUNT 0x31
409
410
411#define SWABORT 0x01
412#define FEICLEAR 0x02
413
414
415#define TXINTE BIT7
416#define RXINTE BIT6
417#define TXRDYE BIT1
418#define RXRDYE BIT0
419
420
421#define UDRN BIT7
422#define IDLE BIT6
423#define SYNCD BIT4
424#define FLGD BIT4
425#define CCTS BIT3
426#define CDCD BIT2
427#define BRKD BIT1
428#define ABTD BIT1
429#define GAPD BIT1
430#define BRKE BIT0
431#define IDLD BIT0
432
433
434#define EOM BIT7
435#define PMP BIT6
436#define SHRT BIT6
437#define PE BIT5
438#define ABT BIT5
439#define FRME BIT4
440#define RBIT BIT4
441#define OVRN BIT3
442#define CRCE BIT2
443
444
445
446
447
448static SLMP_INFO *synclinkmp_device_list = NULL;
449static int synclinkmp_adapter_count = -1;
450static int synclinkmp_device_count = 0;
451
452
453
454
455
456
457static bool break_on_load = 0;
458
459
460
461
462
463static int ttymajor = 0;
464
465
466
467
468static int debug_level = 0;
469static int maxframe[MAX_DEVICES] = {0,};
470
471module_param(break_on_load, bool, 0);
472module_param(ttymajor, int, 0);
473module_param(debug_level, int, 0);
474module_param_array(maxframe, int, NULL, 0);
475
476static char *driver_name = "SyncLink MultiPort driver";
477static char *driver_version = "$Revision: 4.38 $";
478
479static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480static void synclinkmp_remove_one(struct pci_dev *dev);
481
482static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, },
485};
486MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488MODULE_LICENSE("GPL");
489
490static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495};
496
497
498static struct tty_driver *serial_driver;
499
500
501#define WAKEUP_CHARS 256
502
503
504
505
506static int open(struct tty_struct *tty, struct file * filp);
507static void close(struct tty_struct *tty, struct file * filp);
508static void hangup(struct tty_struct *tty);
509static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512static int put_char(struct tty_struct *tty, unsigned char ch);
513static void send_xchar(struct tty_struct *tty, char ch);
514static void wait_until_sent(struct tty_struct *tty, int timeout);
515static int write_room(struct tty_struct *tty);
516static void flush_chars(struct tty_struct *tty);
517static void flush_buffer(struct tty_struct *tty);
518static void tx_hold(struct tty_struct *tty);
519static void tx_release(struct tty_struct *tty);
520
521static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522static int chars_in_buffer(struct tty_struct *tty);
523static void throttle(struct tty_struct * tty);
524static void unthrottle(struct tty_struct * tty);
525static int set_break(struct tty_struct *tty, int break_state);
526
527#if SYNCLINK_GENERIC_HDLC
528#define dev_to_port(D) (dev_to_hdlc(D)->priv)
529static void hdlcdev_tx_done(SLMP_INFO *info);
530static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531static int hdlcdev_init(SLMP_INFO *info);
532static void hdlcdev_exit(SLMP_INFO *info);
533#endif
534
535
536
537static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541static int set_txidle(SLMP_INFO *info, int idle_mode);
542static int tx_enable(SLMP_INFO *info, int enable);
543static int tx_abort(SLMP_INFO *info);
544static int rx_enable(SLMP_INFO *info, int enable);
545static int modem_input_wait(SLMP_INFO *info,int arg);
546static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547static int tiocmget(struct tty_struct *tty);
548static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550static int set_break(struct tty_struct *tty, int break_state);
551
552static void add_device(SLMP_INFO *info);
553static void device_init(int adapter_num, struct pci_dev *pdev);
554static int claim_resources(SLMP_INFO *info);
555static void release_resources(SLMP_INFO *info);
556
557static int startup(SLMP_INFO *info);
558static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559static int carrier_raised(struct tty_port *port);
560static void shutdown(SLMP_INFO *info);
561static void program_hw(SLMP_INFO *info);
562static void change_params(SLMP_INFO *info);
563
564static bool init_adapter(SLMP_INFO *info);
565static bool register_test(SLMP_INFO *info);
566static bool irq_test(SLMP_INFO *info);
567static bool loopback_test(SLMP_INFO *info);
568static int adapter_test(SLMP_INFO *info);
569static bool memory_test(SLMP_INFO *info);
570
571static void reset_adapter(SLMP_INFO *info);
572static void reset_port(SLMP_INFO *info);
573static void async_mode(SLMP_INFO *info);
574static void hdlc_mode(SLMP_INFO *info);
575
576static void rx_stop(SLMP_INFO *info);
577static void rx_start(SLMP_INFO *info);
578static void rx_reset_buffers(SLMP_INFO *info);
579static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580static bool rx_get_frame(SLMP_INFO *info);
581
582static void tx_start(SLMP_INFO *info);
583static void tx_stop(SLMP_INFO *info);
584static void tx_load_fifo(SLMP_INFO *info);
585static void tx_set_idle(SLMP_INFO *info);
586static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588static void get_signals(SLMP_INFO *info);
589static void set_signals(SLMP_INFO *info);
590static void enable_loopback(SLMP_INFO *info, int enable);
591static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593static int bh_action(SLMP_INFO *info);
594static void bh_handler(struct work_struct *work);
595static void bh_receive(SLMP_INFO *info);
596static void bh_transmit(SLMP_INFO *info);
597static void bh_status(SLMP_INFO *info);
598static void isr_timer(SLMP_INFO *info);
599static void isr_rxint(SLMP_INFO *info);
600static void isr_rxrdy(SLMP_INFO *info);
601static void isr_txint(SLMP_INFO *info);
602static void isr_txrdy(SLMP_INFO *info);
603static void isr_rxdmaok(SLMP_INFO *info);
604static void isr_rxdmaerror(SLMP_INFO *info);
605static void isr_txdmaok(SLMP_INFO *info);
606static void isr_txdmaerror(SLMP_INFO *info);
607static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609static int alloc_dma_bufs(SLMP_INFO *info);
610static void free_dma_bufs(SLMP_INFO *info);
611static int alloc_buf_list(SLMP_INFO *info);
612static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613static int alloc_tmp_rx_buf(SLMP_INFO *info);
614static void free_tmp_rx_buf(SLMP_INFO *info);
615
616static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618static void tx_timeout(unsigned long context);
619static void status_timeout(unsigned long context);
620
621static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625static unsigned char read_status_reg(SLMP_INFO * info);
626static void write_control_reg(SLMP_INFO * info);
627
628
629static unsigned char rx_active_fifo_level = 16;
630static unsigned char tx_active_fifo_level = 16;
631static unsigned char tx_negate_fifo_level = 32;
632
633static u32 misc_ctrl_value = 0x007e4040;
634static u32 lcr1_brdr_value = 0x00800028;
635
636static u32 read_ahead_count = 8;
637
638
639
640
641
642
643
644
645
646
647
648
649static unsigned char dma_priority = 0x04;
650
651
652
653static u32 sca_pci_load_interval = 64;
654
655
656
657
658
659
660
661static void* synclinkmp_get_text_ptr(void);
662static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666{
667#ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681#else
682 if (!info)
683 return 1;
684#endif
685 return 0;
686}
687
688
689
690
691
692
693
694
695
696
697static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699{
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709}
710
711
712
713static int install(struct tty_driver *driver, struct tty_struct *tty)
714{
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739}
740
741
742
743static int open(struct tty_struct *tty, struct file *filp)
744{
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755
756 if (info->port.flags & ASYNC_CLOSING){
757 wait_event_interruptible_tty(tty, info->port.close_wait,
758 !(info->port.flags & ASYNC_CLOSING));
759 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
760 -EAGAIN : -ERESTARTSYS);
761 goto cleanup;
762 }
763
764 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
765
766 spin_lock_irqsave(&info->netlock, flags);
767 if (info->netcount) {
768 retval = -EBUSY;
769 spin_unlock_irqrestore(&info->netlock, flags);
770 goto cleanup;
771 }
772 info->port.count++;
773 spin_unlock_irqrestore(&info->netlock, flags);
774
775 if (info->port.count == 1) {
776
777 retval = startup(info);
778 if (retval < 0)
779 goto cleanup;
780 }
781
782 retval = block_til_ready(tty, filp, info);
783 if (retval) {
784 if (debug_level >= DEBUG_LEVEL_INFO)
785 printk("%s(%d):%s block_til_ready() returned %d\n",
786 __FILE__,__LINE__, info->device_name, retval);
787 goto cleanup;
788 }
789
790 if (debug_level >= DEBUG_LEVEL_INFO)
791 printk("%s(%d):%s open() success\n",
792 __FILE__,__LINE__, info->device_name);
793 retval = 0;
794
795cleanup:
796 if (retval) {
797 if (tty->count == 1)
798 info->port.tty = NULL;
799 if(info->port.count)
800 info->port.count--;
801 }
802
803 return retval;
804}
805
806
807
808
809static void close(struct tty_struct *tty, struct file *filp)
810{
811 SLMP_INFO * info = tty->driver_data;
812
813 if (sanity_check(info, tty->name, "close"))
814 return;
815
816 if (debug_level >= DEBUG_LEVEL_INFO)
817 printk("%s(%d):%s close() entry, count=%d\n",
818 __FILE__,__LINE__, info->device_name, info->port.count);
819
820 if (tty_port_close_start(&info->port, tty, filp) == 0)
821 goto cleanup;
822
823 mutex_lock(&info->port.mutex);
824 if (info->port.flags & ASYNC_INITIALIZED)
825 wait_until_sent(tty, info->timeout);
826
827 flush_buffer(tty);
828 tty_ldisc_flush(tty);
829 shutdown(info);
830 mutex_unlock(&info->port.mutex);
831
832 tty_port_close_end(&info->port, tty);
833 info->port.tty = NULL;
834cleanup:
835 if (debug_level >= DEBUG_LEVEL_INFO)
836 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
837 tty->driver->name, info->port.count);
838}
839
840
841
842
843static void hangup(struct tty_struct *tty)
844{
845 SLMP_INFO *info = tty->driver_data;
846 unsigned long flags;
847
848 if (debug_level >= DEBUG_LEVEL_INFO)
849 printk("%s(%d):%s hangup()\n",
850 __FILE__,__LINE__, info->device_name );
851
852 if (sanity_check(info, tty->name, "hangup"))
853 return;
854
855 mutex_lock(&info->port.mutex);
856 flush_buffer(tty);
857 shutdown(info);
858
859 spin_lock_irqsave(&info->port.lock, flags);
860 info->port.count = 0;
861 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
862 info->port.tty = NULL;
863 spin_unlock_irqrestore(&info->port.lock, flags);
864 mutex_unlock(&info->port.mutex);
865
866 wake_up_interruptible(&info->port.open_wait);
867}
868
869
870
871static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
872{
873 SLMP_INFO *info = tty->driver_data;
874 unsigned long flags;
875
876 if (debug_level >= DEBUG_LEVEL_INFO)
877 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
878 tty->driver->name );
879
880 change_params(info);
881
882
883 if (old_termios->c_cflag & CBAUD &&
884 !(tty->termios.c_cflag & CBAUD)) {
885 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891
892 if (!(old_termios->c_cflag & CBAUD) &&
893 tty->termios.c_cflag & CBAUD) {
894 info->serial_signals |= SerialSignal_DTR;
895 if (!(tty->termios.c_cflag & CRTSCTS) ||
896 !test_bit(TTY_THROTTLED, &tty->flags)) {
897 info->serial_signals |= SerialSignal_RTS;
898 }
899 spin_lock_irqsave(&info->lock,flags);
900 set_signals(info);
901 spin_unlock_irqrestore(&info->lock,flags);
902 }
903
904
905 if (old_termios->c_cflag & CRTSCTS &&
906 !(tty->termios.c_cflag & CRTSCTS)) {
907 tty->hw_stopped = 0;
908 tx_release(tty);
909 }
910}
911
912
913
914
915
916
917
918
919
920
921
922static int write(struct tty_struct *tty,
923 const unsigned char *buf, int count)
924{
925 int c, ret = 0;
926 SLMP_INFO *info = tty->driver_data;
927 unsigned long flags;
928
929 if (debug_level >= DEBUG_LEVEL_INFO)
930 printk("%s(%d):%s write() count=%d\n",
931 __FILE__,__LINE__,info->device_name,count);
932
933 if (sanity_check(info, tty->name, "write"))
934 goto cleanup;
935
936 if (!info->tx_buf)
937 goto cleanup;
938
939 if (info->params.mode == MGSL_MODE_HDLC) {
940 if (count > info->max_frame_size) {
941 ret = -EIO;
942 goto cleanup;
943 }
944 if (info->tx_active)
945 goto cleanup;
946 if (info->tx_count) {
947
948
949 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
950 goto start;
951 }
952 ret = info->tx_count = count;
953 tx_load_dma_buffer(info, buf, count);
954 goto start;
955 }
956
957 for (;;) {
958 c = min_t(int, count,
959 min(info->max_frame_size - info->tx_count - 1,
960 info->max_frame_size - info->tx_put));
961 if (c <= 0)
962 break;
963
964 memcpy(info->tx_buf + info->tx_put, buf, c);
965
966 spin_lock_irqsave(&info->lock,flags);
967 info->tx_put += c;
968 if (info->tx_put >= info->max_frame_size)
969 info->tx_put -= info->max_frame_size;
970 info->tx_count += c;
971 spin_unlock_irqrestore(&info->lock,flags);
972
973 buf += c;
974 count -= c;
975 ret += c;
976 }
977
978 if (info->params.mode == MGSL_MODE_HDLC) {
979 if (count) {
980 ret = info->tx_count = 0;
981 goto cleanup;
982 }
983 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
984 }
985start:
986 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
987 spin_lock_irqsave(&info->lock,flags);
988 if (!info->tx_active)
989 tx_start(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991 }
992
993cleanup:
994 if (debug_level >= DEBUG_LEVEL_INFO)
995 printk( "%s(%d):%s write() returning=%d\n",
996 __FILE__,__LINE__,info->device_name,ret);
997 return ret;
998}
999
1000
1001
1002static int put_char(struct tty_struct *tty, unsigned char ch)
1003{
1004 SLMP_INFO *info = tty->driver_data;
1005 unsigned long flags;
1006 int ret = 0;
1007
1008 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1009 printk( "%s(%d):%s put_char(%d)\n",
1010 __FILE__,__LINE__,info->device_name,ch);
1011 }
1012
1013 if (sanity_check(info, tty->name, "put_char"))
1014 return 0;
1015
1016 if (!info->tx_buf)
1017 return 0;
1018
1019 spin_lock_irqsave(&info->lock,flags);
1020
1021 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1022 !info->tx_active ) {
1023
1024 if (info->tx_count < info->max_frame_size - 1) {
1025 info->tx_buf[info->tx_put++] = ch;
1026 if (info->tx_put >= info->max_frame_size)
1027 info->tx_put -= info->max_frame_size;
1028 info->tx_count++;
1029 ret = 1;
1030 }
1031 }
1032
1033 spin_unlock_irqrestore(&info->lock,flags);
1034 return ret;
1035}
1036
1037
1038
1039static void send_xchar(struct tty_struct *tty, char ch)
1040{
1041 SLMP_INFO *info = tty->driver_data;
1042 unsigned long flags;
1043
1044 if (debug_level >= DEBUG_LEVEL_INFO)
1045 printk("%s(%d):%s send_xchar(%d)\n",
1046 __FILE__,__LINE__, info->device_name, ch );
1047
1048 if (sanity_check(info, tty->name, "send_xchar"))
1049 return;
1050
1051 info->x_char = ch;
1052 if (ch) {
1053
1054 spin_lock_irqsave(&info->lock,flags);
1055 if (!info->tx_enabled)
1056 tx_start(info);
1057 spin_unlock_irqrestore(&info->lock,flags);
1058 }
1059}
1060
1061
1062
1063static void wait_until_sent(struct tty_struct *tty, int timeout)
1064{
1065 SLMP_INFO * info = tty->driver_data;
1066 unsigned long orig_jiffies, char_time;
1067
1068 if (!info )
1069 return;
1070
1071 if (debug_level >= DEBUG_LEVEL_INFO)
1072 printk("%s(%d):%s wait_until_sent() entry\n",
1073 __FILE__,__LINE__, info->device_name );
1074
1075 if (sanity_check(info, tty->name, "wait_until_sent"))
1076 return;
1077
1078 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1079 goto exit;
1080
1081 orig_jiffies = jiffies;
1082
1083
1084
1085
1086
1087
1088
1089 if ( info->params.data_rate ) {
1090 char_time = info->timeout/(32 * 5);
1091 if (!char_time)
1092 char_time++;
1093 } else
1094 char_time = 1;
1095
1096 if (timeout)
1097 char_time = min_t(unsigned long, char_time, timeout);
1098
1099 if ( info->params.mode == MGSL_MODE_HDLC ) {
1100 while (info->tx_active) {
1101 msleep_interruptible(jiffies_to_msecs(char_time));
1102 if (signal_pending(current))
1103 break;
1104 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1105 break;
1106 }
1107 } else {
1108
1109
1110
1111
1112 while ( info->tx_active && info->tx_enabled) {
1113 msleep_interruptible(jiffies_to_msecs(char_time));
1114 if (signal_pending(current))
1115 break;
1116 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1117 break;
1118 }
1119 }
1120
1121exit:
1122 if (debug_level >= DEBUG_LEVEL_INFO)
1123 printk("%s(%d):%s wait_until_sent() exit\n",
1124 __FILE__,__LINE__, info->device_name );
1125}
1126
1127
1128
1129static int write_room(struct tty_struct *tty)
1130{
1131 SLMP_INFO *info = tty->driver_data;
1132 int ret;
1133
1134 if (sanity_check(info, tty->name, "write_room"))
1135 return 0;
1136
1137 if (info->params.mode == MGSL_MODE_HDLC) {
1138 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1139 } else {
1140 ret = info->max_frame_size - info->tx_count - 1;
1141 if (ret < 0)
1142 ret = 0;
1143 }
1144
1145 if (debug_level >= DEBUG_LEVEL_INFO)
1146 printk("%s(%d):%s write_room()=%d\n",
1147 __FILE__, __LINE__, info->device_name, ret);
1148
1149 return ret;
1150}
1151
1152
1153
1154static void flush_chars(struct tty_struct *tty)
1155{
1156 SLMP_INFO *info = tty->driver_data;
1157 unsigned long flags;
1158
1159 if ( debug_level >= DEBUG_LEVEL_INFO )
1160 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1161 __FILE__,__LINE__,info->device_name,info->tx_count);
1162
1163 if (sanity_check(info, tty->name, "flush_chars"))
1164 return;
1165
1166 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1167 !info->tx_buf)
1168 return;
1169
1170 if ( debug_level >= DEBUG_LEVEL_INFO )
1171 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1172 __FILE__,__LINE__,info->device_name );
1173
1174 spin_lock_irqsave(&info->lock,flags);
1175
1176 if (!info->tx_active) {
1177 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1178 info->tx_count ) {
1179
1180
1181
1182 tx_load_dma_buffer(info,
1183 info->tx_buf,info->tx_count);
1184 }
1185 tx_start(info);
1186 }
1187
1188 spin_unlock_irqrestore(&info->lock,flags);
1189}
1190
1191
1192
1193static void flush_buffer(struct tty_struct *tty)
1194{
1195 SLMP_INFO *info = tty->driver_data;
1196 unsigned long flags;
1197
1198 if (debug_level >= DEBUG_LEVEL_INFO)
1199 printk("%s(%d):%s flush_buffer() entry\n",
1200 __FILE__,__LINE__, info->device_name );
1201
1202 if (sanity_check(info, tty->name, "flush_buffer"))
1203 return;
1204
1205 spin_lock_irqsave(&info->lock,flags);
1206 info->tx_count = info->tx_put = info->tx_get = 0;
1207 del_timer(&info->tx_timer);
1208 spin_unlock_irqrestore(&info->lock,flags);
1209
1210 tty_wakeup(tty);
1211}
1212
1213
1214
1215static void tx_hold(struct tty_struct *tty)
1216{
1217 SLMP_INFO *info = tty->driver_data;
1218 unsigned long flags;
1219
1220 if (sanity_check(info, tty->name, "tx_hold"))
1221 return;
1222
1223 if ( debug_level >= DEBUG_LEVEL_INFO )
1224 printk("%s(%d):%s tx_hold()\n",
1225 __FILE__,__LINE__,info->device_name);
1226
1227 spin_lock_irqsave(&info->lock,flags);
1228 if (info->tx_enabled)
1229 tx_stop(info);
1230 spin_unlock_irqrestore(&info->lock,flags);
1231}
1232
1233
1234
1235static void tx_release(struct tty_struct *tty)
1236{
1237 SLMP_INFO *info = tty->driver_data;
1238 unsigned long flags;
1239
1240 if (sanity_check(info, tty->name, "tx_release"))
1241 return;
1242
1243 if ( debug_level >= DEBUG_LEVEL_INFO )
1244 printk("%s(%d):%s tx_release()\n",
1245 __FILE__,__LINE__,info->device_name);
1246
1247 spin_lock_irqsave(&info->lock,flags);
1248 if (!info->tx_enabled)
1249 tx_start(info);
1250 spin_unlock_irqrestore(&info->lock,flags);
1251}
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263static int ioctl(struct tty_struct *tty,
1264 unsigned int cmd, unsigned long arg)
1265{
1266 SLMP_INFO *info = tty->driver_data;
1267 void __user *argp = (void __user *)arg;
1268
1269 if (debug_level >= DEBUG_LEVEL_INFO)
1270 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1271 info->device_name, cmd );
1272
1273 if (sanity_check(info, tty->name, "ioctl"))
1274 return -ENODEV;
1275
1276 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1277 (cmd != TIOCMIWAIT)) {
1278 if (tty->flags & (1 << TTY_IO_ERROR))
1279 return -EIO;
1280 }
1281
1282 switch (cmd) {
1283 case MGSL_IOCGPARAMS:
1284 return get_params(info, argp);
1285 case MGSL_IOCSPARAMS:
1286 return set_params(info, argp);
1287 case MGSL_IOCGTXIDLE:
1288 return get_txidle(info, argp);
1289 case MGSL_IOCSTXIDLE:
1290 return set_txidle(info, (int)arg);
1291 case MGSL_IOCTXENABLE:
1292 return tx_enable(info, (int)arg);
1293 case MGSL_IOCRXENABLE:
1294 return rx_enable(info, (int)arg);
1295 case MGSL_IOCTXABORT:
1296 return tx_abort(info);
1297 case MGSL_IOCGSTATS:
1298 return get_stats(info, argp);
1299 case MGSL_IOCWAITEVENT:
1300 return wait_mgsl_event(info, argp);
1301 case MGSL_IOCLOOPTXDONE:
1302 return 0;
1303
1304
1305
1306 case TIOCMIWAIT:
1307 return modem_input_wait(info,(int)arg);
1308
1309
1310
1311
1312
1313
1314
1315 default:
1316 return -ENOIOCTLCMD;
1317 }
1318 return 0;
1319}
1320
1321static int get_icount(struct tty_struct *tty,
1322 struct serial_icounter_struct *icount)
1323{
1324 SLMP_INFO *info = tty->driver_data;
1325 struct mgsl_icount cnow;
1326 unsigned long flags;
1327
1328 spin_lock_irqsave(&info->lock,flags);
1329 cnow = info->icount;
1330 spin_unlock_irqrestore(&info->lock,flags);
1331
1332 icount->cts = cnow.cts;
1333 icount->dsr = cnow.dsr;
1334 icount->rng = cnow.rng;
1335 icount->dcd = cnow.dcd;
1336 icount->rx = cnow.rx;
1337 icount->tx = cnow.tx;
1338 icount->frame = cnow.frame;
1339 icount->overrun = cnow.overrun;
1340 icount->parity = cnow.parity;
1341 icount->brk = cnow.brk;
1342 icount->buf_overrun = cnow.buf_overrun;
1343
1344 return 0;
1345}
1346
1347
1348
1349
1350
1351static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1352{
1353 char stat_buf[30];
1354 unsigned long flags;
1355
1356 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1357 "\tIRQ=%d MaxFrameSize=%u\n",
1358 info->device_name,
1359 info->phys_sca_base,
1360 info->phys_memory_base,
1361 info->phys_statctrl_base,
1362 info->phys_lcr_base,
1363 info->irq_level,
1364 info->max_frame_size );
1365
1366
1367 spin_lock_irqsave(&info->lock,flags);
1368 get_signals(info);
1369 spin_unlock_irqrestore(&info->lock,flags);
1370
1371 stat_buf[0] = 0;
1372 stat_buf[1] = 0;
1373 if (info->serial_signals & SerialSignal_RTS)
1374 strcat(stat_buf, "|RTS");
1375 if (info->serial_signals & SerialSignal_CTS)
1376 strcat(stat_buf, "|CTS");
1377 if (info->serial_signals & SerialSignal_DTR)
1378 strcat(stat_buf, "|DTR");
1379 if (info->serial_signals & SerialSignal_DSR)
1380 strcat(stat_buf, "|DSR");
1381 if (info->serial_signals & SerialSignal_DCD)
1382 strcat(stat_buf, "|CD");
1383 if (info->serial_signals & SerialSignal_RI)
1384 strcat(stat_buf, "|RI");
1385
1386 if (info->params.mode == MGSL_MODE_HDLC) {
1387 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1388 info->icount.txok, info->icount.rxok);
1389 if (info->icount.txunder)
1390 seq_printf(m, " txunder:%d", info->icount.txunder);
1391 if (info->icount.txabort)
1392 seq_printf(m, " txabort:%d", info->icount.txabort);
1393 if (info->icount.rxshort)
1394 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1395 if (info->icount.rxlong)
1396 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1397 if (info->icount.rxover)
1398 seq_printf(m, " rxover:%d", info->icount.rxover);
1399 if (info->icount.rxcrc)
1400 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1401 } else {
1402 seq_printf(m, "\tASYNC tx:%d rx:%d",
1403 info->icount.tx, info->icount.rx);
1404 if (info->icount.frame)
1405 seq_printf(m, " fe:%d", info->icount.frame);
1406 if (info->icount.parity)
1407 seq_printf(m, " pe:%d", info->icount.parity);
1408 if (info->icount.brk)
1409 seq_printf(m, " brk:%d", info->icount.brk);
1410 if (info->icount.overrun)
1411 seq_printf(m, " oe:%d", info->icount.overrun);
1412 }
1413
1414
1415 seq_printf(m, " %s\n", stat_buf+1);
1416
1417 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1418 info->tx_active,info->bh_requested,info->bh_running,
1419 info->pending_bh);
1420}
1421
1422
1423
1424static int synclinkmp_proc_show(struct seq_file *m, void *v)
1425{
1426 SLMP_INFO *info;
1427
1428 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1429
1430 info = synclinkmp_device_list;
1431 while( info ) {
1432 line_info(m, info);
1433 info = info->next_device;
1434 }
1435 return 0;
1436}
1437
1438static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1439{
1440 return single_open(file, synclinkmp_proc_show, NULL);
1441}
1442
1443static const struct file_operations synclinkmp_proc_fops = {
1444 .owner = THIS_MODULE,
1445 .open = synclinkmp_proc_open,
1446 .read = seq_read,
1447 .llseek = seq_lseek,
1448 .release = single_release,
1449};
1450
1451
1452
1453static int chars_in_buffer(struct tty_struct *tty)
1454{
1455 SLMP_INFO *info = tty->driver_data;
1456
1457 if (sanity_check(info, tty->name, "chars_in_buffer"))
1458 return 0;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s chars_in_buffer()=%d\n",
1462 __FILE__, __LINE__, info->device_name, info->tx_count);
1463
1464 return info->tx_count;
1465}
1466
1467
1468
1469static void throttle(struct tty_struct * tty)
1470{
1471 SLMP_INFO *info = tty->driver_data;
1472 unsigned long flags;
1473
1474 if (debug_level >= DEBUG_LEVEL_INFO)
1475 printk("%s(%d):%s throttle() entry\n",
1476 __FILE__,__LINE__, info->device_name );
1477
1478 if (sanity_check(info, tty->name, "throttle"))
1479 return;
1480
1481 if (I_IXOFF(tty))
1482 send_xchar(tty, STOP_CHAR(tty));
1483
1484 if (tty->termios.c_cflag & CRTSCTS) {
1485 spin_lock_irqsave(&info->lock,flags);
1486 info->serial_signals &= ~SerialSignal_RTS;
1487 set_signals(info);
1488 spin_unlock_irqrestore(&info->lock,flags);
1489 }
1490}
1491
1492
1493
1494static void unthrottle(struct tty_struct * tty)
1495{
1496 SLMP_INFO *info = tty->driver_data;
1497 unsigned long flags;
1498
1499 if (debug_level >= DEBUG_LEVEL_INFO)
1500 printk("%s(%d):%s unthrottle() entry\n",
1501 __FILE__,__LINE__, info->device_name );
1502
1503 if (sanity_check(info, tty->name, "unthrottle"))
1504 return;
1505
1506 if (I_IXOFF(tty)) {
1507 if (info->x_char)
1508 info->x_char = 0;
1509 else
1510 send_xchar(tty, START_CHAR(tty));
1511 }
1512
1513 if (tty->termios.c_cflag & CRTSCTS) {
1514 spin_lock_irqsave(&info->lock,flags);
1515 info->serial_signals |= SerialSignal_RTS;
1516 set_signals(info);
1517 spin_unlock_irqrestore(&info->lock,flags);
1518 }
1519}
1520
1521
1522
1523
1524static int set_break(struct tty_struct *tty, int break_state)
1525{
1526 unsigned char RegValue;
1527 SLMP_INFO * info = tty->driver_data;
1528 unsigned long flags;
1529
1530 if (debug_level >= DEBUG_LEVEL_INFO)
1531 printk("%s(%d):%s set_break(%d)\n",
1532 __FILE__,__LINE__, info->device_name, break_state);
1533
1534 if (sanity_check(info, tty->name, "set_break"))
1535 return -EINVAL;
1536
1537 spin_lock_irqsave(&info->lock,flags);
1538 RegValue = read_reg(info, CTL);
1539 if (break_state == -1)
1540 RegValue |= BIT3;
1541 else
1542 RegValue &= ~BIT3;
1543 write_reg(info, CTL, RegValue);
1544 spin_unlock_irqrestore(&info->lock,flags);
1545 return 0;
1546}
1547
1548#if SYNCLINK_GENERIC_HDLC
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1561 unsigned short parity)
1562{
1563 SLMP_INFO *info = dev_to_port(dev);
1564 unsigned char new_encoding;
1565 unsigned short new_crctype;
1566
1567
1568 if (info->port.count)
1569 return -EBUSY;
1570
1571 switch (encoding)
1572 {
1573 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1574 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1575 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1576 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1577 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1578 default: return -EINVAL;
1579 }
1580
1581 switch (parity)
1582 {
1583 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1584 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1585 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1586 default: return -EINVAL;
1587 }
1588
1589 info->params.encoding = new_encoding;
1590 info->params.crc_type = new_crctype;
1591
1592
1593 if (info->netcount)
1594 program_hw(info);
1595
1596 return 0;
1597}
1598
1599
1600
1601
1602
1603
1604
1605static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1606 struct net_device *dev)
1607{
1608 SLMP_INFO *info = dev_to_port(dev);
1609 unsigned long flags;
1610
1611 if (debug_level >= DEBUG_LEVEL_INFO)
1612 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1613
1614
1615 netif_stop_queue(dev);
1616
1617
1618 info->tx_count = skb->len;
1619 tx_load_dma_buffer(info, skb->data, skb->len);
1620
1621
1622 dev->stats.tx_packets++;
1623 dev->stats.tx_bytes += skb->len;
1624
1625
1626 dev_kfree_skb(skb);
1627
1628
1629 dev->trans_start = jiffies;
1630
1631
1632 spin_lock_irqsave(&info->lock,flags);
1633 if (!info->tx_active)
1634 tx_start(info);
1635 spin_unlock_irqrestore(&info->lock,flags);
1636
1637 return NETDEV_TX_OK;
1638}
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648static int hdlcdev_open(struct net_device *dev)
1649{
1650 SLMP_INFO *info = dev_to_port(dev);
1651 int rc;
1652 unsigned long flags;
1653
1654 if (debug_level >= DEBUG_LEVEL_INFO)
1655 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1656
1657
1658 if ((rc = hdlc_open(dev)))
1659 return rc;
1660
1661
1662 spin_lock_irqsave(&info->netlock, flags);
1663 if (info->port.count != 0 || info->netcount != 0) {
1664 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1665 spin_unlock_irqrestore(&info->netlock, flags);
1666 return -EBUSY;
1667 }
1668 info->netcount=1;
1669 spin_unlock_irqrestore(&info->netlock, flags);
1670
1671
1672 if ((rc = startup(info)) != 0) {
1673 spin_lock_irqsave(&info->netlock, flags);
1674 info->netcount=0;
1675 spin_unlock_irqrestore(&info->netlock, flags);
1676 return rc;
1677 }
1678
1679
1680 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1681 program_hw(info);
1682
1683
1684 dev->trans_start = jiffies;
1685 netif_start_queue(dev);
1686
1687
1688 spin_lock_irqsave(&info->lock, flags);
1689 get_signals(info);
1690 spin_unlock_irqrestore(&info->lock, flags);
1691 if (info->serial_signals & SerialSignal_DCD)
1692 netif_carrier_on(dev);
1693 else
1694 netif_carrier_off(dev);
1695 return 0;
1696}
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706static int hdlcdev_close(struct net_device *dev)
1707{
1708 SLMP_INFO *info = dev_to_port(dev);
1709 unsigned long flags;
1710
1711 if (debug_level >= DEBUG_LEVEL_INFO)
1712 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1713
1714 netif_stop_queue(dev);
1715
1716
1717 shutdown(info);
1718
1719 hdlc_close(dev);
1720
1721 spin_lock_irqsave(&info->netlock, flags);
1722 info->netcount=0;
1723 spin_unlock_irqrestore(&info->netlock, flags);
1724
1725 return 0;
1726}
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1738{
1739 const size_t size = sizeof(sync_serial_settings);
1740 sync_serial_settings new_line;
1741 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1742 SLMP_INFO *info = dev_to_port(dev);
1743 unsigned int flags;
1744
1745 if (debug_level >= DEBUG_LEVEL_INFO)
1746 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1747
1748
1749 if (info->port.count)
1750 return -EBUSY;
1751
1752 if (cmd != SIOCWANDEV)
1753 return hdlc_ioctl(dev, ifr, cmd);
1754
1755 switch(ifr->ifr_settings.type) {
1756 case IF_GET_IFACE:
1757
1758 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1759 if (ifr->ifr_settings.size < size) {
1760 ifr->ifr_settings.size = size;
1761 return -ENOBUFS;
1762 }
1763
1764 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1765 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1766 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1767 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1768
1769 memset(&new_line, 0, sizeof(new_line));
1770 switch (flags){
1771 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1772 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1774 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1775 default: new_line.clock_type = CLOCK_DEFAULT;
1776 }
1777
1778 new_line.clock_rate = info->params.clock_speed;
1779 new_line.loopback = info->params.loopback ? 1:0;
1780
1781 if (copy_to_user(line, &new_line, size))
1782 return -EFAULT;
1783 return 0;
1784
1785 case IF_IFACE_SYNC_SERIAL:
1786
1787 if(!capable(CAP_NET_ADMIN))
1788 return -EPERM;
1789 if (copy_from_user(&new_line, line, size))
1790 return -EFAULT;
1791
1792 switch (new_line.clock_type)
1793 {
1794 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1795 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1796 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1797 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1798 case CLOCK_DEFAULT: flags = info->params.flags &
1799 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1800 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1801 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1802 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1803 default: return -EINVAL;
1804 }
1805
1806 if (new_line.loopback != 0 && new_line.loopback != 1)
1807 return -EINVAL;
1808
1809 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1810 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1811 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1812 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1813 info->params.flags |= flags;
1814
1815 info->params.loopback = new_line.loopback;
1816
1817 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1818 info->params.clock_speed = new_line.clock_rate;
1819 else
1820 info->params.clock_speed = 0;
1821
1822
1823 if (info->netcount)
1824 program_hw(info);
1825 return 0;
1826
1827 default:
1828 return hdlc_ioctl(dev, ifr, cmd);
1829 }
1830}
1831
1832
1833
1834
1835
1836
1837static void hdlcdev_tx_timeout(struct net_device *dev)
1838{
1839 SLMP_INFO *info = dev_to_port(dev);
1840 unsigned long flags;
1841
1842 if (debug_level >= DEBUG_LEVEL_INFO)
1843 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1844
1845 dev->stats.tx_errors++;
1846 dev->stats.tx_aborted_errors++;
1847
1848 spin_lock_irqsave(&info->lock,flags);
1849 tx_stop(info);
1850 spin_unlock_irqrestore(&info->lock,flags);
1851
1852 netif_wake_queue(dev);
1853}
1854
1855
1856
1857
1858
1859
1860
1861static void hdlcdev_tx_done(SLMP_INFO *info)
1862{
1863 if (netif_queue_stopped(info->netdev))
1864 netif_wake_queue(info->netdev);
1865}
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1876{
1877 struct sk_buff *skb = dev_alloc_skb(size);
1878 struct net_device *dev = info->netdev;
1879
1880 if (debug_level >= DEBUG_LEVEL_INFO)
1881 printk("hdlcdev_rx(%s)\n",dev->name);
1882
1883 if (skb == NULL) {
1884 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1885 dev->name);
1886 dev->stats.rx_dropped++;
1887 return;
1888 }
1889
1890 memcpy(skb_put(skb, size), buf, size);
1891
1892 skb->protocol = hdlc_type_trans(skb, dev);
1893
1894 dev->stats.rx_packets++;
1895 dev->stats.rx_bytes += size;
1896
1897 netif_rx(skb);
1898}
1899
1900static const struct net_device_ops hdlcdev_ops = {
1901 .ndo_open = hdlcdev_open,
1902 .ndo_stop = hdlcdev_close,
1903 .ndo_change_mtu = hdlc_change_mtu,
1904 .ndo_start_xmit = hdlc_start_xmit,
1905 .ndo_do_ioctl = hdlcdev_ioctl,
1906 .ndo_tx_timeout = hdlcdev_tx_timeout,
1907};
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917static int hdlcdev_init(SLMP_INFO *info)
1918{
1919 int rc;
1920 struct net_device *dev;
1921 hdlc_device *hdlc;
1922
1923
1924
1925 if (!(dev = alloc_hdlcdev(info))) {
1926 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1927 return -ENOMEM;
1928 }
1929
1930
1931 dev->mem_start = info->phys_sca_base;
1932 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1933 dev->irq = info->irq_level;
1934
1935
1936 dev->netdev_ops = &hdlcdev_ops;
1937 dev->watchdog_timeo = 10 * HZ;
1938 dev->tx_queue_len = 50;
1939
1940
1941 hdlc = dev_to_hdlc(dev);
1942 hdlc->attach = hdlcdev_attach;
1943 hdlc->xmit = hdlcdev_xmit;
1944
1945
1946 if ((rc = register_hdlc_device(dev))) {
1947 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1948 free_netdev(dev);
1949 return rc;
1950 }
1951
1952 info->netdev = dev;
1953 return 0;
1954}
1955
1956
1957
1958
1959
1960
1961
1962static void hdlcdev_exit(SLMP_INFO *info)
1963{
1964 unregister_hdlc_device(info->netdev);
1965 free_netdev(info->netdev);
1966 info->netdev = NULL;
1967}
1968
1969#endif
1970
1971
1972
1973
1974
1975static int bh_action(SLMP_INFO *info)
1976{
1977 unsigned long flags;
1978 int rc = 0;
1979
1980 spin_lock_irqsave(&info->lock,flags);
1981
1982 if (info->pending_bh & BH_RECEIVE) {
1983 info->pending_bh &= ~BH_RECEIVE;
1984 rc = BH_RECEIVE;
1985 } else if (info->pending_bh & BH_TRANSMIT) {
1986 info->pending_bh &= ~BH_TRANSMIT;
1987 rc = BH_TRANSMIT;
1988 } else if (info->pending_bh & BH_STATUS) {
1989 info->pending_bh &= ~BH_STATUS;
1990 rc = BH_STATUS;
1991 }
1992
1993 if (!rc) {
1994
1995 info->bh_running = false;
1996 info->bh_requested = false;
1997 }
1998
1999 spin_unlock_irqrestore(&info->lock,flags);
2000
2001 return rc;
2002}
2003
2004
2005
2006static void bh_handler(struct work_struct *work)
2007{
2008 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2009 int action;
2010
2011 if ( debug_level >= DEBUG_LEVEL_BH )
2012 printk( "%s(%d):%s bh_handler() entry\n",
2013 __FILE__,__LINE__,info->device_name);
2014
2015 info->bh_running = true;
2016
2017 while((action = bh_action(info)) != 0) {
2018
2019
2020 if ( debug_level >= DEBUG_LEVEL_BH )
2021 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2022 __FILE__,__LINE__,info->device_name, action);
2023
2024 switch (action) {
2025
2026 case BH_RECEIVE:
2027 bh_receive(info);
2028 break;
2029 case BH_TRANSMIT:
2030 bh_transmit(info);
2031 break;
2032 case BH_STATUS:
2033 bh_status(info);
2034 break;
2035 default:
2036
2037 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2038 __FILE__,__LINE__,info->device_name,action);
2039 break;
2040 }
2041 }
2042
2043 if ( debug_level >= DEBUG_LEVEL_BH )
2044 printk( "%s(%d):%s bh_handler() exit\n",
2045 __FILE__,__LINE__,info->device_name);
2046}
2047
2048static void bh_receive(SLMP_INFO *info)
2049{
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_receive()\n",
2052 __FILE__,__LINE__,info->device_name);
2053
2054 while( rx_get_frame(info) );
2055}
2056
2057static void bh_transmit(SLMP_INFO *info)
2058{
2059 struct tty_struct *tty = info->port.tty;
2060
2061 if ( debug_level >= DEBUG_LEVEL_BH )
2062 printk( "%s(%d):%s bh_transmit() entry\n",
2063 __FILE__,__LINE__,info->device_name);
2064
2065 if (tty)
2066 tty_wakeup(tty);
2067}
2068
2069static void bh_status(SLMP_INFO *info)
2070{
2071 if ( debug_level >= DEBUG_LEVEL_BH )
2072 printk( "%s(%d):%s bh_status() entry\n",
2073 __FILE__,__LINE__,info->device_name);
2074
2075 info->ri_chkcount = 0;
2076 info->dsr_chkcount = 0;
2077 info->dcd_chkcount = 0;
2078 info->cts_chkcount = 0;
2079}
2080
2081static void isr_timer(SLMP_INFO * info)
2082{
2083 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2084
2085
2086 write_reg(info, IER2, 0);
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098 write_reg(info, (unsigned char)(timer + TMCS), 0);
2099
2100 info->irq_occurred = true;
2101
2102 if ( debug_level >= DEBUG_LEVEL_ISR )
2103 printk("%s(%d):%s isr_timer()\n",
2104 __FILE__,__LINE__,info->device_name);
2105}
2106
2107static void isr_rxint(SLMP_INFO * info)
2108{
2109 struct tty_struct *tty = info->port.tty;
2110 struct mgsl_icount *icount = &info->icount;
2111 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2112 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2113
2114
2115 if (status)
2116 write_reg(info, SR1, status);
2117
2118 if (status2)
2119 write_reg(info, SR2, status2);
2120
2121 if ( debug_level >= DEBUG_LEVEL_ISR )
2122 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2123 __FILE__,__LINE__,info->device_name,status,status2);
2124
2125 if (info->params.mode == MGSL_MODE_ASYNC) {
2126 if (status & BRKD) {
2127 icount->brk++;
2128
2129
2130
2131
2132 if (!(status & info->ignore_status_mask1)) {
2133 if (info->read_status_mask1 & BRKD) {
2134 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2135 if (tty && (info->port.flags & ASYNC_SAK))
2136 do_SAK(tty);
2137 }
2138 }
2139 }
2140 }
2141 else {
2142 if (status & (FLGD|IDLD)) {
2143 if (status & FLGD)
2144 info->icount.exithunt++;
2145 else if (status & IDLD)
2146 info->icount.rxidle++;
2147 wake_up_interruptible(&info->event_wait_q);
2148 }
2149 }
2150
2151 if (status & CDCD) {
2152
2153
2154
2155 get_signals( info );
2156 isr_io_pin(info,
2157 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2158 }
2159}
2160
2161
2162
2163
2164static void isr_rxrdy(SLMP_INFO * info)
2165{
2166 u16 status;
2167 unsigned char DataByte;
2168 struct mgsl_icount *icount = &info->icount;
2169
2170 if ( debug_level >= DEBUG_LEVEL_ISR )
2171 printk("%s(%d):%s isr_rxrdy\n",
2172 __FILE__,__LINE__,info->device_name);
2173
2174 while((status = read_reg(info,CST0)) & BIT0)
2175 {
2176 int flag = 0;
2177 bool over = false;
2178 DataByte = read_reg(info,TRB);
2179
2180 icount->rx++;
2181
2182 if ( status & (PE + FRME + OVRN) ) {
2183 printk("%s(%d):%s rxerr=%04X\n",
2184 __FILE__,__LINE__,info->device_name,status);
2185
2186
2187 if (status & PE)
2188 icount->parity++;
2189 else if (status & FRME)
2190 icount->frame++;
2191 else if (status & OVRN)
2192 icount->overrun++;
2193
2194
2195 if (status & info->ignore_status_mask2)
2196 continue;
2197
2198 status &= info->read_status_mask2;
2199
2200 if (status & PE)
2201 flag = TTY_PARITY;
2202 else if (status & FRME)
2203 flag = TTY_FRAME;
2204 if (status & OVRN) {
2205
2206
2207
2208
2209 over = true;
2210 }
2211 }
2212
2213 tty_insert_flip_char(&info->port, DataByte, flag);
2214 if (over)
2215 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2216 }
2217
2218 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2219 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2220 __FILE__,__LINE__,info->device_name,
2221 icount->rx,icount->brk,icount->parity,
2222 icount->frame,icount->overrun);
2223 }
2224
2225 tty_flip_buffer_push(&info->port);
2226}
2227
2228static void isr_txeom(SLMP_INFO * info, unsigned char status)
2229{
2230 if ( debug_level >= DEBUG_LEVEL_ISR )
2231 printk("%s(%d):%s isr_txeom status=%02x\n",
2232 __FILE__,__LINE__,info->device_name,status);
2233
2234 write_reg(info, TXDMA + DIR, 0x00);
2235 write_reg(info, TXDMA + DSR, 0xc0);
2236 write_reg(info, TXDMA + DCMD, SWABORT);
2237
2238 if (status & UDRN) {
2239 write_reg(info, CMD, TXRESET);
2240 write_reg(info, CMD, TXENABLE);
2241 } else
2242 write_reg(info, CMD, TXBUFCLR);
2243
2244
2245 info->ie0_value &= ~TXRDYE;
2246 info->ie1_value &= ~(IDLE + UDRN);
2247 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2248 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2249
2250 if ( info->tx_active ) {
2251 if (info->params.mode != MGSL_MODE_ASYNC) {
2252 if (status & UDRN)
2253 info->icount.txunder++;
2254 else if (status & IDLE)
2255 info->icount.txok++;
2256 }
2257
2258 info->tx_active = false;
2259 info->tx_count = info->tx_put = info->tx_get = 0;
2260
2261 del_timer(&info->tx_timer);
2262
2263 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2264 info->serial_signals &= ~SerialSignal_RTS;
2265 info->drop_rts_on_tx_done = false;
2266 set_signals(info);
2267 }
2268
2269#if SYNCLINK_GENERIC_HDLC
2270 if (info->netcount)
2271 hdlcdev_tx_done(info);
2272 else
2273#endif
2274 {
2275 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2276 tx_stop(info);
2277 return;
2278 }
2279 info->pending_bh |= BH_TRANSMIT;
2280 }
2281 }
2282}
2283
2284
2285
2286
2287
2288static void isr_txint(SLMP_INFO * info)
2289{
2290 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2291
2292
2293 write_reg(info, SR1, status);
2294
2295 if ( debug_level >= DEBUG_LEVEL_ISR )
2296 printk("%s(%d):%s isr_txint status=%02x\n",
2297 __FILE__,__LINE__,info->device_name,status);
2298
2299 if (status & (UDRN + IDLE))
2300 isr_txeom(info, status);
2301
2302 if (status & CCTS) {
2303
2304
2305
2306 get_signals( info );
2307 isr_io_pin(info,
2308 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2309
2310 }
2311}
2312
2313
2314
2315
2316static void isr_txrdy(SLMP_INFO * info)
2317{
2318 if ( debug_level >= DEBUG_LEVEL_ISR )
2319 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2320 __FILE__,__LINE__,info->device_name,info->tx_count);
2321
2322 if (info->params.mode != MGSL_MODE_ASYNC) {
2323
2324 info->ie0_value &= ~TXRDYE;
2325 info->ie1_value |= IDLE;
2326 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2327 return;
2328 }
2329
2330 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2331 tx_stop(info);
2332 return;
2333 }
2334
2335 if ( info->tx_count )
2336 tx_load_fifo( info );
2337 else {
2338 info->tx_active = false;
2339 info->ie0_value &= ~TXRDYE;
2340 write_reg(info, IE0, info->ie0_value);
2341 }
2342
2343 if (info->tx_count < WAKEUP_CHARS)
2344 info->pending_bh |= BH_TRANSMIT;
2345}
2346
2347static void isr_rxdmaok(SLMP_INFO * info)
2348{
2349
2350
2351
2352 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2353
2354
2355 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2356
2357 if ( debug_level >= DEBUG_LEVEL_ISR )
2358 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2359 __FILE__,__LINE__,info->device_name,status);
2360
2361 info->pending_bh |= BH_RECEIVE;
2362}
2363
2364static void isr_rxdmaerror(SLMP_INFO * info)
2365{
2366
2367
2368
2369 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2370
2371
2372 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2373
2374 if ( debug_level >= DEBUG_LEVEL_ISR )
2375 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2376 __FILE__,__LINE__,info->device_name,status);
2377
2378 info->rx_overflow = true;
2379 info->pending_bh |= BH_RECEIVE;
2380}
2381
2382static void isr_txdmaok(SLMP_INFO * info)
2383{
2384 unsigned char status_reg1 = read_reg(info, SR1);
2385
2386 write_reg(info, TXDMA + DIR, 0x00);
2387 write_reg(info, TXDMA + DSR, 0xc0);
2388 write_reg(info, TXDMA + DCMD, SWABORT);
2389
2390 if ( debug_level >= DEBUG_LEVEL_ISR )
2391 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2392 __FILE__,__LINE__,info->device_name,status_reg1);
2393
2394
2395 write_reg16(info, TRC0, 0);
2396 info->ie0_value |= TXRDYE;
2397 write_reg(info, IE0, info->ie0_value);
2398}
2399
2400static void isr_txdmaerror(SLMP_INFO * info)
2401{
2402
2403
2404
2405 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2406
2407
2408 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2412 __FILE__,__LINE__,info->device_name,status);
2413}
2414
2415
2416
2417static void isr_io_pin( SLMP_INFO *info, u16 status )
2418{
2419 struct mgsl_icount *icount;
2420
2421 if ( debug_level >= DEBUG_LEVEL_ISR )
2422 printk("%s(%d):isr_io_pin status=%04X\n",
2423 __FILE__,__LINE__,status);
2424
2425 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2426 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2427 icount = &info->icount;
2428
2429 if (status & MISCSTATUS_RI_LATCHED) {
2430 icount->rng++;
2431 if ( status & SerialSignal_RI )
2432 info->input_signal_events.ri_up++;
2433 else
2434 info->input_signal_events.ri_down++;
2435 }
2436 if (status & MISCSTATUS_DSR_LATCHED) {
2437 icount->dsr++;
2438 if ( status & SerialSignal_DSR )
2439 info->input_signal_events.dsr_up++;
2440 else
2441 info->input_signal_events.dsr_down++;
2442 }
2443 if (status & MISCSTATUS_DCD_LATCHED) {
2444 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2445 info->ie1_value &= ~CDCD;
2446 write_reg(info, IE1, info->ie1_value);
2447 }
2448 icount->dcd++;
2449 if (status & SerialSignal_DCD) {
2450 info->input_signal_events.dcd_up++;
2451 } else
2452 info->input_signal_events.dcd_down++;
2453#if SYNCLINK_GENERIC_HDLC
2454 if (info->netcount) {
2455 if (status & SerialSignal_DCD)
2456 netif_carrier_on(info->netdev);
2457 else
2458 netif_carrier_off(info->netdev);
2459 }
2460#endif
2461 }
2462 if (status & MISCSTATUS_CTS_LATCHED)
2463 {
2464 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2465 info->ie1_value &= ~CCTS;
2466 write_reg(info, IE1, info->ie1_value);
2467 }
2468 icount->cts++;
2469 if ( status & SerialSignal_CTS )
2470 info->input_signal_events.cts_up++;
2471 else
2472 info->input_signal_events.cts_down++;
2473 }
2474 wake_up_interruptible(&info->status_event_wait_q);
2475 wake_up_interruptible(&info->event_wait_q);
2476
2477 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2478 (status & MISCSTATUS_DCD_LATCHED) ) {
2479 if ( debug_level >= DEBUG_LEVEL_ISR )
2480 printk("%s CD now %s...", info->device_name,
2481 (status & SerialSignal_DCD) ? "on" : "off");
2482 if (status & SerialSignal_DCD)
2483 wake_up_interruptible(&info->port.open_wait);
2484 else {
2485 if ( debug_level >= DEBUG_LEVEL_ISR )
2486 printk("doing serial hangup...");
2487 if (info->port.tty)
2488 tty_hangup(info->port.tty);
2489 }
2490 }
2491
2492 if (tty_port_cts_enabled(&info->port) &&
2493 (status & MISCSTATUS_CTS_LATCHED) ) {
2494 if ( info->port.tty ) {
2495 if (info->port.tty->hw_stopped) {
2496 if (status & SerialSignal_CTS) {
2497 if ( debug_level >= DEBUG_LEVEL_ISR )
2498 printk("CTS tx start...");
2499 info->port.tty->hw_stopped = 0;
2500 tx_start(info);
2501 info->pending_bh |= BH_TRANSMIT;
2502 return;
2503 }
2504 } else {
2505 if (!(status & SerialSignal_CTS)) {
2506 if ( debug_level >= DEBUG_LEVEL_ISR )
2507 printk("CTS tx stop...");
2508 info->port.tty->hw_stopped = 1;
2509 tx_stop(info);
2510 }
2511 }
2512 }
2513 }
2514 }
2515
2516 info->pending_bh |= BH_STATUS;
2517}
2518
2519
2520
2521
2522
2523
2524
2525
2526static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2527{
2528 SLMP_INFO *info = dev_id;
2529 unsigned char status, status0, status1=0;
2530 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2531 unsigned char timerstatus0, timerstatus1=0;
2532 unsigned char shift;
2533 unsigned int i;
2534 unsigned short tmp;
2535
2536 if ( debug_level >= DEBUG_LEVEL_ISR )
2537 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2538 __FILE__, __LINE__, info->irq_level);
2539
2540 spin_lock(&info->lock);
2541
2542 for(;;) {
2543
2544
2545 tmp = read_reg16(info, ISR0);
2546 status0 = (unsigned char)tmp;
2547 dmastatus0 = (unsigned char)(tmp>>8);
2548 timerstatus0 = read_reg(info, ISR2);
2549
2550 if ( debug_level >= DEBUG_LEVEL_ISR )
2551 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2552 __FILE__, __LINE__, info->device_name,
2553 status0, dmastatus0, timerstatus0);
2554
2555 if (info->port_count == 4) {
2556
2557 tmp = read_reg16(info->port_array[2], ISR0);
2558 status1 = (unsigned char)tmp;
2559 dmastatus1 = (unsigned char)(tmp>>8);
2560 timerstatus1 = read_reg(info->port_array[2], ISR2);
2561
2562 if ( debug_level >= DEBUG_LEVEL_ISR )
2563 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2564 __FILE__,__LINE__,info->device_name,
2565 status1,dmastatus1,timerstatus1);
2566 }
2567
2568 if (!status0 && !dmastatus0 && !timerstatus0 &&
2569 !status1 && !dmastatus1 && !timerstatus1)
2570 break;
2571
2572 for(i=0; i < info->port_count ; i++) {
2573 if (info->port_array[i] == NULL)
2574 continue;
2575 if (i < 2) {
2576 status = status0;
2577 dmastatus = dmastatus0;
2578 } else {
2579 status = status1;
2580 dmastatus = dmastatus1;
2581 }
2582
2583 shift = i & 1 ? 4 :0;
2584
2585 if (status & BIT0 << shift)
2586 isr_rxrdy(info->port_array[i]);
2587 if (status & BIT1 << shift)
2588 isr_txrdy(info->port_array[i]);
2589 if (status & BIT2 << shift)
2590 isr_rxint(info->port_array[i]);
2591 if (status & BIT3 << shift)
2592 isr_txint(info->port_array[i]);
2593
2594 if (dmastatus & BIT0 << shift)
2595 isr_rxdmaerror(info->port_array[i]);
2596 if (dmastatus & BIT1 << shift)
2597 isr_rxdmaok(info->port_array[i]);
2598 if (dmastatus & BIT2 << shift)
2599 isr_txdmaerror(info->port_array[i]);
2600 if (dmastatus & BIT3 << shift)
2601 isr_txdmaok(info->port_array[i]);
2602 }
2603
2604 if (timerstatus0 & (BIT5 | BIT4))
2605 isr_timer(info->port_array[0]);
2606 if (timerstatus0 & (BIT7 | BIT6))
2607 isr_timer(info->port_array[1]);
2608 if (timerstatus1 & (BIT5 | BIT4))
2609 isr_timer(info->port_array[2]);
2610 if (timerstatus1 & (BIT7 | BIT6))
2611 isr_timer(info->port_array[3]);
2612 }
2613
2614 for(i=0; i < info->port_count ; i++) {
2615 SLMP_INFO * port = info->port_array[i];
2616
2617
2618
2619
2620
2621
2622
2623
2624 if ( port && (port->port.count || port->netcount) &&
2625 port->pending_bh && !port->bh_running &&
2626 !port->bh_requested ) {
2627 if ( debug_level >= DEBUG_LEVEL_ISR )
2628 printk("%s(%d):%s queueing bh task.\n",
2629 __FILE__,__LINE__,port->device_name);
2630 schedule_work(&port->task);
2631 port->bh_requested = true;
2632 }
2633 }
2634
2635 spin_unlock(&info->lock);
2636
2637 if ( debug_level >= DEBUG_LEVEL_ISR )
2638 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2639 __FILE__, __LINE__, info->irq_level);
2640 return IRQ_HANDLED;
2641}
2642
2643
2644
2645static int startup(SLMP_INFO * info)
2646{
2647 if ( debug_level >= DEBUG_LEVEL_INFO )
2648 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2649
2650 if (info->port.flags & ASYNC_INITIALIZED)
2651 return 0;
2652
2653 if (!info->tx_buf) {
2654 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2655 if (!info->tx_buf) {
2656 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2657 __FILE__,__LINE__,info->device_name);
2658 return -ENOMEM;
2659 }
2660 }
2661
2662 info->pending_bh = 0;
2663
2664 memset(&info->icount, 0, sizeof(info->icount));
2665
2666
2667 reset_port(info);
2668
2669 change_params(info);
2670
2671 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2672
2673 if (info->port.tty)
2674 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2675
2676 info->port.flags |= ASYNC_INITIALIZED;
2677
2678 return 0;
2679}
2680
2681
2682
2683static void shutdown(SLMP_INFO * info)
2684{
2685 unsigned long flags;
2686
2687 if (!(info->port.flags & ASYNC_INITIALIZED))
2688 return;
2689
2690 if (debug_level >= DEBUG_LEVEL_INFO)
2691 printk("%s(%d):%s synclinkmp_shutdown()\n",
2692 __FILE__,__LINE__, info->device_name );
2693
2694
2695
2696 wake_up_interruptible(&info->status_event_wait_q);
2697 wake_up_interruptible(&info->event_wait_q);
2698
2699 del_timer(&info->tx_timer);
2700 del_timer(&info->status_timer);
2701
2702 kfree(info->tx_buf);
2703 info->tx_buf = NULL;
2704
2705 spin_lock_irqsave(&info->lock,flags);
2706
2707 reset_port(info);
2708
2709 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2710 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2711 set_signals(info);
2712 }
2713
2714 spin_unlock_irqrestore(&info->lock,flags);
2715
2716 if (info->port.tty)
2717 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2718
2719 info->port.flags &= ~ASYNC_INITIALIZED;
2720}
2721
2722static void program_hw(SLMP_INFO *info)
2723{
2724 unsigned long flags;
2725
2726 spin_lock_irqsave(&info->lock,flags);
2727
2728 rx_stop(info);
2729 tx_stop(info);
2730
2731 info->tx_count = info->tx_put = info->tx_get = 0;
2732
2733 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2734 hdlc_mode(info);
2735 else
2736 async_mode(info);
2737
2738 set_signals(info);
2739
2740 info->dcd_chkcount = 0;
2741 info->cts_chkcount = 0;
2742 info->ri_chkcount = 0;
2743 info->dsr_chkcount = 0;
2744
2745 info->ie1_value |= (CDCD|CCTS);
2746 write_reg(info, IE1, info->ie1_value);
2747
2748 get_signals(info);
2749
2750 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2751 rx_start(info);
2752
2753 spin_unlock_irqrestore(&info->lock,flags);
2754}
2755
2756
2757
2758static void change_params(SLMP_INFO *info)
2759{
2760 unsigned cflag;
2761 int bits_per_char;
2762
2763 if (!info->port.tty)
2764 return;
2765
2766 if (debug_level >= DEBUG_LEVEL_INFO)
2767 printk("%s(%d):%s change_params()\n",
2768 __FILE__,__LINE__, info->device_name );
2769
2770 cflag = info->port.tty->termios.c_cflag;
2771
2772
2773
2774 if (cflag & CBAUD)
2775 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2776 else
2777 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2778
2779
2780
2781 switch (cflag & CSIZE) {
2782 case CS5: info->params.data_bits = 5; break;
2783 case CS6: info->params.data_bits = 6; break;
2784 case CS7: info->params.data_bits = 7; break;
2785 case CS8: info->params.data_bits = 8; break;
2786
2787 default: info->params.data_bits = 7; break;
2788 }
2789
2790 if (cflag & CSTOPB)
2791 info->params.stop_bits = 2;
2792 else
2793 info->params.stop_bits = 1;
2794
2795 info->params.parity = ASYNC_PARITY_NONE;
2796 if (cflag & PARENB) {
2797 if (cflag & PARODD)
2798 info->params.parity = ASYNC_PARITY_ODD;
2799 else
2800 info->params.parity = ASYNC_PARITY_EVEN;
2801#ifdef CMSPAR
2802 if (cflag & CMSPAR)
2803 info->params.parity = ASYNC_PARITY_SPACE;
2804#endif
2805 }
2806
2807
2808
2809
2810 bits_per_char = info->params.data_bits +
2811 info->params.stop_bits + 1;
2812
2813
2814
2815
2816
2817 if (info->params.data_rate <= 460800) {
2818 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2819 }
2820
2821 if ( info->params.data_rate ) {
2822 info->timeout = (32*HZ*bits_per_char) /
2823 info->params.data_rate;
2824 }
2825 info->timeout += HZ/50;
2826
2827 if (cflag & CRTSCTS)
2828 info->port.flags |= ASYNC_CTS_FLOW;
2829 else
2830 info->port.flags &= ~ASYNC_CTS_FLOW;
2831
2832 if (cflag & CLOCAL)
2833 info->port.flags &= ~ASYNC_CHECK_CD;
2834 else
2835 info->port.flags |= ASYNC_CHECK_CD;
2836
2837
2838
2839 info->read_status_mask2 = OVRN;
2840 if (I_INPCK(info->port.tty))
2841 info->read_status_mask2 |= PE | FRME;
2842 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2843 info->read_status_mask1 |= BRKD;
2844 if (I_IGNPAR(info->port.tty))
2845 info->ignore_status_mask2 |= PE | FRME;
2846 if (I_IGNBRK(info->port.tty)) {
2847 info->ignore_status_mask1 |= BRKD;
2848
2849
2850
2851 if (I_IGNPAR(info->port.tty))
2852 info->ignore_status_mask2 |= OVRN;
2853 }
2854
2855 program_hw(info);
2856}
2857
2858static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2859{
2860 int err;
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s get_params()\n",
2864 __FILE__,__LINE__, info->device_name);
2865
2866 if (!user_icount) {
2867 memset(&info->icount, 0, sizeof(info->icount));
2868 } else {
2869 mutex_lock(&info->port.mutex);
2870 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2871 mutex_unlock(&info->port.mutex);
2872 if (err)
2873 return -EFAULT;
2874 }
2875
2876 return 0;
2877}
2878
2879static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2880{
2881 int err;
2882 if (debug_level >= DEBUG_LEVEL_INFO)
2883 printk("%s(%d):%s get_params()\n",
2884 __FILE__,__LINE__, info->device_name);
2885
2886 mutex_lock(&info->port.mutex);
2887 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2888 mutex_unlock(&info->port.mutex);
2889 if (err) {
2890 if ( debug_level >= DEBUG_LEVEL_INFO )
2891 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2892 __FILE__,__LINE__,info->device_name);
2893 return -EFAULT;
2894 }
2895
2896 return 0;
2897}
2898
2899static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2900{
2901 unsigned long flags;
2902 MGSL_PARAMS tmp_params;
2903 int err;
2904
2905 if (debug_level >= DEBUG_LEVEL_INFO)
2906 printk("%s(%d):%s set_params\n",
2907 __FILE__,__LINE__,info->device_name );
2908 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2909 if (err) {
2910 if ( debug_level >= DEBUG_LEVEL_INFO )
2911 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2912 __FILE__,__LINE__,info->device_name);
2913 return -EFAULT;
2914 }
2915
2916 mutex_lock(&info->port.mutex);
2917 spin_lock_irqsave(&info->lock,flags);
2918 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2919 spin_unlock_irqrestore(&info->lock,flags);
2920
2921 change_params(info);
2922 mutex_unlock(&info->port.mutex);
2923
2924 return 0;
2925}
2926
2927static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2928{
2929 int err;
2930
2931 if (debug_level >= DEBUG_LEVEL_INFO)
2932 printk("%s(%d):%s get_txidle()=%d\n",
2933 __FILE__,__LINE__, info->device_name, info->idle_mode);
2934
2935 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2936 if (err) {
2937 if ( debug_level >= DEBUG_LEVEL_INFO )
2938 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2939 __FILE__,__LINE__,info->device_name);
2940 return -EFAULT;
2941 }
2942
2943 return 0;
2944}
2945
2946static int set_txidle(SLMP_INFO * info, int idle_mode)
2947{
2948 unsigned long flags;
2949
2950 if (debug_level >= DEBUG_LEVEL_INFO)
2951 printk("%s(%d):%s set_txidle(%d)\n",
2952 __FILE__,__LINE__,info->device_name, idle_mode );
2953
2954 spin_lock_irqsave(&info->lock,flags);
2955 info->idle_mode = idle_mode;
2956 tx_set_idle( info );
2957 spin_unlock_irqrestore(&info->lock,flags);
2958 return 0;
2959}
2960
2961static int tx_enable(SLMP_INFO * info, int enable)
2962{
2963 unsigned long flags;
2964
2965 if (debug_level >= DEBUG_LEVEL_INFO)
2966 printk("%s(%d):%s tx_enable(%d)\n",
2967 __FILE__,__LINE__,info->device_name, enable);
2968
2969 spin_lock_irqsave(&info->lock,flags);
2970 if ( enable ) {
2971 if ( !info->tx_enabled ) {
2972 tx_start(info);
2973 }
2974 } else {
2975 if ( info->tx_enabled )
2976 tx_stop(info);
2977 }
2978 spin_unlock_irqrestore(&info->lock,flags);
2979 return 0;
2980}
2981
2982
2983
2984static int tx_abort(SLMP_INFO * info)
2985{
2986 unsigned long flags;
2987
2988 if (debug_level >= DEBUG_LEVEL_INFO)
2989 printk("%s(%d):%s tx_abort()\n",
2990 __FILE__,__LINE__,info->device_name);
2991
2992 spin_lock_irqsave(&info->lock,flags);
2993 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2994 info->ie1_value &= ~UDRN;
2995 info->ie1_value |= IDLE;
2996 write_reg(info, IE1, info->ie1_value);
2997 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
2998
2999 write_reg(info, TXDMA + DSR, 0);
3000 write_reg(info, TXDMA + DCMD, SWABORT);
3001
3002 write_reg(info, CMD, TXABORT);
3003 }
3004 spin_unlock_irqrestore(&info->lock,flags);
3005 return 0;
3006}
3007
3008static int rx_enable(SLMP_INFO * info, int enable)
3009{
3010 unsigned long flags;
3011
3012 if (debug_level >= DEBUG_LEVEL_INFO)
3013 printk("%s(%d):%s rx_enable(%d)\n",
3014 __FILE__,__LINE__,info->device_name,enable);
3015
3016 spin_lock_irqsave(&info->lock,flags);
3017 if ( enable ) {
3018 if ( !info->rx_enabled )
3019 rx_start(info);
3020 } else {
3021 if ( info->rx_enabled )
3022 rx_stop(info);
3023 }
3024 spin_unlock_irqrestore(&info->lock,flags);
3025 return 0;
3026}
3027
3028
3029
3030static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3031{
3032 unsigned long flags;
3033 int s;
3034 int rc=0;
3035 struct mgsl_icount cprev, cnow;
3036 int events;
3037 int mask;
3038 struct _input_signal_events oldsigs, newsigs;
3039 DECLARE_WAITQUEUE(wait, current);
3040
3041 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3042 if (rc) {
3043 return -EFAULT;
3044 }
3045
3046 if (debug_level >= DEBUG_LEVEL_INFO)
3047 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3048 __FILE__,__LINE__,info->device_name,mask);
3049
3050 spin_lock_irqsave(&info->lock,flags);
3051
3052
3053 get_signals(info);
3054 s = info->serial_signals;
3055
3056 events = mask &
3057 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3058 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3059 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3060 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3061 if (events) {
3062 spin_unlock_irqrestore(&info->lock,flags);
3063 goto exit;
3064 }
3065
3066
3067 cprev = info->icount;
3068 oldsigs = info->input_signal_events;
3069
3070
3071 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3072 unsigned char oldval = info->ie1_value;
3073 unsigned char newval = oldval +
3074 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3075 (mask & MgslEvent_IdleReceived ? IDLD:0);
3076 if ( oldval != newval ) {
3077 info->ie1_value = newval;
3078 write_reg(info, IE1, info->ie1_value);
3079 }
3080 }
3081
3082 set_current_state(TASK_INTERRUPTIBLE);
3083 add_wait_queue(&info->event_wait_q, &wait);
3084
3085 spin_unlock_irqrestore(&info->lock,flags);
3086
3087 for(;;) {
3088 schedule();
3089 if (signal_pending(current)) {
3090 rc = -ERESTARTSYS;
3091 break;
3092 }
3093
3094
3095 spin_lock_irqsave(&info->lock,flags);
3096 cnow = info->icount;
3097 newsigs = info->input_signal_events;
3098 set_current_state(TASK_INTERRUPTIBLE);
3099 spin_unlock_irqrestore(&info->lock,flags);
3100
3101
3102 if (newsigs.dsr_up == oldsigs.dsr_up &&
3103 newsigs.dsr_down == oldsigs.dsr_down &&
3104 newsigs.dcd_up == oldsigs.dcd_up &&
3105 newsigs.dcd_down == oldsigs.dcd_down &&
3106 newsigs.cts_up == oldsigs.cts_up &&
3107 newsigs.cts_down == oldsigs.cts_down &&
3108 newsigs.ri_up == oldsigs.ri_up &&
3109 newsigs.ri_down == oldsigs.ri_down &&
3110 cnow.exithunt == cprev.exithunt &&
3111 cnow.rxidle == cprev.rxidle) {
3112 rc = -EIO;
3113 break;
3114 }
3115
3116 events = mask &
3117 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3118 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3119 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3120 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3121 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3122 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3123 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3124 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3125 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3126 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3127 if (events)
3128 break;
3129
3130 cprev = cnow;
3131 oldsigs = newsigs;
3132 }
3133
3134 remove_wait_queue(&info->event_wait_q, &wait);
3135 set_current_state(TASK_RUNNING);
3136
3137
3138 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3139 spin_lock_irqsave(&info->lock,flags);
3140 if (!waitqueue_active(&info->event_wait_q)) {
3141
3142 info->ie1_value &= ~(FLGD|IDLD);
3143 write_reg(info, IE1, info->ie1_value);
3144 }
3145 spin_unlock_irqrestore(&info->lock,flags);
3146 }
3147exit:
3148 if ( rc == 0 )
3149 PUT_USER(rc, events, mask_ptr);
3150
3151 return rc;
3152}
3153
3154static int modem_input_wait(SLMP_INFO *info,int arg)
3155{
3156 unsigned long flags;
3157 int rc;
3158 struct mgsl_icount cprev, cnow;
3159 DECLARE_WAITQUEUE(wait, current);
3160
3161
3162 spin_lock_irqsave(&info->lock,flags);
3163 cprev = info->icount;
3164 add_wait_queue(&info->status_event_wait_q, &wait);
3165 set_current_state(TASK_INTERRUPTIBLE);
3166 spin_unlock_irqrestore(&info->lock,flags);
3167
3168 for(;;) {
3169 schedule();
3170 if (signal_pending(current)) {
3171 rc = -ERESTARTSYS;
3172 break;
3173 }
3174
3175
3176 spin_lock_irqsave(&info->lock,flags);
3177 cnow = info->icount;
3178 set_current_state(TASK_INTERRUPTIBLE);
3179 spin_unlock_irqrestore(&info->lock,flags);
3180
3181
3182 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3183 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3184 rc = -EIO;
3185 break;
3186 }
3187
3188
3189 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3190 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3191 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3192 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3193 rc = 0;
3194 break;
3195 }
3196
3197 cprev = cnow;
3198 }
3199 remove_wait_queue(&info->status_event_wait_q, &wait);
3200 set_current_state(TASK_RUNNING);
3201 return rc;
3202}
3203
3204
3205
3206static int tiocmget(struct tty_struct *tty)
3207{
3208 SLMP_INFO *info = tty->driver_data;
3209 unsigned int result;
3210 unsigned long flags;
3211
3212 spin_lock_irqsave(&info->lock,flags);
3213 get_signals(info);
3214 spin_unlock_irqrestore(&info->lock,flags);
3215
3216 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3217 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3218 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3219 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3220 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3221 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3222
3223 if (debug_level >= DEBUG_LEVEL_INFO)
3224 printk("%s(%d):%s tiocmget() value=%08X\n",
3225 __FILE__,__LINE__, info->device_name, result );
3226 return result;
3227}
3228
3229
3230
3231static int tiocmset(struct tty_struct *tty,
3232 unsigned int set, unsigned int clear)
3233{
3234 SLMP_INFO *info = tty->driver_data;
3235 unsigned long flags;
3236
3237 if (debug_level >= DEBUG_LEVEL_INFO)
3238 printk("%s(%d):%s tiocmset(%x,%x)\n",
3239 __FILE__,__LINE__,info->device_name, set, clear);
3240
3241 if (set & TIOCM_RTS)
3242 info->serial_signals |= SerialSignal_RTS;
3243 if (set & TIOCM_DTR)
3244 info->serial_signals |= SerialSignal_DTR;
3245 if (clear & TIOCM_RTS)
3246 info->serial_signals &= ~SerialSignal_RTS;
3247 if (clear & TIOCM_DTR)
3248 info->serial_signals &= ~SerialSignal_DTR;
3249
3250 spin_lock_irqsave(&info->lock,flags);
3251 set_signals(info);
3252 spin_unlock_irqrestore(&info->lock,flags);
3253
3254 return 0;
3255}
3256
3257static int carrier_raised(struct tty_port *port)
3258{
3259 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3260 unsigned long flags;
3261
3262 spin_lock_irqsave(&info->lock,flags);
3263 get_signals(info);
3264 spin_unlock_irqrestore(&info->lock,flags);
3265
3266 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3267}
3268
3269static void dtr_rts(struct tty_port *port, int on)
3270{
3271 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3272 unsigned long flags;
3273
3274 spin_lock_irqsave(&info->lock,flags);
3275 if (on)
3276 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3277 else
3278 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3279 set_signals(info);
3280 spin_unlock_irqrestore(&info->lock,flags);
3281}
3282
3283
3284
3285static int block_til_ready(struct tty_struct *tty, struct file *filp,
3286 SLMP_INFO *info)
3287{
3288 DECLARE_WAITQUEUE(wait, current);
3289 int retval;
3290 bool do_clocal = false;
3291 unsigned long flags;
3292 int cd;
3293 struct tty_port *port = &info->port;
3294
3295 if (debug_level >= DEBUG_LEVEL_INFO)
3296 printk("%s(%d):%s block_til_ready()\n",
3297 __FILE__,__LINE__, tty->driver->name );
3298
3299 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3300
3301
3302 port->flags |= ASYNC_NORMAL_ACTIVE;
3303 return 0;
3304 }
3305
3306 if (tty->termios.c_cflag & CLOCAL)
3307 do_clocal = true;
3308
3309
3310
3311
3312
3313
3314
3315
3316 retval = 0;
3317 add_wait_queue(&port->open_wait, &wait);
3318
3319 if (debug_level >= DEBUG_LEVEL_INFO)
3320 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3321 __FILE__,__LINE__, tty->driver->name, port->count );
3322
3323 spin_lock_irqsave(&info->lock, flags);
3324 port->count--;
3325 spin_unlock_irqrestore(&info->lock, flags);
3326 port->blocked_open++;
3327
3328 while (1) {
3329 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3330 tty_port_raise_dtr_rts(port);
3331
3332 set_current_state(TASK_INTERRUPTIBLE);
3333
3334 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3335 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3336 -EAGAIN : -ERESTARTSYS;
3337 break;
3338 }
3339
3340 cd = tty_port_carrier_raised(port);
3341
3342 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3343 break;
3344
3345 if (signal_pending(current)) {
3346 retval = -ERESTARTSYS;
3347 break;
3348 }
3349
3350 if (debug_level >= DEBUG_LEVEL_INFO)
3351 printk("%s(%d):%s block_til_ready() count=%d\n",
3352 __FILE__,__LINE__, tty->driver->name, port->count );
3353
3354 tty_unlock(tty);
3355 schedule();
3356 tty_lock(tty);
3357 }
3358
3359 set_current_state(TASK_RUNNING);
3360 remove_wait_queue(&port->open_wait, &wait);
3361 if (!tty_hung_up_p(filp))
3362 port->count++;
3363 port->blocked_open--;
3364
3365 if (debug_level >= DEBUG_LEVEL_INFO)
3366 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3367 __FILE__,__LINE__, tty->driver->name, port->count );
3368
3369 if (!retval)
3370 port->flags |= ASYNC_NORMAL_ACTIVE;
3371
3372 return retval;
3373}
3374
3375static int alloc_dma_bufs(SLMP_INFO *info)
3376{
3377 unsigned short BuffersPerFrame;
3378 unsigned short BufferCount;
3379
3380
3381
3382
3383
3384
3385 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3386
3387
3388
3389
3390
3391
3392 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3393 if ( info->max_frame_size % SCABUFSIZE )
3394 BuffersPerFrame++;
3395
3396
3397
3398
3399
3400 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3401
3402
3403 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3404 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3405
3406
3407 info->tx_buf_count = BuffersPerFrame + 1;
3408
3409
3410 if (info->tx_buf_count > (BufferCount/2))
3411 info->tx_buf_count = BufferCount/2;
3412
3413 if (info->tx_buf_count > SCAMAXDESC)
3414 info->tx_buf_count = SCAMAXDESC;
3415
3416
3417 info->rx_buf_count = BufferCount - info->tx_buf_count;
3418
3419 if (info->rx_buf_count > SCAMAXDESC)
3420 info->rx_buf_count = SCAMAXDESC;
3421
3422 if ( debug_level >= DEBUG_LEVEL_INFO )
3423 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3424 __FILE__,__LINE__, info->device_name,
3425 info->tx_buf_count,info->rx_buf_count);
3426
3427 if ( alloc_buf_list( info ) < 0 ||
3428 alloc_frame_bufs(info,
3429 info->rx_buf_list,
3430 info->rx_buf_list_ex,
3431 info->rx_buf_count) < 0 ||
3432 alloc_frame_bufs(info,
3433 info->tx_buf_list,
3434 info->tx_buf_list_ex,
3435 info->tx_buf_count) < 0 ||
3436 alloc_tmp_rx_buf(info) < 0 ) {
3437 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3438 __FILE__,__LINE__, info->device_name);
3439 return -ENOMEM;
3440 }
3441
3442 rx_reset_buffers( info );
3443
3444 return 0;
3445}
3446
3447
3448
3449static int alloc_buf_list(SLMP_INFO *info)
3450{
3451 unsigned int i;
3452
3453
3454 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3455 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3456 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3457
3458 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3459
3460
3461
3462
3463 info->rx_buf_list = (SCADESC *)info->buffer_list;
3464
3465 info->tx_buf_list = (SCADESC *)info->buffer_list;
3466 info->tx_buf_list += info->rx_buf_count;
3467
3468
3469
3470
3471
3472
3473
3474 for ( i = 0; i < info->rx_buf_count; i++ ) {
3475
3476 info->rx_buf_list_ex[i].phys_entry =
3477 info->buffer_list_phys + (i * SCABUFSIZE);
3478
3479
3480
3481 info->rx_buf_list[i].next = info->buffer_list_phys;
3482 if ( i < info->rx_buf_count - 1 )
3483 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3484
3485 info->rx_buf_list[i].length = SCABUFSIZE;
3486 }
3487
3488 for ( i = 0; i < info->tx_buf_count; i++ ) {
3489
3490 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3491 ((info->rx_buf_count + i) * sizeof(SCADESC));
3492
3493
3494
3495
3496 info->tx_buf_list[i].next = info->buffer_list_phys +
3497 info->rx_buf_count * sizeof(SCADESC);
3498
3499 if ( i < info->tx_buf_count - 1 )
3500 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3501 }
3502
3503 return 0;
3504}
3505
3506
3507
3508static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3509{
3510 int i;
3511 unsigned long phys_addr;
3512
3513 for ( i = 0; i < count; i++ ) {
3514 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3515 phys_addr = info->port_array[0]->last_mem_alloc;
3516 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3517
3518 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3519 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3520 }
3521
3522 return 0;
3523}
3524
3525static void free_dma_bufs(SLMP_INFO *info)
3526{
3527 info->buffer_list = NULL;
3528 info->rx_buf_list = NULL;
3529 info->tx_buf_list = NULL;
3530}
3531
3532
3533
3534
3535static int alloc_tmp_rx_buf(SLMP_INFO *info)
3536{
3537 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3538 if (info->tmp_rx_buf == NULL)
3539 return -ENOMEM;
3540
3541 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3542 if (!info->flag_buf) {
3543 kfree(info->tmp_rx_buf);
3544 info->tmp_rx_buf = NULL;
3545 return -ENOMEM;
3546 }
3547 return 0;
3548}
3549
3550static void free_tmp_rx_buf(SLMP_INFO *info)
3551{
3552 kfree(info->tmp_rx_buf);
3553 info->tmp_rx_buf = NULL;
3554 kfree(info->flag_buf);
3555 info->flag_buf = NULL;
3556}
3557
3558static int claim_resources(SLMP_INFO *info)
3559{
3560 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3561 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3562 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3563 info->init_error = DiagStatus_AddressConflict;
3564 goto errout;
3565 }
3566 else
3567 info->shared_mem_requested = true;
3568
3569 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3570 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3571 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3572 info->init_error = DiagStatus_AddressConflict;
3573 goto errout;
3574 }
3575 else
3576 info->lcr_mem_requested = true;
3577
3578 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3579 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3580 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3581 info->init_error = DiagStatus_AddressConflict;
3582 goto errout;
3583 }
3584 else
3585 info->sca_base_requested = true;
3586
3587 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3588 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3589 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3590 info->init_error = DiagStatus_AddressConflict;
3591 goto errout;
3592 }
3593 else
3594 info->sca_statctrl_requested = true;
3595
3596 info->memory_base = ioremap_nocache(info->phys_memory_base,
3597 SCA_MEM_SIZE);
3598 if (!info->memory_base) {
3599 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3600 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3601 info->init_error = DiagStatus_CantAssignPciResources;
3602 goto errout;
3603 }
3604
3605 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3606 if (!info->lcr_base) {
3607 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3608 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3609 info->init_error = DiagStatus_CantAssignPciResources;
3610 goto errout;
3611 }
3612 info->lcr_base += info->lcr_offset;
3613
3614 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3615 if (!info->sca_base) {
3616 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3617 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3618 info->init_error = DiagStatus_CantAssignPciResources;
3619 goto errout;
3620 }
3621 info->sca_base += info->sca_offset;
3622
3623 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3624 PAGE_SIZE);
3625 if (!info->statctrl_base) {
3626 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3627 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3628 info->init_error = DiagStatus_CantAssignPciResources;
3629 goto errout;
3630 }
3631 info->statctrl_base += info->statctrl_offset;
3632
3633 if ( !memory_test(info) ) {
3634 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3635 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3636 info->init_error = DiagStatus_MemoryError;
3637 goto errout;
3638 }
3639
3640 return 0;
3641
3642errout:
3643 release_resources( info );
3644 return -ENODEV;
3645}
3646
3647static void release_resources(SLMP_INFO *info)
3648{
3649 if ( debug_level >= DEBUG_LEVEL_INFO )
3650 printk( "%s(%d):%s release_resources() entry\n",
3651 __FILE__,__LINE__,info->device_name );
3652
3653 if ( info->irq_requested ) {
3654 free_irq(info->irq_level, info);
3655 info->irq_requested = false;
3656 }
3657
3658 if ( info->shared_mem_requested ) {
3659 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3660 info->shared_mem_requested = false;
3661 }
3662 if ( info->lcr_mem_requested ) {
3663 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3664 info->lcr_mem_requested = false;
3665 }
3666 if ( info->sca_base_requested ) {
3667 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3668 info->sca_base_requested = false;
3669 }
3670 if ( info->sca_statctrl_requested ) {
3671 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3672 info->sca_statctrl_requested = false;
3673 }
3674
3675 if (info->memory_base){
3676 iounmap(info->memory_base);
3677 info->memory_base = NULL;
3678 }
3679
3680 if (info->sca_base) {
3681 iounmap(info->sca_base - info->sca_offset);
3682 info->sca_base=NULL;
3683 }
3684
3685 if (info->statctrl_base) {
3686 iounmap(info->statctrl_base - info->statctrl_offset);
3687 info->statctrl_base=NULL;
3688 }
3689
3690 if (info->lcr_base){
3691 iounmap(info->lcr_base - info->lcr_offset);
3692 info->lcr_base = NULL;
3693 }
3694
3695 if ( debug_level >= DEBUG_LEVEL_INFO )
3696 printk( "%s(%d):%s release_resources() exit\n",
3697 __FILE__,__LINE__,info->device_name );
3698}
3699
3700
3701
3702
3703static void add_device(SLMP_INFO *info)
3704{
3705 info->next_device = NULL;
3706 info->line = synclinkmp_device_count;
3707 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3708
3709 if (info->line < MAX_DEVICES) {
3710 if (maxframe[info->line])
3711 info->max_frame_size = maxframe[info->line];
3712 }
3713
3714 synclinkmp_device_count++;
3715
3716 if ( !synclinkmp_device_list )
3717 synclinkmp_device_list = info;
3718 else {
3719 SLMP_INFO *current_dev = synclinkmp_device_list;
3720 while( current_dev->next_device )
3721 current_dev = current_dev->next_device;
3722 current_dev->next_device = info;
3723 }
3724
3725 if ( info->max_frame_size < 4096 )
3726 info->max_frame_size = 4096;
3727 else if ( info->max_frame_size > 65535 )
3728 info->max_frame_size = 65535;
3729
3730 printk( "SyncLink MultiPort %s: "
3731 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3732 info->device_name,
3733 info->phys_sca_base,
3734 info->phys_memory_base,
3735 info->phys_statctrl_base,
3736 info->phys_lcr_base,
3737 info->irq_level,
3738 info->max_frame_size );
3739
3740#if SYNCLINK_GENERIC_HDLC
3741 hdlcdev_init(info);
3742#endif
3743}
3744
3745static const struct tty_port_operations port_ops = {
3746 .carrier_raised = carrier_raised,
3747 .dtr_rts = dtr_rts,
3748};
3749
3750
3751
3752
3753
3754static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3755{
3756 SLMP_INFO *info;
3757
3758 info = kzalloc(sizeof(SLMP_INFO),
3759 GFP_KERNEL);
3760
3761 if (!info) {
3762 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3763 __FILE__,__LINE__, adapter_num, port_num);
3764 } else {
3765 tty_port_init(&info->port);
3766 info->port.ops = &port_ops;
3767 info->magic = MGSL_MAGIC;
3768 INIT_WORK(&info->task, bh_handler);
3769 info->max_frame_size = 4096;
3770 info->port.close_delay = 5*HZ/10;
3771 info->port.closing_wait = 30*HZ;
3772 init_waitqueue_head(&info->status_event_wait_q);
3773 init_waitqueue_head(&info->event_wait_q);
3774 spin_lock_init(&info->netlock);
3775 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3776 info->idle_mode = HDLC_TXIDLE_FLAGS;
3777 info->adapter_num = adapter_num;
3778 info->port_num = port_num;
3779
3780
3781 info->irq_level = pdev->irq;
3782 info->phys_lcr_base = pci_resource_start(pdev,0);
3783 info->phys_sca_base = pci_resource_start(pdev,2);
3784 info->phys_memory_base = pci_resource_start(pdev,3);
3785 info->phys_statctrl_base = pci_resource_start(pdev,4);
3786
3787
3788
3789
3790
3791 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3792 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3793
3794 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3795 info->phys_sca_base &= ~(PAGE_SIZE-1);
3796
3797 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3798 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3799
3800 info->bus_type = MGSL_BUS_TYPE_PCI;
3801 info->irq_flags = IRQF_SHARED;
3802
3803 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3804 setup_timer(&info->status_timer, status_timeout,
3805 (unsigned long)info);
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816 info->misc_ctrl_value = 0x087e4546;
3817
3818
3819
3820
3821
3822
3823
3824 info->init_error = -1;
3825 }
3826
3827 return info;
3828}
3829
3830static void device_init(int adapter_num, struct pci_dev *pdev)
3831{
3832 SLMP_INFO *port_array[SCA_MAX_PORTS];
3833 int port;
3834
3835
3836 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3837 port_array[port] = alloc_dev(adapter_num,port,pdev);
3838 if( port_array[port] == NULL ) {
3839 for (--port; port >= 0; --port) {
3840 tty_port_destroy(&port_array[port]->port);
3841 kfree(port_array[port]);
3842 }
3843 return;
3844 }
3845 }
3846
3847
3848 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3849 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3850 add_device( port_array[port] );
3851 spin_lock_init(&port_array[port]->lock);
3852 }
3853
3854
3855 if ( !claim_resources(port_array[0]) ) {
3856
3857 alloc_dma_bufs(port_array[0]);
3858
3859
3860 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3861 port_array[port]->lock = port_array[0]->lock;
3862 port_array[port]->irq_level = port_array[0]->irq_level;
3863 port_array[port]->memory_base = port_array[0]->memory_base;
3864 port_array[port]->sca_base = port_array[0]->sca_base;
3865 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3866 port_array[port]->lcr_base = port_array[0]->lcr_base;
3867 alloc_dma_bufs(port_array[port]);
3868 }
3869
3870 if ( request_irq(port_array[0]->irq_level,
3871 synclinkmp_interrupt,
3872 port_array[0]->irq_flags,
3873 port_array[0]->device_name,
3874 port_array[0]) < 0 ) {
3875 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3876 __FILE__,__LINE__,
3877 port_array[0]->device_name,
3878 port_array[0]->irq_level );
3879 }
3880 else {
3881 port_array[0]->irq_requested = true;
3882 adapter_test(port_array[0]);
3883 }
3884 }
3885}
3886
3887static const struct tty_operations ops = {
3888 .install = install,
3889 .open = open,
3890 .close = close,
3891 .write = write,
3892 .put_char = put_char,
3893 .flush_chars = flush_chars,
3894 .write_room = write_room,
3895 .chars_in_buffer = chars_in_buffer,
3896 .flush_buffer = flush_buffer,
3897 .ioctl = ioctl,
3898 .throttle = throttle,
3899 .unthrottle = unthrottle,
3900 .send_xchar = send_xchar,
3901 .break_ctl = set_break,
3902 .wait_until_sent = wait_until_sent,
3903 .set_termios = set_termios,
3904 .stop = tx_hold,
3905 .start = tx_release,
3906 .hangup = hangup,
3907 .tiocmget = tiocmget,
3908 .tiocmset = tiocmset,
3909 .get_icount = get_icount,
3910 .proc_fops = &synclinkmp_proc_fops,
3911};
3912
3913
3914static void synclinkmp_cleanup(void)
3915{
3916 int rc;
3917 SLMP_INFO *info;
3918 SLMP_INFO *tmp;
3919
3920 printk("Unloading %s %s\n", driver_name, driver_version);
3921
3922 if (serial_driver) {
3923 if ((rc = tty_unregister_driver(serial_driver)))
3924 printk("%s(%d) failed to unregister tty driver err=%d\n",
3925 __FILE__,__LINE__,rc);
3926 put_tty_driver(serial_driver);
3927 }
3928
3929
3930 info = synclinkmp_device_list;
3931 while(info) {
3932 reset_port(info);
3933 info = info->next_device;
3934 }
3935
3936
3937 info = synclinkmp_device_list;
3938 while(info) {
3939#if SYNCLINK_GENERIC_HDLC
3940 hdlcdev_exit(info);
3941#endif
3942 free_dma_bufs(info);
3943 free_tmp_rx_buf(info);
3944 if ( info->port_num == 0 ) {
3945 if (info->sca_base)
3946 write_reg(info, LPR, 1);
3947 release_resources(info);
3948 }
3949 tmp = info;
3950 info = info->next_device;
3951 tty_port_destroy(&tmp->port);
3952 kfree(tmp);
3953 }
3954
3955 pci_unregister_driver(&synclinkmp_pci_driver);
3956}
3957
3958
3959
3960
3961static int __init synclinkmp_init(void)
3962{
3963 int rc;
3964
3965 if (break_on_load) {
3966 synclinkmp_get_text_ptr();
3967 BREAKPOINT();
3968 }
3969
3970 printk("%s %s\n", driver_name, driver_version);
3971
3972 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3973 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3974 return rc;
3975 }
3976
3977 serial_driver = alloc_tty_driver(128);
3978 if (!serial_driver) {
3979 rc = -ENOMEM;
3980 goto error;
3981 }
3982
3983
3984
3985 serial_driver->driver_name = "synclinkmp";
3986 serial_driver->name = "ttySLM";
3987 serial_driver->major = ttymajor;
3988 serial_driver->minor_start = 64;
3989 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3990 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3991 serial_driver->init_termios = tty_std_termios;
3992 serial_driver->init_termios.c_cflag =
3993 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3994 serial_driver->init_termios.c_ispeed = 9600;
3995 serial_driver->init_termios.c_ospeed = 9600;
3996 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3997 tty_set_operations(serial_driver, &ops);
3998 if ((rc = tty_register_driver(serial_driver)) < 0) {
3999 printk("%s(%d):Couldn't register serial driver\n",
4000 __FILE__,__LINE__);
4001 put_tty_driver(serial_driver);
4002 serial_driver = NULL;
4003 goto error;
4004 }
4005
4006 printk("%s %s, tty major#%d\n",
4007 driver_name, driver_version,
4008 serial_driver->major);
4009
4010 return 0;
4011
4012error:
4013 synclinkmp_cleanup();
4014 return rc;
4015}
4016
4017static void __exit synclinkmp_exit(void)
4018{
4019 synclinkmp_cleanup();
4020}
4021
4022module_init(synclinkmp_init);
4023module_exit(synclinkmp_exit);
4024
4025
4026
4027
4028
4029static void enable_loopback(SLMP_INFO *info, int enable)
4030{
4031 if (enable) {
4032
4033
4034
4035 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4036
4037
4038 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4039 write_control_reg(info);
4040
4041
4042
4043
4044
4045
4046 write_reg(info, RXS, 0x40);
4047 write_reg(info, TXS, 0x40);
4048
4049 } else {
4050
4051
4052
4053 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4054
4055
4056
4057
4058
4059
4060 write_reg(info, RXS, 0x00);
4061 write_reg(info, TXS, 0x00);
4062 }
4063
4064
4065 if (info->params.clock_speed)
4066 set_rate(info, info->params.clock_speed);
4067 else
4068 set_rate(info, 3686400);
4069}
4070
4071
4072
4073
4074
4075
4076static void set_rate( SLMP_INFO *info, u32 data_rate )
4077{
4078 u32 TMCValue;
4079 unsigned char BRValue;
4080 u32 Divisor=0;
4081
4082
4083
4084 if (data_rate != 0) {
4085 Divisor = 14745600/data_rate;
4086 if (!Divisor)
4087 Divisor = 1;
4088
4089 TMCValue = Divisor;
4090
4091 BRValue = 0;
4092 if (TMCValue != 1 && TMCValue != 2) {
4093
4094
4095
4096
4097 BRValue = 1;
4098 TMCValue >>= 1;
4099 }
4100
4101
4102
4103
4104 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4105 TMCValue >>= 1;
4106
4107 write_reg(info, TXS,
4108 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4109 write_reg(info, RXS,
4110 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4111 write_reg(info, TMC, (unsigned char)TMCValue);
4112 }
4113 else {
4114 write_reg(info, TXS,0);
4115 write_reg(info, RXS,0);
4116 write_reg(info, TMC, 0);
4117 }
4118}
4119
4120
4121
4122static void rx_stop(SLMP_INFO *info)
4123{
4124 if (debug_level >= DEBUG_LEVEL_ISR)
4125 printk("%s(%d):%s rx_stop()\n",
4126 __FILE__,__LINE__, info->device_name );
4127
4128 write_reg(info, CMD, RXRESET);
4129
4130 info->ie0_value &= ~RXRDYE;
4131 write_reg(info, IE0, info->ie0_value);
4132
4133 write_reg(info, RXDMA + DSR, 0);
4134 write_reg(info, RXDMA + DCMD, SWABORT);
4135 write_reg(info, RXDMA + DIR, 0);
4136
4137 info->rx_enabled = false;
4138 info->rx_overflow = false;
4139}
4140
4141
4142
4143static void rx_start(SLMP_INFO *info)
4144{
4145 int i;
4146
4147 if (debug_level >= DEBUG_LEVEL_ISR)
4148 printk("%s(%d):%s rx_start()\n",
4149 __FILE__,__LINE__, info->device_name );
4150
4151 write_reg(info, CMD, RXRESET);
4152
4153 if ( info->params.mode == MGSL_MODE_HDLC ) {
4154
4155 info->ie0_value &= ~RXRDYE;
4156 write_reg(info, IE0, info->ie0_value);
4157
4158
4159 write_reg(info, RXDMA + DSR, 0);
4160 write_reg(info, RXDMA + DCMD, SWABORT);
4161
4162 for (i = 0; i < info->rx_buf_count; i++) {
4163 info->rx_buf_list[i].status = 0xff;
4164
4165
4166
4167 if (!(i % 4))
4168 read_status_reg(info);
4169 }
4170 info->current_rx_buf = 0;
4171
4172
4173 write_reg16(info, RXDMA + CDA,
4174 info->rx_buf_list_ex[0].phys_entry);
4175
4176
4177 write_reg16(info, RXDMA + EDA,
4178 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4179
4180
4181 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4182
4183 write_reg(info, RXDMA + DIR, 0x60);
4184 write_reg(info, RXDMA + DSR, 0xf2);
4185 } else {
4186
4187 info->ie0_value |= RXRDYE;
4188 write_reg(info, IE0, info->ie0_value);
4189 }
4190
4191 write_reg(info, CMD, RXENABLE);
4192
4193 info->rx_overflow = false;
4194 info->rx_enabled = true;
4195}
4196
4197
4198
4199
4200static void tx_start(SLMP_INFO *info)
4201{
4202 if (debug_level >= DEBUG_LEVEL_ISR)
4203 printk("%s(%d):%s tx_start() tx_count=%d\n",
4204 __FILE__,__LINE__, info->device_name,info->tx_count );
4205
4206 if (!info->tx_enabled ) {
4207 write_reg(info, CMD, TXRESET);
4208 write_reg(info, CMD, TXENABLE);
4209 info->tx_enabled = true;
4210 }
4211
4212 if ( info->tx_count ) {
4213
4214
4215
4216
4217
4218 info->drop_rts_on_tx_done = false;
4219
4220 if (info->params.mode != MGSL_MODE_ASYNC) {
4221
4222 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4223 get_signals( info );
4224 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4225 info->serial_signals |= SerialSignal_RTS;
4226 set_signals( info );
4227 info->drop_rts_on_tx_done = true;
4228 }
4229 }
4230
4231 write_reg16(info, TRC0,
4232 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4233
4234 write_reg(info, TXDMA + DSR, 0);
4235 write_reg(info, TXDMA + DCMD, SWABORT);
4236
4237
4238 write_reg16(info, TXDMA + CDA,
4239 info->tx_buf_list_ex[0].phys_entry);
4240
4241
4242 write_reg16(info, TXDMA + EDA,
4243 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4244
4245
4246 info->ie1_value &= ~IDLE;
4247 info->ie1_value |= UDRN;
4248 write_reg(info, IE1, info->ie1_value);
4249 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4250
4251 write_reg(info, TXDMA + DIR, 0x40);
4252 write_reg(info, TXDMA + DSR, 0xf2);
4253
4254 mod_timer(&info->tx_timer, jiffies +
4255 msecs_to_jiffies(5000));
4256 }
4257 else {
4258 tx_load_fifo(info);
4259
4260 info->ie0_value |= TXRDYE;
4261 write_reg(info, IE0, info->ie0_value);
4262 }
4263
4264 info->tx_active = true;
4265 }
4266}
4267
4268
4269
4270static void tx_stop( SLMP_INFO *info )
4271{
4272 if (debug_level >= DEBUG_LEVEL_ISR)
4273 printk("%s(%d):%s tx_stop()\n",
4274 __FILE__,__LINE__, info->device_name );
4275
4276 del_timer(&info->tx_timer);
4277
4278 write_reg(info, TXDMA + DSR, 0);
4279 write_reg(info, TXDMA + DCMD, SWABORT);
4280
4281 write_reg(info, CMD, TXRESET);
4282
4283 info->ie1_value &= ~(UDRN + IDLE);
4284 write_reg(info, IE1, info->ie1_value);
4285 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4286
4287 info->ie0_value &= ~TXRDYE;
4288 write_reg(info, IE0, info->ie0_value);
4289
4290 info->tx_enabled = false;
4291 info->tx_active = false;
4292}
4293
4294
4295
4296
4297static void tx_load_fifo(SLMP_INFO *info)
4298{
4299 u8 TwoBytes[2];
4300
4301
4302
4303 if ( !info->tx_count && !info->x_char )
4304 return;
4305
4306
4307
4308 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4309
4310
4311
4312
4313 if ( (info->tx_count > 1) && !info->x_char ) {
4314
4315 TwoBytes[0] = info->tx_buf[info->tx_get++];
4316 if (info->tx_get >= info->max_frame_size)
4317 info->tx_get -= info->max_frame_size;
4318 TwoBytes[1] = info->tx_buf[info->tx_get++];
4319 if (info->tx_get >= info->max_frame_size)
4320 info->tx_get -= info->max_frame_size;
4321
4322 write_reg16(info, TRB, *((u16 *)TwoBytes));
4323
4324 info->tx_count -= 2;
4325 info->icount.tx += 2;
4326 } else {
4327
4328
4329 if (info->x_char) {
4330
4331 write_reg(info, TRB, info->x_char);
4332 info->x_char = 0;
4333 } else {
4334 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4335 if (info->tx_get >= info->max_frame_size)
4336 info->tx_get -= info->max_frame_size;
4337 info->tx_count--;
4338 }
4339 info->icount.tx++;
4340 }
4341 }
4342}
4343
4344
4345
4346static void reset_port(SLMP_INFO *info)
4347{
4348 if (info->sca_base) {
4349
4350 tx_stop(info);
4351 rx_stop(info);
4352
4353 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4354 set_signals(info);
4355
4356
4357 info->ie0_value = 0;
4358 info->ie1_value = 0;
4359 info->ie2_value = 0;
4360 write_reg(info, IE0, info->ie0_value);
4361 write_reg(info, IE1, info->ie1_value);
4362 write_reg(info, IE2, info->ie2_value);
4363
4364 write_reg(info, CMD, CHRESET);
4365 }
4366}
4367
4368
4369
4370static void reset_adapter(SLMP_INFO *info)
4371{
4372 int i;
4373
4374 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4375 if (info->port_array[i])
4376 reset_port(info->port_array[i]);
4377 }
4378}
4379
4380
4381
4382static void async_mode(SLMP_INFO *info)
4383{
4384
4385 unsigned char RegValue;
4386
4387 tx_stop(info);
4388 rx_stop(info);
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400 RegValue = 0x00;
4401 if (info->params.stop_bits != 1)
4402 RegValue |= BIT1;
4403 write_reg(info, MD0, RegValue);
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414 RegValue = 0x40;
4415 switch (info->params.data_bits) {
4416 case 7: RegValue |= BIT4 + BIT2; break;
4417 case 6: RegValue |= BIT5 + BIT3; break;
4418 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4419 }
4420 if (info->params.parity != ASYNC_PARITY_NONE) {
4421 RegValue |= BIT1;
4422 if (info->params.parity == ASYNC_PARITY_ODD)
4423 RegValue |= BIT0;
4424 }
4425 write_reg(info, MD1, RegValue);
4426
4427
4428
4429
4430
4431
4432
4433
4434 RegValue = 0x00;
4435 if (info->params.loopback)
4436 RegValue |= (BIT1 + BIT0);
4437 write_reg(info, MD2, RegValue);
4438
4439
4440
4441
4442
4443
4444
4445 RegValue=BIT6;
4446 write_reg(info, RXS, RegValue);
4447
4448
4449
4450
4451
4452
4453
4454 RegValue=BIT6;
4455 write_reg(info, TXS, RegValue);
4456
4457
4458
4459
4460
4461 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4462 write_control_reg(info);
4463
4464 tx_set_idle(info);
4465
4466
4467
4468
4469
4470
4471 write_reg(info, RRC, 0x00);
4472
4473
4474
4475
4476
4477
4478 write_reg(info, TRC0, 0x10);
4479
4480
4481
4482
4483
4484
4485 write_reg(info, TRC1, 0x1e);
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499 RegValue = 0x10;
4500 if (!(info->serial_signals & SerialSignal_RTS))
4501 RegValue |= 0x01;
4502 write_reg(info, CTL, RegValue);
4503
4504
4505 info->ie0_value |= TXINTE + RXINTE;
4506 write_reg(info, IE0, info->ie0_value);
4507
4508
4509 info->ie1_value = BRKD;
4510 write_reg(info, IE1, info->ie1_value);
4511
4512
4513 info->ie2_value = OVRN;
4514 write_reg(info, IE2, info->ie2_value);
4515
4516 set_rate( info, info->params.data_rate * 16 );
4517}
4518
4519
4520
4521static void hdlc_mode(SLMP_INFO *info)
4522{
4523 unsigned char RegValue;
4524 u32 DpllDivisor;
4525
4526
4527
4528
4529
4530 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4531
4532
4533 write_reg(info, TXDMA + DIR, 0);
4534 write_reg(info, RXDMA + DIR, 0);
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547 RegValue = 0x81;
4548 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4549 RegValue |= BIT4;
4550 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4551 RegValue |= BIT4;
4552 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4553 RegValue |= BIT2 + BIT1;
4554 write_reg(info, MD0, RegValue);
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565 RegValue = 0x00;
4566 write_reg(info, MD1, RegValue);
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578 RegValue = 0x00;
4579 switch(info->params.encoding) {
4580 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4581 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break;
4582 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break;
4583 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;
4584#if 0
4585 case HDLC_ENCODING_NRZB:
4586 case HDLC_ENCODING_NRZI_MARK:
4587 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4588#endif
4589 }
4590 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4591 DpllDivisor = 16;
4592 RegValue |= BIT3;
4593 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4594 DpllDivisor = 8;
4595 } else {
4596 DpllDivisor = 32;
4597 RegValue |= BIT4;
4598 }
4599 write_reg(info, MD2, RegValue);
4600
4601
4602
4603
4604
4605
4606
4607
4608 RegValue=0;
4609 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4610 RegValue |= BIT6;
4611 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4612 RegValue |= BIT6 + BIT5;
4613 write_reg(info, RXS, RegValue);
4614
4615
4616
4617
4618
4619
4620
4621 RegValue=0;
4622 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4623 RegValue |= BIT6;
4624 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4625 RegValue |= BIT6 + BIT5;
4626 write_reg(info, TXS, RegValue);
4627
4628 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4629 set_rate(info, info->params.clock_speed * DpllDivisor);
4630 else
4631 set_rate(info, info->params.clock_speed);
4632
4633
4634
4635
4636
4637 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4638 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4639 else
4640 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4641 write_control_reg(info);
4642
4643
4644
4645
4646
4647
4648 write_reg(info, RRC, rx_active_fifo_level);
4649
4650
4651
4652
4653
4654
4655 write_reg(info, TRC0, tx_active_fifo_level);
4656
4657
4658
4659
4660
4661
4662 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675 write_reg(info, TXDMA + DMR, 0x14);
4676 write_reg(info, RXDMA + DMR, 0x14);
4677
4678
4679 write_reg(info, RXDMA + CPB,
4680 (unsigned char)(info->buffer_list_phys >> 16));
4681
4682
4683 write_reg(info, TXDMA + CPB,
4684 (unsigned char)(info->buffer_list_phys >> 16));
4685
4686
4687
4688
4689 info->ie0_value |= TXINTE + RXINTE;
4690 write_reg(info, IE0, info->ie0_value);
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704 RegValue = 0x10;
4705 if (!(info->serial_signals & SerialSignal_RTS))
4706 RegValue |= 0x01;
4707 write_reg(info, CTL, RegValue);
4708
4709
4710
4711 tx_set_idle(info);
4712 tx_stop(info);
4713 rx_stop(info);
4714
4715 set_rate(info, info->params.clock_speed);
4716
4717 if (info->params.loopback)
4718 enable_loopback(info,1);
4719}
4720
4721
4722
4723static void tx_set_idle(SLMP_INFO *info)
4724{
4725 unsigned char RegValue = 0xff;
4726
4727
4728 switch(info->idle_mode) {
4729 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4730 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4731 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4732 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4733 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4734 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4735 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4736 }
4737
4738 write_reg(info, IDL, RegValue);
4739}
4740
4741
4742
4743static void get_signals(SLMP_INFO *info)
4744{
4745 u16 status = read_reg(info, SR3);
4746 u16 gpstatus = read_status_reg(info);
4747 u16 testbit;
4748
4749
4750 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4751
4752
4753
4754 if (!(status & BIT3))
4755 info->serial_signals |= SerialSignal_CTS;
4756
4757 if ( !(status & BIT2))
4758 info->serial_signals |= SerialSignal_DCD;
4759
4760 testbit = BIT1 << (info->port_num * 2);
4761 if (!(gpstatus & testbit))
4762 info->serial_signals |= SerialSignal_RI;
4763
4764 testbit = BIT0 << (info->port_num * 2);
4765 if (!(gpstatus & testbit))
4766 info->serial_signals |= SerialSignal_DSR;
4767}
4768
4769
4770
4771
4772static void set_signals(SLMP_INFO *info)
4773{
4774 unsigned char RegValue;
4775 u16 EnableBit;
4776
4777 RegValue = read_reg(info, CTL);
4778 if (info->serial_signals & SerialSignal_RTS)
4779 RegValue &= ~BIT0;
4780 else
4781 RegValue |= BIT0;
4782 write_reg(info, CTL, RegValue);
4783
4784
4785 EnableBit = BIT1 << (info->port_num*2);
4786 if (info->serial_signals & SerialSignal_DTR)
4787 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4788 else
4789 info->port_array[0]->ctrlreg_value |= EnableBit;
4790 write_control_reg(info);
4791}
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801static void rx_reset_buffers(SLMP_INFO *info)
4802{
4803 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4804}
4805
4806
4807
4808
4809
4810
4811
4812static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4813{
4814 bool done = false;
4815
4816 while(!done) {
4817
4818 info->rx_buf_list[first].status = 0xff;
4819
4820 if (first == last) {
4821 done = true;
4822
4823 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4824 }
4825
4826 first++;
4827 if (first == info->rx_buf_count)
4828 first = 0;
4829 }
4830
4831
4832 info->current_rx_buf = first;
4833}
4834
4835
4836
4837
4838
4839
4840static bool rx_get_frame(SLMP_INFO *info)
4841{
4842 unsigned int StartIndex, EndIndex;
4843 unsigned short status;
4844 unsigned int framesize = 0;
4845 bool ReturnCode = false;
4846 unsigned long flags;
4847 struct tty_struct *tty = info->port.tty;
4848 unsigned char addr_field = 0xff;
4849 SCADESC *desc;
4850 SCADESC_EX *desc_ex;
4851
4852CheckAgain:
4853
4854 framesize = 0;
4855 addr_field = 0xff;
4856
4857
4858
4859
4860
4861
4862
4863 StartIndex = EndIndex = info->current_rx_buf;
4864
4865 for ( ;; ) {
4866 desc = &info->rx_buf_list[EndIndex];
4867 desc_ex = &info->rx_buf_list_ex[EndIndex];
4868
4869 if (desc->status == 0xff)
4870 goto Cleanup;
4871
4872 if (framesize == 0 && info->params.addr_filter != 0xff)
4873 addr_field = desc_ex->virt_addr[0];
4874
4875 framesize += desc->length;
4876
4877
4878 if (desc->status)
4879 break;
4880
4881 EndIndex++;
4882 if (EndIndex == info->rx_buf_count)
4883 EndIndex = 0;
4884
4885 if (EndIndex == info->current_rx_buf) {
4886
4887
4888 if ( info->rx_enabled ){
4889 spin_lock_irqsave(&info->lock,flags);
4890 rx_start(info);
4891 spin_unlock_irqrestore(&info->lock,flags);
4892 }
4893 goto Cleanup;
4894 }
4895
4896 }
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910 status = desc->status;
4911
4912
4913
4914 if (info->params.crc_type == HDLC_CRC_NONE)
4915 status &= ~BIT2;
4916
4917 if (framesize == 0 ||
4918 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4919
4920
4921
4922 rx_free_frame_buffers(info, StartIndex, EndIndex);
4923 goto CheckAgain;
4924 }
4925
4926 if (framesize < 2)
4927 status |= BIT6;
4928
4929 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4930
4931
4932
4933 if (status & BIT6)
4934 info->icount.rxshort++;
4935 else if (status & BIT5)
4936 info->icount.rxabort++;
4937 else if (status & BIT3)
4938 info->icount.rxover++;
4939 else
4940 info->icount.rxcrc++;
4941
4942 framesize = 0;
4943#if SYNCLINK_GENERIC_HDLC
4944 {
4945 info->netdev->stats.rx_errors++;
4946 info->netdev->stats.rx_frame_errors++;
4947 }
4948#endif
4949 }
4950
4951 if ( debug_level >= DEBUG_LEVEL_BH )
4952 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4953 __FILE__,__LINE__,info->device_name,status,framesize);
4954
4955 if ( debug_level >= DEBUG_LEVEL_DATA )
4956 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4957 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4958
4959 if (framesize) {
4960 if (framesize > info->max_frame_size)
4961 info->icount.rxlong++;
4962 else {
4963
4964 int copy_count = framesize;
4965 int index = StartIndex;
4966 unsigned char *ptmp = info->tmp_rx_buf;
4967 info->tmp_rx_buf_count = framesize;
4968
4969 info->icount.rxok++;
4970
4971 while(copy_count) {
4972 int partial_count = min(copy_count,SCABUFSIZE);
4973 memcpy( ptmp,
4974 info->rx_buf_list_ex[index].virt_addr,
4975 partial_count );
4976 ptmp += partial_count;
4977 copy_count -= partial_count;
4978
4979 if ( ++index == info->rx_buf_count )
4980 index = 0;
4981 }
4982
4983#if SYNCLINK_GENERIC_HDLC
4984 if (info->netcount)
4985 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4986 else
4987#endif
4988 ldisc_receive_buf(tty,info->tmp_rx_buf,
4989 info->flag_buf, framesize);
4990 }
4991 }
4992
4993 rx_free_frame_buffers( info, StartIndex, EndIndex );
4994
4995 ReturnCode = true;
4996
4997Cleanup:
4998 if ( info->rx_enabled && info->rx_overflow ) {
4999
5000
5001
5002 if (info->rx_buf_list[EndIndex].status == 0xff) {
5003 spin_lock_irqsave(&info->lock,flags);
5004 rx_start(info);
5005 spin_unlock_irqrestore(&info->lock,flags);
5006 }
5007 }
5008
5009 return ReturnCode;
5010}
5011
5012
5013
5014static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5015{
5016 unsigned short copy_count;
5017 unsigned int i = 0;
5018 SCADESC *desc;
5019 SCADESC_EX *desc_ex;
5020
5021 if ( debug_level >= DEBUG_LEVEL_DATA )
5022 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5023
5024
5025
5026
5027 for(i=0;;)
5028 {
5029 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5030
5031 desc = &info->tx_buf_list[i];
5032 desc_ex = &info->tx_buf_list_ex[i];
5033
5034 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5035
5036 desc->length = copy_count;
5037 desc->status = 0;
5038
5039 buf += copy_count;
5040 count -= copy_count;
5041
5042 if (!count)
5043 break;
5044
5045 i++;
5046 if (i >= info->tx_buf_count)
5047 i = 0;
5048 }
5049
5050 info->tx_buf_list[i].status = 0x81;
5051 info->last_tx_buf = ++i;
5052}
5053
5054static bool register_test(SLMP_INFO *info)
5055{
5056 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5057 static unsigned int count = ARRAY_SIZE(testval);
5058 unsigned int i;
5059 bool rc = true;
5060 unsigned long flags;
5061
5062 spin_lock_irqsave(&info->lock,flags);
5063 reset_port(info);
5064
5065
5066 info->init_error = DiagStatus_AddressFailure;
5067
5068
5069
5070
5071 for (i = 0 ; i < count ; i++) {
5072 write_reg(info, TMC, testval[i]);
5073 write_reg(info, IDL, testval[(i+1)%count]);
5074 write_reg(info, SA0, testval[(i+2)%count]);
5075 write_reg(info, SA1, testval[(i+3)%count]);
5076
5077 if ( (read_reg(info, TMC) != testval[i]) ||
5078 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5079 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5080 (read_reg(info, SA1) != testval[(i+3)%count]) )
5081 {
5082 rc = false;
5083 break;
5084 }
5085 }
5086
5087 reset_port(info);
5088 spin_unlock_irqrestore(&info->lock,flags);
5089
5090 return rc;
5091}
5092
5093static bool irq_test(SLMP_INFO *info)
5094{
5095 unsigned long timeout;
5096 unsigned long flags;
5097
5098 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5099
5100 spin_lock_irqsave(&info->lock,flags);
5101 reset_port(info);
5102
5103
5104 info->init_error = DiagStatus_IrqFailure;
5105 info->irq_occurred = false;
5106
5107
5108
5109
5110 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5111
5112 write_reg(info, (unsigned char)(timer + TEPR), 0);
5113 write_reg16(info, (unsigned char)(timer + TCONR), 1);
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5127
5128 spin_unlock_irqrestore(&info->lock,flags);
5129
5130 timeout=100;
5131 while( timeout-- && !info->irq_occurred ) {
5132 msleep_interruptible(10);
5133 }
5134
5135 spin_lock_irqsave(&info->lock,flags);
5136 reset_port(info);
5137 spin_unlock_irqrestore(&info->lock,flags);
5138
5139 return info->irq_occurred;
5140}
5141
5142
5143
5144static bool sca_init(SLMP_INFO *info)
5145{
5146
5147 write_reg(info, PABR0, 0);
5148 write_reg(info, PABR1, 0);
5149 write_reg(info, WCRL, 0);
5150 write_reg(info, WCRM, 0);
5151 write_reg(info, WCRH, 0);
5152
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162 write_reg(info, DPCR, dma_priority);
5163
5164
5165 write_reg(info, DMER, 0x80);
5166
5167
5168 write_reg(info, IER0, 0xff);
5169 write_reg(info, IER1, 0xff);
5170 write_reg(info, IER2, 0xf0);
5171
5172
5173
5174
5175
5176
5177
5178 write_reg(info, ITCR, 0);
5179
5180 return true;
5181}
5182
5183
5184
5185static bool init_adapter(SLMP_INFO *info)
5186{
5187 int i;
5188
5189
5190 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5191 u32 readval;
5192
5193 info->misc_ctrl_value |= BIT30;
5194 *MiscCtrl = info->misc_ctrl_value;
5195
5196
5197
5198
5199
5200
5201 for(i=0;i<10;i++)
5202 readval = *MiscCtrl;
5203
5204 info->misc_ctrl_value &= ~BIT30;
5205 *MiscCtrl = info->misc_ctrl_value;
5206
5207
5208 info->ctrlreg_value = 0xaa;
5209 write_control_reg(info);
5210
5211 {
5212 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5213 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5214
5215 switch(read_ahead_count)
5216 {
5217 case 16:
5218 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5219 break;
5220 case 8:
5221 lcr1_brdr_value |= BIT5 + BIT4;
5222 break;
5223 case 4:
5224 lcr1_brdr_value |= BIT5 + BIT3;
5225 break;
5226 case 0:
5227 lcr1_brdr_value |= BIT5;
5228 break;
5229 }
5230
5231 *LCR1BRDR = lcr1_brdr_value;
5232 *MiscCtrl = misc_ctrl_value;
5233 }
5234
5235 sca_init(info->port_array[0]);
5236 sca_init(info->port_array[2]);
5237
5238 return true;
5239}
5240
5241
5242
5243
5244static bool loopback_test(SLMP_INFO *info)
5245{
5246#define TESTFRAMESIZE 20
5247
5248 unsigned long timeout;
5249 u16 count = TESTFRAMESIZE;
5250 unsigned char buf[TESTFRAMESIZE];
5251 bool rc = false;
5252 unsigned long flags;
5253
5254 struct tty_struct *oldtty = info->port.tty;
5255 u32 speed = info->params.clock_speed;
5256
5257 info->params.clock_speed = 3686400;
5258 info->port.tty = NULL;
5259
5260
5261 info->init_error = DiagStatus_DmaFailure;
5262
5263
5264 for (count = 0; count < TESTFRAMESIZE;++count)
5265 buf[count] = (unsigned char)count;
5266
5267 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5268
5269
5270 spin_lock_irqsave(&info->lock,flags);
5271 hdlc_mode(info);
5272 enable_loopback(info,1);
5273 rx_start(info);
5274 info->tx_count = count;
5275 tx_load_dma_buffer(info,buf,count);
5276 tx_start(info);
5277 spin_unlock_irqrestore(&info->lock,flags);
5278
5279
5280
5281 for ( timeout = 100; timeout; --timeout ) {
5282 msleep_interruptible(10);
5283
5284 if (rx_get_frame(info)) {
5285 rc = true;
5286 break;
5287 }
5288 }
5289
5290
5291 if (rc &&
5292 ( info->tmp_rx_buf_count != count ||
5293 memcmp(buf, info->tmp_rx_buf,count))) {
5294 rc = false;
5295 }
5296
5297 spin_lock_irqsave(&info->lock,flags);
5298 reset_adapter(info);
5299 spin_unlock_irqrestore(&info->lock,flags);
5300
5301 info->params.clock_speed = speed;
5302 info->port.tty = oldtty;
5303
5304 return rc;
5305}
5306
5307
5308
5309static int adapter_test( SLMP_INFO *info )
5310{
5311 unsigned long flags;
5312 if ( debug_level >= DEBUG_LEVEL_INFO )
5313 printk( "%s(%d):Testing device %s\n",
5314 __FILE__,__LINE__,info->device_name );
5315
5316 spin_lock_irqsave(&info->lock,flags);
5317 init_adapter(info);
5318 spin_unlock_irqrestore(&info->lock,flags);
5319
5320 info->port_array[0]->port_count = 0;
5321
5322 if ( register_test(info->port_array[0]) &&
5323 register_test(info->port_array[1])) {
5324
5325 info->port_array[0]->port_count = 2;
5326
5327 if ( register_test(info->port_array[2]) &&
5328 register_test(info->port_array[3]) )
5329 info->port_array[0]->port_count += 2;
5330 }
5331 else {
5332 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5333 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5334 return -ENODEV;
5335 }
5336
5337 if ( !irq_test(info->port_array[0]) ||
5338 !irq_test(info->port_array[1]) ||
5339 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5340 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5341 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5342 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5343 return -ENODEV;
5344 }
5345
5346 if (!loopback_test(info->port_array[0]) ||
5347 !loopback_test(info->port_array[1]) ||
5348 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5349 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5350 printk( "%s(%d):DMA test failure for device %s\n",
5351 __FILE__,__LINE__,info->device_name);
5352 return -ENODEV;
5353 }
5354
5355 if ( debug_level >= DEBUG_LEVEL_INFO )
5356 printk( "%s(%d):device %s passed diagnostics\n",
5357 __FILE__,__LINE__,info->device_name );
5358
5359 info->port_array[0]->init_error = 0;
5360 info->port_array[1]->init_error = 0;
5361 if ( info->port_count > 2 ) {
5362 info->port_array[2]->init_error = 0;
5363 info->port_array[3]->init_error = 0;
5364 }
5365
5366 return 0;
5367}
5368
5369
5370
5371static bool memory_test(SLMP_INFO *info)
5372{
5373 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5374 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5375 unsigned long count = ARRAY_SIZE(testval);
5376 unsigned long i;
5377 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5378 unsigned long * addr = (unsigned long *)info->memory_base;
5379
5380
5381
5382 for ( i = 0 ; i < count ; i++ ) {
5383 *addr = testval[i];
5384 if ( *addr != testval[i] )
5385 return false;
5386 }
5387
5388
5389
5390
5391 for ( i = 0 ; i < limit ; i++ ) {
5392 *addr = i * 4;
5393 addr++;
5394 }
5395
5396 addr = (unsigned long *)info->memory_base;
5397
5398 for ( i = 0 ; i < limit ; i++ ) {
5399 if ( *addr != i * 4 )
5400 return false;
5401 addr++;
5402 }
5403
5404 memset( info->memory_base, 0, SCA_MEM_SIZE );
5405 return true;
5406}
5407
5408
5409
5410
5411
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422
5423static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5424{
5425
5426
5427
5428 unsigned short interval = count / sca_pci_load_interval;
5429 unsigned short i;
5430
5431 for ( i = 0 ; i < interval ; i++ )
5432 {
5433 memcpy(dest, src, sca_pci_load_interval);
5434 read_status_reg(info);
5435 dest += sca_pci_load_interval;
5436 src += sca_pci_load_interval;
5437 }
5438
5439 memcpy(dest, src, count % sca_pci_load_interval);
5440}
5441
5442static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5443{
5444 int i;
5445 int linecount;
5446 if (xmit)
5447 printk("%s tx data:\n",info->device_name);
5448 else
5449 printk("%s rx data:\n",info->device_name);
5450
5451 while(count) {
5452 if (count > 16)
5453 linecount = 16;
5454 else
5455 linecount = count;
5456
5457 for(i=0;i<linecount;i++)
5458 printk("%02X ",(unsigned char)data[i]);
5459 for(;i<17;i++)
5460 printk(" ");
5461 for(i=0;i<linecount;i++) {
5462 if (data[i]>=040 && data[i]<=0176)
5463 printk("%c",data[i]);
5464 else
5465 printk(".");
5466 }
5467 printk("\n");
5468
5469 data += linecount;
5470 count -= linecount;
5471 }
5472}
5473
5474
5475
5476
5477static void tx_timeout(unsigned long context)
5478{
5479 SLMP_INFO *info = (SLMP_INFO*)context;
5480 unsigned long flags;
5481
5482 if ( debug_level >= DEBUG_LEVEL_INFO )
5483 printk( "%s(%d):%s tx_timeout()\n",
5484 __FILE__,__LINE__,info->device_name);
5485 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5486 info->icount.txtimeout++;
5487 }
5488 spin_lock_irqsave(&info->lock,flags);
5489 info->tx_active = false;
5490 info->tx_count = info->tx_put = info->tx_get = 0;
5491
5492 spin_unlock_irqrestore(&info->lock,flags);
5493
5494#if SYNCLINK_GENERIC_HDLC
5495 if (info->netcount)
5496 hdlcdev_tx_done(info);
5497 else
5498#endif
5499 bh_transmit(info);
5500}
5501
5502
5503
5504static void status_timeout(unsigned long context)
5505{
5506 u16 status = 0;
5507 SLMP_INFO *info = (SLMP_INFO*)context;
5508 unsigned long flags;
5509 unsigned char delta;
5510
5511
5512 spin_lock_irqsave(&info->lock,flags);
5513 get_signals(info);
5514 spin_unlock_irqrestore(&info->lock,flags);
5515
5516
5517
5518 delta = info->old_signals ^ info->serial_signals;
5519 info->old_signals = info->serial_signals;
5520
5521 if (delta & SerialSignal_DSR)
5522 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5523
5524 if (delta & SerialSignal_RI)
5525 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5526
5527 if (delta & SerialSignal_DCD)
5528 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5529
5530 if (delta & SerialSignal_CTS)
5531 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5532
5533 if (status)
5534 isr_io_pin(info,status);
5535
5536 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5537}
5538
5539
5540
5541
5542
5543#define CALC_REGADDR() \
5544 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5545 if (info->port_num > 1) \
5546 RegAddr += 256; \
5547 if ( info->port_num & 1) { \
5548 if (Addr > 0x7f) \
5549 RegAddr += 0x40; \
5550 else if (Addr > 0x1f && Addr < 0x60) \
5551 RegAddr += 0x20; \
5552 }
5553
5554
5555static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5556{
5557 CALC_REGADDR();
5558 return *RegAddr;
5559}
5560static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5561{
5562 CALC_REGADDR();
5563 *RegAddr = Value;
5564}
5565
5566static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5567{
5568 CALC_REGADDR();
5569 return *((u16 *)RegAddr);
5570}
5571
5572static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5573{
5574 CALC_REGADDR();
5575 *((u16 *)RegAddr) = Value;
5576}
5577
5578static unsigned char read_status_reg(SLMP_INFO * info)
5579{
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5581 return *RegAddr;
5582}
5583
5584static void write_control_reg(SLMP_INFO * info)
5585{
5586 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5587 *RegAddr = info->port_array[0]->ctrlreg_value;
5588}
5589
5590
5591static int synclinkmp_init_one (struct pci_dev *dev,
5592 const struct pci_device_id *ent)
5593{
5594 if (pci_enable_device(dev)) {
5595 printk("error enabling pci device %p\n", dev);
5596 return -EIO;
5597 }
5598 device_init( ++synclinkmp_adapter_count, dev );
5599 return 0;
5600}
5601
5602static void synclinkmp_remove_one (struct pci_dev *dev)
5603{
5604}
5605