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8#ifndef __MATROXFB_H__
9#define __MATROXFB_H__
10
11
12#undef MATROXFB_DEBUG
13
14
15
16#undef MATROXFB_DEBUG_HEAVY
17
18
19
20#undef MATROXFB_DEBUG_LOOP
21
22
23#undef MATROXFB_DEBUG_REG
24
25
26#undef MATROXFB_USE_SPINLOCKS
27
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/string.h>
32#include <linux/mm.h>
33#include <linux/slab.h>
34#include <linux/delay.h>
35#include <linux/fb.h>
36#include <linux/console.h>
37#include <linux/selection.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/timer.h>
41#include <linux/pci.h>
42#include <linux/spinlock.h>
43#include <linux/kd.h>
44
45#include <asm/io.h>
46#include <asm/unaligned.h>
47#ifdef CONFIG_MTRR
48#include <asm/mtrr.h>
49#endif
50
51#if defined(CONFIG_PPC_PMAC)
52#include <asm/prom.h>
53#include <asm/pci-bridge.h>
54#include "../macmodes.h"
55#endif
56
57#ifdef MATROXFB_DEBUG
58
59#define DEBUG
60#define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
61
62#ifdef MATROXFB_DEBUG_HEAVY
63#define DBG_HEAVY(x) DBG(x)
64#else
65#define DBG_HEAVY(x)
66#endif
67
68#ifdef MATROXFB_DEBUG_LOOP
69#define DBG_LOOP(x) DBG(x)
70#else
71#define DBG_LOOP(x)
72#endif
73
74#ifdef MATROXFB_DEBUG_REG
75#define DBG_REG(x) DBG(x)
76#else
77#define DBG_REG(x)
78#endif
79
80#else
81
82#define DBG(x)
83#define DBG_HEAVY(x)
84#define DBG_REG(x)
85#define DBG_LOOP(x)
86
87#endif
88
89#ifdef DEBUG
90#define dprintk(X...) printk(X)
91#else
92#define dprintk(X...)
93#endif
94
95#ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
96#define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
97#endif
98#ifndef PCI_SS_VENDOR_ID_MATROX
99#define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
100#endif
101
102#ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
103#define PCI_SS_ID_MATROX_GENERIC 0xFF00
104#define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
105#define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
106#define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
107#define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
108#define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
109#define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
110#define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
111#define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E
112#define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032
113#endif
114
115#define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
116#define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
117#define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
118
119#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
120
121
122#undef NEED_DAC1064
123#if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
124#define NEED_DAC1064 1
125#endif
126
127typedef struct {
128 void __iomem* vaddr;
129} vaddr_t;
130
131static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
132 return readb(va.vaddr + offs);
133}
134
135static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
136 writeb(value, va.vaddr + offs);
137}
138
139static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
140 writew(value, va.vaddr + offs);
141}
142
143static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
144 return readl(va.vaddr + offs);
145}
146
147static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
148 writel(value, va.vaddr + offs);
149}
150
151static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
152#if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
153
154
155
156
157
158
159
160 iowrite32_rep(va.vaddr, src, len >> 2);
161#else
162 u_int32_t __iomem* addr = va.vaddr;
163
164 if ((unsigned long)src & 3) {
165 while (len >= 4) {
166 fb_writel(get_unaligned((u32 *)src), addr);
167 addr++;
168 len -= 4;
169 src += 4;
170 }
171 } else {
172 while (len >= 4) {
173 fb_writel(*(u32 *)src, addr);
174 addr++;
175 len -= 4;
176 src += 4;
177 }
178 }
179#endif
180}
181
182static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
183 va->vaddr += offs;
184}
185
186static inline void __iomem* vaddr_va(vaddr_t va) {
187 return va.vaddr;
188}
189
190#define MGA_IOREMAP_NORMAL 0
191#define MGA_IOREMAP_NOCACHE 1
192
193#define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
194#define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
195static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
196 if (flags & MGA_IOREMAP_NOCACHE)
197 virt->vaddr = ioremap_nocache(phys, size);
198 else
199 virt->vaddr = ioremap(phys, size);
200 return (virt->vaddr == NULL);
201}
202
203static inline void mga_iounmap(vaddr_t va) {
204 iounmap(va.vaddr);
205}
206
207struct my_timming {
208 unsigned int pixclock;
209 int mnp;
210 unsigned int crtc;
211 unsigned int HDisplay;
212 unsigned int HSyncStart;
213 unsigned int HSyncEnd;
214 unsigned int HTotal;
215 unsigned int VDisplay;
216 unsigned int VSyncStart;
217 unsigned int VSyncEnd;
218 unsigned int VTotal;
219 unsigned int sync;
220 int dblscan;
221 int interlaced;
222 unsigned int delay;
223};
224
225enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
226
227struct matrox_pll_cache {
228 unsigned int valid;
229 struct {
230 unsigned int mnp_key;
231 unsigned int mnp_value;
232 } data[4];
233};
234
235struct matrox_pll_limits {
236 unsigned int vcomin;
237 unsigned int vcomax;
238};
239
240struct matrox_pll_features {
241 unsigned int vco_freq_min;
242 unsigned int ref_freq;
243 unsigned int feed_div_min;
244 unsigned int feed_div_max;
245 unsigned int in_div_min;
246 unsigned int in_div_max;
247 unsigned int post_shift_max;
248};
249
250struct matroxfb_par
251{
252 unsigned int final_bppShift;
253 unsigned int cmap_len;
254 struct {
255 unsigned int bytes;
256 unsigned int pixels;
257 unsigned int chunks;
258 } ydstorg;
259};
260
261struct matrox_fb_info;
262
263struct matrox_DAC1064_features {
264 u_int8_t xvrefctrl;
265 u_int8_t xmiscctrl;
266};
267
268
269struct mavenregs {
270 u_int8_t regs[256];
271 int mode;
272 int vlines;
273 int xtal;
274 int fv;
275
276 u_int16_t htotal;
277 u_int16_t hcorr;
278};
279
280struct matrox_crtc2 {
281 u_int32_t ctl;
282};
283
284struct matrox_hw_state {
285 u_int32_t MXoptionReg;
286 unsigned char DACclk[6];
287 unsigned char DACreg[80];
288 unsigned char MiscOutReg;
289 unsigned char DACpal[768];
290 unsigned char CRTC[25];
291 unsigned char CRTCEXT[9];
292 unsigned char SEQ[5];
293
294 unsigned char GCTL[9];
295
296 unsigned char ATTR[21];
297
298
299 struct mavenregs maven;
300
301 struct matrox_crtc2 crtc2;
302};
303
304struct matrox_accel_data {
305#ifdef CONFIG_FB_MATROX_MILLENIUM
306 unsigned char ramdac_rev;
307#endif
308 u_int32_t m_dwg_rect;
309 u_int32_t m_opmode;
310 u_int32_t m_access;
311 u_int32_t m_pitch;
312};
313
314struct v4l2_queryctrl;
315struct v4l2_control;
316
317struct matrox_altout {
318 const char *name;
319 int (*compute)(void* altout_dev, struct my_timming* input);
320 int (*program)(void* altout_dev);
321 int (*start)(void* altout_dev);
322 int (*verifymode)(void* altout_dev, u_int32_t mode);
323 int (*getqueryctrl)(void* altout_dev,
324 struct v4l2_queryctrl* ctrl);
325 int (*getctrl)(void* altout_dev,
326 struct v4l2_control* ctrl);
327 int (*setctrl)(void* altout_dev,
328 struct v4l2_control* ctrl);
329};
330
331#define MATROXFB_SRC_NONE 0
332#define MATROXFB_SRC_CRTC1 1
333#define MATROXFB_SRC_CRTC2 2
334
335enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
336
337struct matrox_bios {
338 unsigned int bios_valid : 1;
339 unsigned int pins_len;
340 unsigned char pins[128];
341 struct {
342 unsigned char vMaj, vMin, vRev;
343 } version;
344 struct {
345 unsigned char state, tvout;
346 } output;
347};
348
349struct matrox_switch;
350struct matroxfb_driver;
351struct matroxfb_dh_fb_info;
352
353struct matrox_vsync {
354 wait_queue_head_t wait;
355 unsigned int cnt;
356};
357
358struct matrox_fb_info {
359 struct fb_info fbcon;
360
361 struct list_head next_fb;
362
363 int dead;
364 int initialized;
365 unsigned int usecount;
366
367 unsigned int userusecount;
368 unsigned long irq_flags;
369
370 struct matroxfb_par curr;
371 struct matrox_hw_state hw;
372
373 struct matrox_accel_data accel;
374
375 struct pci_dev* pcidev;
376
377 struct {
378 struct matrox_vsync vsync;
379 unsigned int pixclock;
380 int mnp;
381 int panpos;
382 } crtc1;
383 struct {
384 struct matrox_vsync vsync;
385 unsigned int pixclock;
386 int mnp;
387 struct matroxfb_dh_fb_info* info;
388 struct rw_semaphore lock;
389 } crtc2;
390 struct {
391 struct rw_semaphore lock;
392 struct {
393 int brightness, contrast, saturation, hue, gamma;
394 int testout, deflicker;
395 } tvo_params;
396 } altout;
397#define MATROXFB_MAX_OUTPUTS 3
398 struct {
399 unsigned int src;
400 struct matrox_altout* output;
401 void* data;
402 unsigned int mode;
403 unsigned int default_src;
404 } outputs[MATROXFB_MAX_OUTPUTS];
405
406#define MATROXFB_MAX_FB_DRIVERS 5
407 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
408 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
409 unsigned int drivers_count;
410
411 struct {
412 unsigned long base;
413 vaddr_t vbase;
414 unsigned int len;
415 unsigned int len_usable;
416 unsigned int len_maximum;
417 } video;
418
419 struct {
420 unsigned long base;
421 vaddr_t vbase;
422 unsigned int len;
423 } mmio;
424
425 unsigned int max_pixel_clock;
426 unsigned int max_pixel_clock_panellink;
427
428 struct matrox_switch* hw_switch;
429
430 struct {
431 struct matrox_pll_features pll;
432 struct matrox_DAC1064_features DAC1064;
433 } features;
434 struct {
435 spinlock_t DAC;
436 spinlock_t accel;
437 } lock;
438
439 enum mga_chip chip;
440
441 int interleave;
442 int millenium;
443 int milleniumII;
444 struct {
445 int cfb4;
446 const int* vxres;
447 int cross4MB;
448 int text;
449 int plnwt;
450 int srcorg;
451 } capable;
452#ifdef CONFIG_MTRR
453 struct {
454 int vram;
455 int vram_valid;
456 } mtrr;
457#endif
458 struct {
459 int precise_width;
460 int mga_24bpp_fix;
461 int novga;
462 int nobios;
463 int nopciretry;
464 int noinit;
465 int sgram;
466 int support32MB;
467
468 int accelerator;
469 int text_type_aux;
470 int video64bits;
471 int crtc2;
472 int maven_capable;
473 unsigned int vgastep;
474 unsigned int textmode;
475 unsigned int textstep;
476 unsigned int textvram;
477 unsigned int ydstorg;
478
479 int memtype;
480 int g450dac;
481 int dfp_type;
482 int panellink;
483 int dualhead;
484 unsigned int fbResource;
485 } devflags;
486 struct fb_ops fbops;
487 struct matrox_bios bios;
488 struct {
489 struct matrox_pll_limits pixel;
490 struct matrox_pll_limits system;
491 struct matrox_pll_limits video;
492 } limits;
493 struct {
494 struct matrox_pll_cache pixel;
495 struct matrox_pll_cache system;
496 struct matrox_pll_cache video;
497 } cache;
498 struct {
499 struct {
500 unsigned int video;
501 unsigned int system;
502 } pll;
503 struct {
504 u_int32_t opt;
505 u_int32_t opt2;
506 u_int32_t opt3;
507 u_int32_t mctlwtst;
508 u_int32_t mctlwtst_core;
509 u_int32_t memmisc;
510 u_int32_t memrdbk;
511 u_int32_t maccess;
512 } reg;
513 struct {
514 unsigned int ddr:1,
515 emrswen:1,
516 dll:1;
517 } memory;
518 } values;
519 u_int32_t cmap[16];
520};
521
522#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
523
524struct matrox_switch {
525 int (*preinit)(struct matrox_fb_info *minfo);
526 void (*reset)(struct matrox_fb_info *minfo);
527 int (*init)(struct matrox_fb_info *minfo, struct my_timming*);
528 void (*restore)(struct matrox_fb_info *minfo);
529};
530
531struct matroxfb_driver {
532 struct list_head node;
533 char* name;
534 void* (*probe)(struct matrox_fb_info* info);
535 void (*remove)(struct matrox_fb_info* info, void* data);
536};
537
538int matroxfb_register_driver(struct matroxfb_driver* drv);
539void matroxfb_unregister_driver(struct matroxfb_driver* drv);
540
541#define PCI_OPTION_REG 0x40
542#define PCI_OPTION_ENABLE_ROM 0x40000000
543
544#define PCI_MGA_INDEX 0x44
545#define PCI_MGA_DATA 0x48
546#define PCI_OPTION2_REG 0x50
547#define PCI_OPTION3_REG 0x54
548#define PCI_MEMMISC_REG 0x58
549
550#define M_DWGCTL 0x1C00
551#define M_MACCESS 0x1C04
552#define M_CTLWTST 0x1C08
553
554#define M_PLNWT 0x1C1C
555
556#define M_BCOL 0x1C20
557#define M_FCOL 0x1C24
558
559#define M_SGN 0x1C58
560#define M_LEN 0x1C5C
561#define M_AR0 0x1C60
562#define M_AR1 0x1C64
563#define M_AR2 0x1C68
564#define M_AR3 0x1C6C
565#define M_AR4 0x1C70
566#define M_AR5 0x1C74
567#define M_AR6 0x1C78
568
569#define M_CXBNDRY 0x1C80
570#define M_FXBNDRY 0x1C84
571#define M_YDSTLEN 0x1C88
572#define M_PITCH 0x1C8C
573#define M_YDST 0x1C90
574#define M_YDSTORG 0x1C94
575#define M_YTOP 0x1C98
576#define M_YBOT 0x1C9C
577
578
579#define M_CACHEFLUSH 0x1FFF
580
581#define M_EXEC 0x0100
582
583#define M_DWG_TRAP 0x04
584#define M_DWG_BITBLT 0x08
585#define M_DWG_ILOAD 0x09
586
587#define M_DWG_LINEAR 0x0080
588#define M_DWG_SOLID 0x0800
589#define M_DWG_ARZERO 0x1000
590#define M_DWG_SGNZERO 0x2000
591#define M_DWG_SHIFTZERO 0x4000
592
593#define M_DWG_REPLACE 0x000C0000
594#define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
595#define M_DWG_XOR 0x00060010
596
597#define M_DWG_BFCOL 0x04000000
598#define M_DWG_BMONOWF 0x08000000
599
600#define M_DWG_TRANSC 0x40000000
601
602#define M_FIFOSTATUS 0x1E10
603#define M_STATUS 0x1E14
604#define M_ICLEAR 0x1E18
605#define M_IEN 0x1E1C
606
607#define M_VCOUNT 0x1E20
608
609#define M_RESET 0x1E40
610#define M_MEMRDBK 0x1E44
611
612#define M_AGP2PLL 0x1E4C
613
614#define M_OPMODE 0x1E54
615#define M_OPMODE_DMA_GEN_WRITE 0x00
616#define M_OPMODE_DMA_BLIT 0x04
617#define M_OPMODE_DMA_VECTOR_WRITE 0x08
618#define M_OPMODE_DMA_LE 0x0000
619#define M_OPMODE_DMA_BE_8BPP 0x0000
620#define M_OPMODE_DMA_BE_16BPP 0x0100
621#define M_OPMODE_DMA_BE_32BPP 0x0200
622#define M_OPMODE_DIR_LE 0x000000
623#define M_OPMODE_DIR_BE_8BPP 0x000000
624#define M_OPMODE_DIR_BE_16BPP 0x010000
625#define M_OPMODE_DIR_BE_32BPP 0x020000
626
627#define M_ATTR_INDEX 0x1FC0
628#define M_ATTR_DATA 0x1FC1
629
630#define M_MISC_REG 0x1FC2
631#define M_3C2_RD 0x1FC2
632
633#define M_SEQ_INDEX 0x1FC4
634#define M_SEQ_DATA 0x1FC5
635#define M_SEQ1 0x01
636#define M_SEQ1_SCROFF 0x20
637
638#define M_MISC_REG_READ 0x1FCC
639
640#define M_GRAPHICS_INDEX 0x1FCE
641#define M_GRAPHICS_DATA 0x1FCF
642
643#define M_CRTC_INDEX 0x1FD4
644
645#define M_ATTR_RESET 0x1FDA
646#define M_3DA_WR 0x1FDA
647#define M_INSTS1 0x1FDA
648
649#define M_EXTVGA_INDEX 0x1FDE
650#define M_EXTVGA_DATA 0x1FDF
651
652
653#define M_SRCORG 0x2CB4
654#define M_DSTORG 0x2CB8
655
656#define M_RAMDAC_BASE 0x3C00
657
658
659#define M_DAC_REG (M_RAMDAC_BASE+0)
660#define M_DAC_VAL (M_RAMDAC_BASE+1)
661#define M_PALETTE_MASK (M_RAMDAC_BASE+2)
662
663#define M_X_INDEX 0x00
664#define M_X_DATAREG 0x0A
665
666#define DAC_XGENIOCTRL 0x2A
667#define DAC_XGENIODATA 0x2B
668
669#define M_C2CTL 0x3C10
670
671#define MX_OPTION_BSWAP 0x00000000
672
673#ifdef __LITTLE_ENDIAN
674#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
675#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
676#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
677#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
678#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
679#else
680#ifdef __BIG_ENDIAN
681#define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
682#define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
683#define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
684#define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
685#define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
686#else
687#error "Byte ordering have to be defined. Cannot continue."
688#endif
689#endif
690
691#define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr))
692#define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr))
693#define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val))
694#define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val))
695#define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val))
696#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
697#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
698
699#define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
700
701#define WaitTillIdle() do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0)
702
703
704#ifdef CONFIG_FB_MATROX_MILLENIUM
705#define isInterleave(x) (x->interleave)
706#define isMillenium(x) (x->millenium)
707#define isMilleniumII(x) (x->milleniumII)
708#else
709#define isInterleave(x) (0)
710#define isMillenium(x) (0)
711#define isMilleniumII(x) (0)
712#endif
713
714#define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC)
715#define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC)
716#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags)
717#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
718extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg,
719 int val);
720extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg);
721extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
722extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc);
723extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable);
724
725#ifdef MATROXFB_USE_SPINLOCKS
726#define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags);
727#define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags);
728#define CRITFLAGS unsigned long critflags;
729#else
730#define CRITBEGIN
731#define CRITEND
732#define CRITFLAGS
733#endif
734
735#endif
736
