1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/types.h>
27#include <linux/i2c.h>
28#include <linux/delay.h>
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45#define DP_AUX_I2C_WRITE 0x0
46#define DP_AUX_I2C_READ 0x1
47#define DP_AUX_I2C_STATUS 0x2
48#define DP_AUX_I2C_MOT 0x4
49#define DP_AUX_NATIVE_WRITE 0x8
50#define DP_AUX_NATIVE_READ 0x9
51
52#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
53#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
54#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
55#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
56
57#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
58#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
59#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
60#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
61
62
63
64#define DP_DPCD_REV 0x000
65
66#define DP_MAX_LINK_RATE 0x001
67
68#define DP_MAX_LANE_COUNT 0x002
69# define DP_MAX_LANE_COUNT_MASK 0x1f
70# define DP_TPS3_SUPPORTED (1 << 6)
71# define DP_ENHANCED_FRAME_CAP (1 << 7)
72
73#define DP_MAX_DOWNSPREAD 0x003
74# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
75
76#define DP_NORP 0x004
77
78#define DP_DOWNSTREAMPORT_PRESENT 0x005
79# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
80# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
81# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
82# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
83# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
84# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
85# define DP_FORMAT_CONVERSION (1 << 3)
86# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
87
88#define DP_MAIN_LINK_CHANNEL_CODING 0x006
89
90#define DP_DOWN_STREAM_PORT_COUNT 0x007
91# define DP_PORT_COUNT_MASK 0x0f
92# define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
93# define DP_OUI_SUPPORT (1 << 7)
94
95#define DP_I2C_SPEED_CAP 0x00c
96# define DP_I2C_SPEED_1K 0x01
97# define DP_I2C_SPEED_5K 0x02
98# define DP_I2C_SPEED_10K 0x04
99# define DP_I2C_SPEED_100K 0x08
100# define DP_I2C_SPEED_400K 0x10
101# define DP_I2C_SPEED_1M 0x20
102
103#define DP_EDP_CONFIGURATION_CAP 0x00d
104#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
105
106
107#define DP_FAUX_CAP 0x020
108# define DP_FAUX_CAP_1 (1 << 0)
109
110#define DP_MSTM_CAP 0x021
111# define DP_MST_CAP (1 << 0)
112
113#define DP_GUID 0x030
114
115#define DP_PSR_SUPPORT 0x070
116# define DP_PSR_IS_SUPPORTED 1
117#define DP_PSR_CAPS 0x071
118# define DP_PSR_NO_TRAIN_ON_EXIT 1
119# define DP_PSR_SETUP_TIME_330 (0 << 1)
120# define DP_PSR_SETUP_TIME_275 (1 << 1)
121# define DP_PSR_SETUP_TIME_220 (2 << 1)
122# define DP_PSR_SETUP_TIME_165 (3 << 1)
123# define DP_PSR_SETUP_TIME_110 (4 << 1)
124# define DP_PSR_SETUP_TIME_55 (5 << 1)
125# define DP_PSR_SETUP_TIME_0 (6 << 1)
126# define DP_PSR_SETUP_TIME_MASK (7 << 1)
127# define DP_PSR_SETUP_TIME_SHIFT 1
128
129
130
131
132
133
134
135
136
137
138#define DP_DOWNSTREAM_PORT_0 0x80
139# define DP_DS_PORT_TYPE_MASK (7 << 0)
140# define DP_DS_PORT_TYPE_DP 0
141# define DP_DS_PORT_TYPE_VGA 1
142# define DP_DS_PORT_TYPE_DVI 2
143# define DP_DS_PORT_TYPE_HDMI 3
144# define DP_DS_PORT_TYPE_NON_EDID 4
145# define DP_DS_PORT_HPD (1 << 3)
146
147
148# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
149# define DP_DS_VGA_8BPC 0
150# define DP_DS_VGA_10BPC 1
151# define DP_DS_VGA_12BPC 2
152# define DP_DS_VGA_16BPC 3
153
154
155#define DP_LINK_BW_SET 0x100
156# define DP_LINK_BW_1_62 0x06
157# define DP_LINK_BW_2_7 0x0a
158# define DP_LINK_BW_5_4 0x14
159
160#define DP_LANE_COUNT_SET 0x101
161# define DP_LANE_COUNT_MASK 0x0f
162# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
163
164#define DP_TRAINING_PATTERN_SET 0x102
165# define DP_TRAINING_PATTERN_DISABLE 0
166# define DP_TRAINING_PATTERN_1 1
167# define DP_TRAINING_PATTERN_2 2
168# define DP_TRAINING_PATTERN_3 3
169# define DP_TRAINING_PATTERN_MASK 0x3
170
171# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
172# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
173# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
174# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
175# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
176
177# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
178# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
179
180# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
181# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
182# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
183# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
184
185#define DP_TRAINING_LANE0_SET 0x103
186#define DP_TRAINING_LANE1_SET 0x104
187#define DP_TRAINING_LANE2_SET 0x105
188#define DP_TRAINING_LANE3_SET 0x106
189
190# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
191# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
192# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
193# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
194# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
195# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
196# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
197
198# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
199# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
200# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
201# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
202# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
203
204# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
205# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
206
207#define DP_DOWNSPREAD_CTRL 0x107
208# define DP_SPREAD_AMP_0_5 (1 << 4)
209# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
210
211#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
212# define DP_SET_ANSI_8B10B (1 << 0)
213
214#define DP_I2C_SPEED_CONTROL_STATUS 0x109
215
216
217#define DP_EDP_CONFIGURATION_SET 0x10a
218
219#define DP_MSTM_CTRL 0x111
220# define DP_MST_EN (1 << 0)
221# define DP_UP_REQ_EN (1 << 1)
222# define DP_UPSTREAM_IS_SRC (1 << 2)
223
224#define DP_PSR_EN_CFG 0x170
225# define DP_PSR_ENABLE (1 << 0)
226# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
227# define DP_PSR_CRC_VERIFICATION (1 << 2)
228# define DP_PSR_FRAME_CAPTURE (1 << 3)
229
230#define DP_ADAPTER_CTRL 0x1a0
231# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
232
233#define DP_BRANCH_DEVICE_CTRL 0x1a1
234# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
235
236#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
237#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
238#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
239
240#define DP_SINK_COUNT 0x200
241
242# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
243# define DP_SINK_CP_READY (1 << 6)
244
245#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
246# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
247# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
248# define DP_CP_IRQ (1 << 2)
249# define DP_MCCS_IRQ (1 << 3)
250# define DP_DOWN_REP_MSG_RDY (1 << 4)
251# define DP_UP_REQ_MSG_RDY (1 << 5)
252# define DP_SINK_SPECIFIC_IRQ (1 << 6)
253
254#define DP_LANE0_1_STATUS 0x202
255#define DP_LANE2_3_STATUS 0x203
256# define DP_LANE_CR_DONE (1 << 0)
257# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
258# define DP_LANE_SYMBOL_LOCKED (1 << 2)
259
260#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
261 DP_LANE_CHANNEL_EQ_DONE | \
262 DP_LANE_SYMBOL_LOCKED)
263
264#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
265
266#define DP_INTERLANE_ALIGN_DONE (1 << 0)
267#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
268#define DP_LINK_STATUS_UPDATED (1 << 7)
269
270#define DP_SINK_STATUS 0x205
271
272#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
273#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
274
275#define DP_ADJUST_REQUEST_LANE0_1 0x206
276#define DP_ADJUST_REQUEST_LANE2_3 0x207
277# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
278# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
279# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
280# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
281# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
282# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
283# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
284# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
285
286#define DP_TEST_REQUEST 0x218
287# define DP_TEST_LINK_TRAINING (1 << 0)
288# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
289# define DP_TEST_LINK_EDID_READ (1 << 2)
290# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3)
291# define DP_TEST_LINK_FAUX_PATTERN (1 << 4)
292
293#define DP_TEST_LINK_RATE 0x219
294# define DP_LINK_RATE_162 (0x6)
295# define DP_LINK_RATE_27 (0xa)
296
297#define DP_TEST_LANE_COUNT 0x220
298
299#define DP_TEST_PATTERN 0x221
300
301#define DP_TEST_CRC_R_CR 0x240
302#define DP_TEST_CRC_G_Y 0x242
303#define DP_TEST_CRC_B_CB 0x244
304
305#define DP_TEST_SINK_MISC 0x246
306# define DP_TEST_CRC_SUPPORTED (1 << 5)
307# define DP_TEST_COUNT_MASK 0x7
308
309#define DP_TEST_RESPONSE 0x260
310# define DP_TEST_ACK (1 << 0)
311# define DP_TEST_NAK (1 << 1)
312# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
313
314#define DP_TEST_EDID_CHECKSUM 0x261
315
316#define DP_TEST_SINK 0x270
317# define DP_TEST_SINK_START (1 << 0)
318
319#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0
320# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
321# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
322
323#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1
324
325
326#define DP_SOURCE_OUI 0x300
327#define DP_SINK_OUI 0x400
328#define DP_BRANCH_OUI 0x500
329
330#define DP_SET_POWER 0x600
331# define DP_SET_POWER_D0 0x1
332# define DP_SET_POWER_D3 0x2
333# define DP_SET_POWER_MASK 0x3
334
335#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000
336#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200
337#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400
338#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600
339
340#define DP_SINK_COUNT_ESI 0x2002
341
342# define DP_SINK_COUNT_CP_READY (1 << 6)
343
344#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003
345
346#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004
347
348#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005
349
350#define DP_PSR_ERROR_STATUS 0x2006
351# define DP_PSR_LINK_CRC_ERROR (1 << 0)
352# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
353
354#define DP_PSR_ESI 0x2007
355# define DP_PSR_CAPS_CHANGE (1 << 0)
356
357#define DP_PSR_STATUS 0x2008
358# define DP_PSR_SINK_INACTIVE 0
359# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
360# define DP_PSR_SINK_ACTIVE_RFB 2
361# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
362# define DP_PSR_SINK_ACTIVE_RESYNC 4
363# define DP_PSR_SINK_INTERNAL_ERROR 7
364# define DP_PSR_SINK_STATE_MASK 0x07
365
366
367
368#define DP_PEER_DEVICE_NONE 0x0
369#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
370#define DP_PEER_DEVICE_MST_BRANCHING 0x2
371#define DP_PEER_DEVICE_SST_SINK 0x3
372#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
373
374
375#define DP_LINK_ADDRESS 0x01
376#define DP_CONNECTION_STATUS_NOTIFY 0x02
377#define DP_ENUM_PATH_RESOURCES 0x10
378#define DP_ALLOCATE_PAYLOAD 0x11
379#define DP_QUERY_PAYLOAD 0x12
380#define DP_RESOURCE_STATUS_NOTIFY 0x13
381#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
382#define DP_REMOTE_DPCD_READ 0x20
383#define DP_REMOTE_DPCD_WRITE 0x21
384#define DP_REMOTE_I2C_READ 0x22
385#define DP_REMOTE_I2C_WRITE 0x23
386#define DP_POWER_UP_PHY 0x24
387#define DP_POWER_DOWN_PHY 0x25
388#define DP_SINK_EVENT_NOTIFY 0x30
389#define DP_QUERY_STREAM_ENC_STATUS 0x38
390
391
392#define DP_NAK_WRITE_FAILURE 0x01
393#define DP_NAK_INVALID_READ 0x02
394#define DP_NAK_CRC_FAILURE 0x03
395#define DP_NAK_BAD_PARAM 0x04
396#define DP_NAK_DEFER 0x05
397#define DP_NAK_LINK_FAILURE 0x06
398#define DP_NAK_NO_RESOURCES 0x07
399#define DP_NAK_DPCD_FAIL 0x08
400#define DP_NAK_I2C_NAK 0x09
401#define DP_NAK_ALLOCATE_FAIL 0x0a
402
403#define MODE_I2C_START 1
404#define MODE_I2C_WRITE 2
405#define MODE_I2C_READ 4
406#define MODE_I2C_STOP 8
407
408#define DP_LINK_STATUS_SIZE 6
409bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
410 int lane_count);
411bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
412 int lane_count);
413u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
414 int lane);
415u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
416 int lane);
417
418#define DP_RECEIVER_CAP_SIZE 0xf
419#define EDP_PSR_RECEIVER_CAP_SIZE 2
420
421void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
422void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
423
424u8 drm_dp_link_rate_to_bw_code(int link_rate);
425int drm_dp_bw_code_to_link_rate(u8 link_bw);
426
427struct edp_sdp_header {
428 u8 HB0;
429 u8 HB1;
430 u8 HB2;
431 u8 HB3;
432} __packed;
433
434#define EDP_SDP_HEADER_REVISION_MASK 0x1F
435#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
436
437struct edp_vsc_psr {
438 struct edp_sdp_header sdp_header;
439 u8 DB0;
440 u8 DB1;
441 u8 DB2;
442 u8 DB3;
443 u8 DB4;
444 u8 DB5;
445 u8 DB6;
446 u8 DB7;
447 u8 DB8_31[24];
448} __packed;
449
450#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
451#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
452#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
453
454static inline int
455drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
456{
457 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
458}
459
460static inline u8
461drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
462{
463 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
464}
465
466static inline bool
467drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
468{
469 return dpcd[DP_DPCD_REV] >= 0x11 &&
470 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
471}
472
473
474
475
476
477
478
479
480
481
482
483
484
485struct drm_dp_aux_msg {
486 unsigned int address;
487 u8 request;
488 u8 reply;
489 void *buffer;
490 size_t size;
491};
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527struct drm_dp_aux {
528 const char *name;
529 struct i2c_adapter ddc;
530 struct device *dev;
531 struct mutex hw_mutex;
532 ssize_t (*transfer)(struct drm_dp_aux *aux,
533 struct drm_dp_aux_msg *msg);
534 unsigned i2c_nack_count, i2c_defer_count;
535};
536
537ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
538 void *buffer, size_t size);
539ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
540 void *buffer, size_t size);
541
542
543
544
545
546
547
548
549
550
551static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
552 unsigned int offset, u8 *valuep)
553{
554 return drm_dp_dpcd_read(aux, offset, valuep, 1);
555}
556
557
558
559
560
561
562
563
564
565
566static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
567 unsigned int offset, u8 value)
568{
569 return drm_dp_dpcd_write(aux, offset, &value, 1);
570}
571
572int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
573 u8 status[DP_LINK_STATUS_SIZE]);
574
575
576
577
578#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
579
580struct drm_dp_link {
581 unsigned char revision;
582 unsigned int rate;
583 unsigned int num_lanes;
584 unsigned long capabilities;
585};
586
587int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
588int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
589int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
590int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
591
592int drm_dp_aux_register(struct drm_dp_aux *aux);
593void drm_dp_aux_unregister(struct drm_dp_aux *aux);
594
595#endif
596