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19#ifndef __ASM_ARM_KVM_VGIC_H
20#define __ASM_ARM_KVM_VGIC_H
21
22#include <linux/kernel.h>
23#include <linux/kvm.h>
24#include <linux/irqreturn.h>
25#include <linux/spinlock.h>
26#include <linux/types.h>
27
28#define VGIC_NR_IRQS_LEGACY 256
29#define VGIC_NR_SGIS 16
30#define VGIC_NR_PPIS 16
31#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
32
33#define VGIC_V2_MAX_LRS (1 << 6)
34#define VGIC_V3_MAX_LRS 16
35#define VGIC_MAX_IRQS 1024
36#define VGIC_V2_MAX_CPUS 8
37
38
39#if (KVM_MAX_VCPUS > 255)
40#error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
41#endif
42
43#if (VGIC_NR_IRQS_LEGACY & 31)
44#error "VGIC_NR_IRQS must be a multiple of 32"
45#endif
46
47#if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
48#error "VGIC_NR_IRQS must be <= 1024"
49#endif
50
51
52
53
54
55
56struct vgic_bitmap {
57
58
59
60
61
62
63
64
65
66
67 unsigned long *private;
68 unsigned long *shared;
69};
70
71struct vgic_bytemap {
72
73
74
75
76
77
78
79
80
81
82 u32 *private;
83 u32 *shared;
84};
85
86struct kvm_vcpu;
87
88enum vgic_type {
89 VGIC_V2,
90 VGIC_V3,
91};
92
93#define LR_STATE_PENDING (1 << 0)
94#define LR_STATE_ACTIVE (1 << 1)
95#define LR_STATE_MASK (3 << 0)
96#define LR_EOI_INT (1 << 2)
97
98struct vgic_lr {
99 u16 irq;
100 u8 source;
101 u8 state;
102};
103
104struct vgic_vmcr {
105 u32 ctlr;
106 u32 abpr;
107 u32 bpr;
108 u32 pmr;
109};
110
111struct vgic_ops {
112 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
113 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
114 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
115 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
116 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
117 void (*clear_eisr)(struct kvm_vcpu *vcpu);
118 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
119 void (*enable_underflow)(struct kvm_vcpu *vcpu);
120 void (*disable_underflow)(struct kvm_vcpu *vcpu);
121 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
122 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
123 void (*enable)(struct kvm_vcpu *vcpu);
124};
125
126struct vgic_params {
127
128 enum vgic_type type;
129
130 phys_addr_t vcpu_base;
131
132 u32 nr_lr;
133
134 unsigned int maint_irq;
135
136 void __iomem *vctrl_base;
137 int max_gic_vcpus;
138
139 bool can_emulate_gicv2;
140};
141
142struct vgic_vm_ops {
143 bool (*handle_mmio)(struct kvm_vcpu *, struct kvm_run *,
144 struct kvm_exit_mmio *);
145 bool (*queue_sgi)(struct kvm_vcpu *, int irq);
146 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
147 int (*init_model)(struct kvm *);
148 int (*map_resources)(struct kvm *, const struct vgic_params *);
149};
150
151struct vgic_dist {
152#ifdef CONFIG_KVM_ARM_VGIC
153 spinlock_t lock;
154 bool in_kernel;
155 bool ready;
156
157
158 u32 vgic_model;
159
160 int nr_cpus;
161 int nr_irqs;
162
163
164 void __iomem *vctrl_base;
165
166
167 phys_addr_t vgic_dist_base;
168
169 union {
170 phys_addr_t vgic_cpu_base;
171 phys_addr_t vgic_redist_base;
172 };
173
174
175 u32 enabled;
176
177
178 struct vgic_bitmap irq_enabled;
179
180
181 struct vgic_bitmap irq_level;
182
183
184
185
186 struct vgic_bitmap irq_pending;
187
188
189
190
191
192
193
194
195 struct vgic_bitmap irq_soft_pend;
196
197
198 struct vgic_bitmap irq_queued;
199
200
201 struct vgic_bytemap irq_priority;
202
203
204 struct vgic_bitmap irq_cfg;
205
206
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211
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213
214
215
216 u8 *irq_sgi_sources;
217
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222
223
224 u8 *irq_spi_cpu;
225
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229
230
231
232 struct vgic_bitmap *irq_spi_target;
233
234
235 u32 *irq_spi_mpidr;
236
237
238 unsigned long *irq_pending_on_cpu;
239
240 struct vgic_vm_ops vm_ops;
241#endif
242};
243
244struct vgic_v2_cpu_if {
245 u32 vgic_hcr;
246 u32 vgic_vmcr;
247 u32 vgic_misr;
248 u64 vgic_eisr;
249 u64 vgic_elrsr;
250 u32 vgic_apr;
251 u32 vgic_lr[VGIC_V2_MAX_LRS];
252};
253
254struct vgic_v3_cpu_if {
255#ifdef CONFIG_ARM_GIC_V3
256 u32 vgic_hcr;
257 u32 vgic_vmcr;
258 u32 vgic_sre;
259 u32 vgic_misr;
260 u32 vgic_eisr;
261 u32 vgic_elrsr;
262 u32 vgic_ap0r[4];
263 u32 vgic_ap1r[4];
264 u64 vgic_lr[VGIC_V3_MAX_LRS];
265#endif
266};
267
268struct vgic_cpu {
269#ifdef CONFIG_KVM_ARM_VGIC
270
271 u8 *vgic_irq_lr_map;
272
273
274 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
275 unsigned long *pending_shared;
276
277
278 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
279
280
281 int nr_lr;
282
283
284 union {
285 struct vgic_v2_cpu_if vgic_v2;
286 struct vgic_v3_cpu_if vgic_v3;
287 };
288#endif
289};
290
291#define LR_EMPTY 0xff
292
293#define INT_STATUS_EOI (1 << 0)
294#define INT_STATUS_UNDERFLOW (1 << 1)
295
296struct kvm;
297struct kvm_vcpu;
298struct kvm_run;
299struct kvm_exit_mmio;
300
301#ifdef CONFIG_KVM_ARM_VGIC
302int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
303int kvm_vgic_hyp_init(void);
304int kvm_vgic_map_resources(struct kvm *kvm);
305int kvm_vgic_get_max_vcpus(void);
306int kvm_vgic_create(struct kvm *kvm, u32 type);
307void kvm_vgic_destroy(struct kvm *kvm);
308void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
309void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
310void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
311int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
312 bool level);
313void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
314int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
315bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
316 struct kvm_exit_mmio *mmio);
317
318#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
319#define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
320#define vgic_ready(k) ((k)->arch.vgic.ready)
321
322int vgic_v2_probe(struct device_node *vgic_node,
323 const struct vgic_ops **ops,
324 const struct vgic_params **params);
325#ifdef CONFIG_ARM_GIC_V3
326int vgic_v3_probe(struct device_node *vgic_node,
327 const struct vgic_ops **ops,
328 const struct vgic_params **params);
329#else
330static inline int vgic_v3_probe(struct device_node *vgic_node,
331 const struct vgic_ops **ops,
332 const struct vgic_params **params)
333{
334 return -ENODEV;
335}
336#endif
337
338#else
339static inline int kvm_vgic_hyp_init(void)
340{
341 return 0;
342}
343
344static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
345{
346 return 0;
347}
348
349static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
350{
351 return -ENXIO;
352}
353
354static inline int kvm_vgic_map_resources(struct kvm *kvm)
355{
356 return 0;
357}
358
359static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
360{
361 return 0;
362}
363
364static inline void kvm_vgic_destroy(struct kvm *kvm)
365{
366}
367
368static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
369{
370}
371
372static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
373{
374 return 0;
375}
376
377static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
378static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
379
380static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
381 unsigned int irq_num, bool level)
382{
383 return 0;
384}
385
386static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
387{
388 return 0;
389}
390
391static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
392 struct kvm_exit_mmio *mmio)
393{
394 return false;
395}
396
397static inline int irqchip_in_kernel(struct kvm *kvm)
398{
399 return 0;
400}
401
402static inline bool vgic_initialized(struct kvm *kvm)
403{
404 return true;
405}
406
407static inline bool vgic_ready(struct kvm *kvm)
408{
409 return true;
410}
411
412static inline int kvm_vgic_get_max_vcpus(void)
413{
414 return KVM_MAX_VCPUS;
415}
416#endif
417
418#endif
419