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12#ifndef __LINUX_MFD_88PM80X_H
13#define __LINUX_MFD_88PM80X_H
14
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/regmap.h>
18#include <linux/atomic.h>
19
20enum {
21 CHIP_INVALID = 0,
22 CHIP_PM800,
23 CHIP_PM805,
24 CHIP_MAX,
25};
26
27enum {
28 PM800_ID_BUCK1 = 0,
29 PM800_ID_BUCK2,
30 PM800_ID_BUCK3,
31 PM800_ID_BUCK4,
32 PM800_ID_BUCK5,
33
34 PM800_ID_LDO1,
35 PM800_ID_LDO2,
36 PM800_ID_LDO3,
37 PM800_ID_LDO4,
38 PM800_ID_LDO5,
39 PM800_ID_LDO6,
40 PM800_ID_LDO7,
41 PM800_ID_LDO8,
42 PM800_ID_LDO9,
43 PM800_ID_LDO10,
44 PM800_ID_LDO11,
45 PM800_ID_LDO12,
46 PM800_ID_LDO13,
47 PM800_ID_LDO14,
48 PM800_ID_LDO15,
49 PM800_ID_LDO16,
50 PM800_ID_LDO17,
51 PM800_ID_LDO18,
52 PM800_ID_LDO19,
53
54 PM800_ID_RG_MAX,
55};
56#define PM800_MAX_REGULATOR PM800_ID_RG_MAX
57#define PM800_NUM_BUCK (5)
58#define PM800_NUM_LDO (19)
59
60
61
62#define PM800_STATUS_1 (0x01)
63#define PM800_ONKEY_STS1 (1 << 0)
64#define PM800_EXTON_STS1 (1 << 1)
65#define PM800_CHG_STS1 (1 << 2)
66#define PM800_BAT_STS1 (1 << 3)
67#define PM800_VBUS_STS1 (1 << 4)
68#define PM800_LDO_PGOOD_STS1 (1 << 5)
69#define PM800_BUCK_PGOOD_STS1 (1 << 6)
70
71#define PM800_STATUS_2 (0x02)
72#define PM800_RTC_ALARM_STS2 (1 << 0)
73
74
75#define PM800_WAKEUP1 (0x0D)
76
77#define PM800_WAKEUP2 (0x0E)
78#define PM800_WAKEUP2_INV_INT (1 << 0)
79#define PM800_WAKEUP2_INT_CLEAR (1 << 1)
80#define PM800_WAKEUP2_INT_MASK (1 << 2)
81
82#define PM800_POWER_UP_LOG (0x10)
83
84
85#define PM800_LOW_POWER1 (0x20)
86#define PM800_LOW_POWER2 (0x21)
87#define PM800_LOW_POWER_CONFIG3 (0x22)
88#define PM800_LOW_POWER_CONFIG4 (0x23)
89
90
91#define PM800_GPIO_0_1_CNTRL (0x30)
92#define PM800_GPIO0_VAL (1 << 0)
93#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
94#define PM800_GPIO1_VAL (1 << 4)
95#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
96
97#define PM800_GPIO_2_3_CNTRL (0x31)
98#define PM800_GPIO2_VAL (1 << 0)
99#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
100#define PM800_GPIO3_VAL (1 << 4)
101#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
102#define PM800_GPIO3_MODE_MASK 0x1F
103#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
104
105#define PM800_GPIO_4_CNTRL (0x32)
106#define PM800_GPIO4_VAL (1 << 0)
107#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
108
109#define PM800_HEADSET_CNTRL (0x38)
110#define PM800_HEADSET_DET_EN (1 << 7)
111#define PM800_HSDET_SLP (1 << 1)
112
113#define PM800_PWM1 (0x40)
114#define PM800_PWM2 (0x41)
115#define PM800_PWM3 (0x42)
116#define PM800_PWM4 (0x43)
117
118
119#define PM800_RTC_CONTROL (0xD0)
120#define PM800_RTC_MISC1 (0xE1)
121#define PM800_RTC_MISC2 (0xE2)
122#define PM800_RTC_MISC3 (0xE3)
123#define PM800_RTC_MISC4 (0xE4)
124#define PM800_RTC_MISC5 (0xE7)
125
126#define PM800_ALARM1_EN (1 << 0)
127#define PM800_ALARM_WAKEUP (1 << 4)
128#define PM800_ALARM (1 << 5)
129#define PM800_RTC1_USE_XO (1 << 7)
130
131
132
133
134#define PM800_SLEEP_BUCK1 (0x30)
135
136
137#define PM800_BUCK_SLP1 (0x5A)
138#define PM800_BUCK1_SLP1_SHIFT 0
139#define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT)
140
141
142#define PM800_GPADC_MEAS_EN1 (0x01)
143#define PM800_MEAS_EN1_VBAT (1 << 2)
144#define PM800_GPADC_MEAS_EN2 (0x02)
145#define PM800_MEAS_EN2_RFTMP (1 << 0)
146#define PM800_MEAS_GP0_EN (1 << 2)
147#define PM800_MEAS_GP1_EN (1 << 3)
148#define PM800_MEAS_GP2_EN (1 << 4)
149#define PM800_MEAS_GP3_EN (1 << 5)
150#define PM800_MEAS_GP4_EN (1 << 6)
151
152#define PM800_GPADC_MISC_CONFIG1 (0x05)
153#define PM800_GPADC_MISC_CONFIG2 (0x06)
154#define PM800_GPADC_MISC_GPFSM_EN (1 << 0)
155#define PM800_GPADC_SLOW_MODE(x) (x << 3)
156
157#define PM800_GPADC_MISC_CONFIG3 (0x09)
158#define PM800_GPADC_MISC_CONFIG4 (0x0A)
159
160#define PM800_GPADC_PREBIAS1 (0x0F)
161#define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0)
162#define PM800_GPADC_PREBIAS2 (0x10)
163
164#define PM800_GP_BIAS_ENA1 (0x14)
165#define PM800_GPADC_GP_BIAS_EN0 (1 << 0)
166#define PM800_GPADC_GP_BIAS_EN1 (1 << 1)
167#define PM800_GPADC_GP_BIAS_EN2 (1 << 2)
168#define PM800_GPADC_GP_BIAS_EN3 (1 << 3)
169
170#define PM800_GP_BIAS_OUT1 (0x15)
171#define PM800_BIAS_OUT_GP0 (1 << 0)
172#define PM800_BIAS_OUT_GP1 (1 << 1)
173#define PM800_BIAS_OUT_GP2 (1 << 2)
174#define PM800_BIAS_OUT_GP3 (1 << 3)
175
176#define PM800_GPADC0_LOW_TH 0x20
177#define PM800_GPADC1_LOW_TH 0x21
178#define PM800_GPADC2_LOW_TH 0x22
179#define PM800_GPADC3_LOW_TH 0x23
180#define PM800_GPADC4_LOW_TH 0x24
181
182#define PM800_GPADC0_UPP_TH 0x30
183#define PM800_GPADC1_UPP_TH 0x31
184#define PM800_GPADC2_UPP_TH 0x32
185#define PM800_GPADC3_UPP_TH 0x33
186#define PM800_GPADC4_UPP_TH 0x34
187
188#define PM800_VBBAT_MEAS1 0x40
189#define PM800_VBBAT_MEAS2 0x41
190#define PM800_VBAT_MEAS1 0x42
191#define PM800_VBAT_MEAS2 0x43
192#define PM800_VSYS_MEAS1 0x44
193#define PM800_VSYS_MEAS2 0x45
194#define PM800_VCHG_MEAS1 0x46
195#define PM800_VCHG_MEAS2 0x47
196#define PM800_TINT_MEAS1 0x50
197#define PM800_TINT_MEAS2 0x51
198#define PM800_PMOD_MEAS1 0x52
199#define PM800_PMOD_MEAS2 0x53
200
201#define PM800_GPADC0_MEAS1 0x54
202#define PM800_GPADC0_MEAS2 0x55
203#define PM800_GPADC1_MEAS1 0x56
204#define PM800_GPADC1_MEAS2 0x57
205#define PM800_GPADC2_MEAS1 0x58
206#define PM800_GPADC2_MEAS2 0x59
207#define PM800_GPADC3_MEAS1 0x5A
208#define PM800_GPADC3_MEAS2 0x5B
209#define PM800_GPADC4_MEAS1 0x5C
210#define PM800_GPADC4_MEAS2 0x5D
211
212#define PM800_GPADC4_AVG1 0xA8
213#define PM800_GPADC4_AVG2 0xA9
214
215
216#define PM805_MAIN_POWERUP (0x01)
217#define PM805_INT_STATUS0 (0x02)
218
219#define PM805_STATUS0_INT_CLEAR (1 << 0)
220#define PM805_STATUS0_INV_INT (1 << 1)
221#define PM800_STATUS0_INT_MASK (1 << 2)
222
223#define PM805_INT_STATUS1 (0x03)
224
225#define PM805_INT1_HP1_SHRT (1 << 0)
226#define PM805_INT1_HP2_SHRT (1 << 1)
227#define PM805_INT1_MIC_CONFLICT (1 << 2)
228#define PM805_INT1_CLIP_FAULT (1 << 3)
229#define PM805_INT1_LDO_OFF (1 << 4)
230#define PM805_INT1_SRC_DPLL_LOCK (1 << 5)
231
232#define PM805_INT_STATUS2 (0x04)
233
234#define PM805_INT2_MIC_DET (1 << 0)
235#define PM805_INT2_SHRT_BTN_DET (1 << 1)
236#define PM805_INT2_VOLM_BTN_DET (1 << 2)
237#define PM805_INT2_VOLP_BTN_DET (1 << 3)
238#define PM805_INT2_RAW_PLL_FAULT (1 << 4)
239#define PM805_INT2_FINE_PLL_FAULT (1 << 5)
240
241#define PM805_INT_MASK1 (0x05)
242#define PM805_INT_MASK2 (0x06)
243#define PM805_SHRT_BTN_DET (1 << 1)
244
245
246#define PM805_INT_REG_NUM (2)
247
248#define PM805_MIC_DET1 (0x07)
249#define PM805_MIC_DET_EN_MIC_DET (1 << 0)
250#define PM805_MIC_DET2 (0x08)
251#define PM805_MIC_DET_STATUS1 (0x09)
252
253#define PM805_MIC_DET_STATUS3 (0x0A)
254#define PM805_AUTO_SEQ_STATUS1 (0x0B)
255#define PM805_AUTO_SEQ_STATUS2 (0x0C)
256
257#define PM805_ADC_SETTING1 (0x10)
258#define PM805_ADC_SETTING2 (0x11)
259#define PM805_ADC_SETTING3 (0x11)
260#define PM805_ADC_GAIN1 (0x12)
261#define PM805_ADC_GAIN2 (0x13)
262#define PM805_DMIC_SETTING (0x15)
263#define PM805_DWS_SETTING (0x16)
264#define PM805_MIC_CONFLICT_STS (0x17)
265
266#define PM805_PDM_SETTING1 (0x20)
267#define PM805_PDM_SETTING2 (0x21)
268#define PM805_PDM_SETTING3 (0x22)
269#define PM805_PDM_CONTROL1 (0x23)
270#define PM805_PDM_CONTROL2 (0x24)
271#define PM805_PDM_CONTROL3 (0x25)
272
273#define PM805_HEADPHONE_SETTING (0x26)
274#define PM805_HEADPHONE_GAIN_A2A (0x27)
275#define PM805_HEADPHONE_SHORT_STATE (0x28)
276#define PM805_EARPHONE_SETTING (0x29)
277#define PM805_AUTO_SEQ_SETTING (0x2A)
278
279struct pm80x_rtc_pdata {
280 int vrtc;
281 int rtc_wakeup;
282};
283
284struct pm80x_subchip {
285 struct i2c_client *power_page;
286 struct i2c_client *gpadc_page;
287 struct regmap *regmap_power;
288 struct regmap *regmap_gpadc;
289 unsigned short power_page_addr;
290 unsigned short gpadc_page_addr;
291};
292
293struct pm80x_chip {
294 struct pm80x_subchip *subchip;
295 struct device *dev;
296 struct i2c_client *client;
297 struct i2c_client *companion;
298 struct regmap *regmap;
299 struct regmap_irq_chip *regmap_irq_chip;
300 struct regmap_irq_chip_data *irq_data;
301 int type;
302 int irq;
303 int irq_mode;
304 unsigned long wu_flag;
305 spinlock_t lock;
306};
307
308struct pm80x_platform_data {
309 struct pm80x_rtc_pdata *rtc;
310
311
312
313
314
315
316 struct regulator_init_data *regulators[PM800_ID_RG_MAX];
317 unsigned int num_regulators;
318 int irq_mode;
319 int batt_det;
320 int (*plat_config)(struct pm80x_chip *chip,
321 struct pm80x_platform_data *pdata);
322};
323
324extern const struct dev_pm_ops pm80x_pm_ops;
325extern const struct regmap_config pm80x_regmap_config;
326
327static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq,
328 irq_handler_t handler, unsigned long flags,
329 const char *name, void *data)
330{
331 if (!pm80x->irq_data)
332 return -EINVAL;
333 return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq),
334 NULL, handler, flags, name, data);
335}
336
337static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data)
338{
339 if (!pm80x->irq_data)
340 return;
341 free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data);
342}
343
344#ifdef CONFIG_PM
345static inline int pm80x_dev_suspend(struct device *dev)
346{
347 struct platform_device *pdev = to_platform_device(dev);
348 struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
349 int irq = platform_get_irq(pdev, 0);
350
351 if (device_may_wakeup(dev))
352 set_bit((1 << irq), &chip->wu_flag);
353
354 return 0;
355}
356
357static inline int pm80x_dev_resume(struct device *dev)
358{
359 struct platform_device *pdev = to_platform_device(dev);
360 struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent);
361 int irq = platform_get_irq(pdev, 0);
362
363 if (device_may_wakeup(dev))
364 clear_bit((1 << irq), &chip->wu_flag);
365
366 return 0;
367}
368#endif
369
370extern int pm80x_init(struct i2c_client *client);
371extern int pm80x_deinit(void);
372#endif
373
