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18#ifndef __LINUX_MTD_NAND_H
19#define __LINUX_MTD_NAND_H
20
21#include <linux/wait.h>
22#include <linux/spinlock.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/flashchip.h>
25#include <linux/mtd/bbm.h>
26
27struct mtd_info;
28struct nand_flash_dev;
29
30extern int nand_scan(struct mtd_info *mtd, int max_chips);
31
32
33
34
35extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
37extern int nand_scan_tail(struct mtd_info *mtd);
38
39
40extern void nand_release(struct mtd_info *mtd);
41
42
43extern void nand_wait_ready(struct mtd_info *mtd);
44
45
46extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
47
48
49extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50
51
52#define NAND_MAX_CHIPS 8
53
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59
60
61#define NAND_NCE 0x01
62
63#define NAND_CLE 0x02
64
65#define NAND_ALE 0x04
66
67#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69#define NAND_CTRL_CHANGE 0x80
70
71
72
73
74#define NAND_CMD_READ0 0
75#define NAND_CMD_READ1 1
76#define NAND_CMD_RNDOUT 5
77#define NAND_CMD_PAGEPROG 0x10
78#define NAND_CMD_READOOB 0x50
79#define NAND_CMD_ERASE1 0x60
80#define NAND_CMD_STATUS 0x70
81#define NAND_CMD_SEQIN 0x80
82#define NAND_CMD_RNDIN 0x85
83#define NAND_CMD_READID 0x90
84#define NAND_CMD_ERASE2 0xd0
85#define NAND_CMD_PARAM 0xec
86#define NAND_CMD_GET_FEATURES 0xee
87#define NAND_CMD_SET_FEATURES 0xef
88#define NAND_CMD_RESET 0xff
89
90#define NAND_CMD_LOCK 0x2a
91#define NAND_CMD_UNLOCK1 0x23
92#define NAND_CMD_UNLOCK2 0x24
93
94
95#define NAND_CMD_READSTART 0x30
96#define NAND_CMD_RNDOUTSTART 0xE0
97#define NAND_CMD_CACHEDPROG 0x15
98
99#define NAND_CMD_NONE -1
100
101
102#define NAND_STATUS_FAIL 0x01
103#define NAND_STATUS_FAIL_N1 0x02
104#define NAND_STATUS_TRUE_READY 0x20
105#define NAND_STATUS_READY 0x40
106#define NAND_STATUS_WP 0x80
107
108
109
110
111typedef enum {
112 NAND_ECC_NONE,
113 NAND_ECC_SOFT,
114 NAND_ECC_HW,
115 NAND_ECC_HW_SYNDROME,
116 NAND_ECC_HW_OOB_FIRST,
117 NAND_ECC_SOFT_BCH,
118} nand_ecc_modes_t;
119
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121
122
123
124#define NAND_ECC_READ 0
125
126#define NAND_ECC_WRITE 1
127
128#define NAND_ECC_READSYN 2
129
130
131#define NAND_GET_DEVICE 0x80
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138
139#define NAND_BUSWIDTH_16 0x00000002
140
141#define NAND_CACHEPRG 0x00000008
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146
147#define NAND_NEED_READRDY 0x00000100
148
149
150#define NAND_NO_SUBPAGE_WRITE 0x00000200
151
152
153#define NAND_BROKEN_XD 0x00000400
154
155
156#define NAND_ROM 0x00000800
157
158
159#define NAND_SUBPAGE_READ 0x00001000
160
161
162#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
163
164
165#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
166#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
167
168
169
170#define NAND_SKIP_BBTSCAN 0x00010000
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174
175#define NAND_OWN_BUFFERS 0x00020000
176
177#define NAND_SCAN_SILENT_NODEV 0x00040000
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181
182#define NAND_USE_BOUNCE_BUFFER 0x00080000
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188
189#define NAND_BUSWIDTH_AUTO 0x00080000
190
191
192
193#define NAND_CONTROLLER_ALLOC 0x80000000
194
195
196#define NAND_CI_CHIPNR_MSK 0x03
197#define NAND_CI_CELLTYPE_MSK 0x0C
198#define NAND_CI_CELLTYPE_SHIFT 2
199
200
201struct nand_chip;
202
203
204#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
205#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
206
207
208#define ONFI_TIMING_MODE_0 (1 << 0)
209#define ONFI_TIMING_MODE_1 (1 << 1)
210#define ONFI_TIMING_MODE_2 (1 << 2)
211#define ONFI_TIMING_MODE_3 (1 << 3)
212#define ONFI_TIMING_MODE_4 (1 << 4)
213#define ONFI_TIMING_MODE_5 (1 << 5)
214#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
215
216
217#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
218
219
220#define ONFI_FEATURE_ADDR_READ_RETRY 0x89
221
222
223#define ONFI_SUBFEATURE_PARAM_LEN 4
224
225
226#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
227
228struct nand_onfi_params {
229
230
231 u8 sig[4];
232 __le16 revision;
233 __le16 features;
234 __le16 opt_cmd;
235 u8 reserved0[2];
236 __le16 ext_param_page_length;
237 u8 num_of_param_pages;
238 u8 reserved1[17];
239
240
241 char manufacturer[12];
242 char model[20];
243 u8 jedec_id;
244 __le16 date_code;
245 u8 reserved2[13];
246
247
248 __le32 byte_per_page;
249 __le16 spare_bytes_per_page;
250 __le32 data_bytes_per_ppage;
251 __le16 spare_bytes_per_ppage;
252 __le32 pages_per_block;
253 __le32 blocks_per_lun;
254 u8 lun_count;
255 u8 addr_cycles;
256 u8 bits_per_cell;
257 __le16 bb_per_lun;
258 __le16 block_endurance;
259 u8 guaranteed_good_blocks;
260 __le16 guaranteed_block_endurance;
261 u8 programs_per_page;
262 u8 ppage_attr;
263 u8 ecc_bits;
264 u8 interleaved_bits;
265 u8 interleaved_ops;
266 u8 reserved3[13];
267
268
269 u8 io_pin_capacitance_max;
270 __le16 async_timing_mode;
271 __le16 program_cache_timing_mode;
272 __le16 t_prog;
273 __le16 t_bers;
274 __le16 t_r;
275 __le16 t_ccs;
276 __le16 src_sync_timing_mode;
277 __le16 src_ssync_features;
278 __le16 clk_pin_capacitance_typ;
279 __le16 io_pin_capacitance_typ;
280 __le16 input_pin_capacitance_typ;
281 u8 input_pin_capacitance_max;
282 u8 driver_strength_support;
283 __le16 t_int_r;
284 __le16 t_ald;
285 u8 reserved4[7];
286
287
288 __le16 vendor_revision;
289 u8 vendor[88];
290
291 __le16 crc;
292} __packed;
293
294#define ONFI_CRC_BASE 0x4F4E
295
296
297struct onfi_ext_ecc_info {
298 u8 ecc_bits;
299 u8 codeword_size;
300 __le16 bb_per_lun;
301 __le16 block_endurance;
302 u8 reserved[2];
303} __packed;
304
305#define ONFI_SECTION_TYPE_0 0
306#define ONFI_SECTION_TYPE_1 1
307#define ONFI_SECTION_TYPE_2 2
308struct onfi_ext_section {
309 u8 type;
310 u8 length;
311} __packed;
312
313#define ONFI_EXT_SECTION_MAX 8
314
315
316struct onfi_ext_param_page {
317 __le16 crc;
318 u8 sig[4];
319 u8 reserved0[10];
320 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
321
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327
328} __packed;
329
330struct nand_onfi_vendor_micron {
331 u8 two_plane_read;
332 u8 read_cache;
333 u8 read_unique_id;
334 u8 dq_imped;
335 u8 dq_imped_num_settings;
336 u8 dq_imped_feat_addr;
337 u8 rb_pulldown_strength;
338 u8 rb_pulldown_strength_feat_addr;
339 u8 rb_pulldown_strength_num_settings;
340 u8 otp_mode;
341 u8 otp_page_start;
342 u8 otp_data_prot_addr;
343 u8 otp_num_pages;
344 u8 otp_feat_addr;
345 u8 read_retry_options;
346 u8 reserved[72];
347 u8 param_revision;
348} __packed;
349
350struct jedec_ecc_info {
351 u8 ecc_bits;
352 u8 codeword_size;
353 __le16 bb_per_lun;
354 __le16 block_endurance;
355 u8 reserved[2];
356} __packed;
357
358
359#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
360
361struct nand_jedec_params {
362
363
364 u8 sig[4];
365 __le16 revision;
366 __le16 features;
367 u8 opt_cmd[3];
368 __le16 sec_cmd;
369 u8 num_of_param_pages;
370 u8 reserved0[18];
371
372
373 char manufacturer[12];
374 char model[20];
375 u8 jedec_id[6];
376 u8 reserved1[10];
377
378
379 __le32 byte_per_page;
380 __le16 spare_bytes_per_page;
381 u8 reserved2[6];
382 __le32 pages_per_block;
383 __le32 blocks_per_lun;
384 u8 lun_count;
385 u8 addr_cycles;
386 u8 bits_per_cell;
387 u8 programs_per_page;
388 u8 multi_plane_addr;
389 u8 multi_plane_op_attr;
390 u8 reserved3[38];
391
392
393 __le16 async_sdr_speed_grade;
394 __le16 toggle_ddr_speed_grade;
395 __le16 sync_ddr_speed_grade;
396 u8 async_sdr_features;
397 u8 toggle_ddr_features;
398 u8 sync_ddr_features;
399 __le16 t_prog;
400 __le16 t_bers;
401 __le16 t_r;
402 __le16 t_r_multi_plane;
403 __le16 t_ccs;
404 __le16 io_pin_capacitance_typ;
405 __le16 input_pin_capacitance_typ;
406 __le16 clk_pin_capacitance_typ;
407 u8 driver_strength_support;
408 __le16 t_ald;
409 u8 reserved4[36];
410
411
412 u8 guaranteed_good_blocks;
413 __le16 guaranteed_block_endurance;
414 struct jedec_ecc_info ecc_info[4];
415 u8 reserved5[29];
416
417
418 u8 reserved6[148];
419
420
421 __le16 vendor_rev_num;
422 u8 reserved7[88];
423
424
425 __le16 crc;
426} __packed;
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435
436struct nand_hw_control {
437 spinlock_t lock;
438 struct nand_chip *active;
439 wait_queue_head_t wq;
440};
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486struct nand_ecc_ctrl {
487 nand_ecc_modes_t mode;
488 int steps;
489 int size;
490 int bytes;
491 int total;
492 int strength;
493 int prepad;
494 int postpad;
495 struct nand_ecclayout *layout;
496 void *priv;
497 void (*hwctl)(struct mtd_info *mtd, int mode);
498 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
499 uint8_t *ecc_code);
500 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
501 uint8_t *calc_ecc);
502 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
503 uint8_t *buf, int oob_required, int page);
504 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
505 const uint8_t *buf, int oob_required);
506 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
507 uint8_t *buf, int oob_required, int page);
508 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
509 uint32_t offs, uint32_t len, uint8_t *buf, int page);
510 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
511 uint32_t offset, uint32_t data_len,
512 const uint8_t *data_buf, int oob_required);
513 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
514 const uint8_t *buf, int oob_required);
515 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
516 int page);
517 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
518 int page);
519 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
520 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
521 int page);
522};
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532
533struct nand_buffers {
534 uint8_t *ecccalc;
535 uint8_t *ecccode;
536 uint8_t *databuf;
537};
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643struct nand_chip {
644 void __iomem *IO_ADDR_R;
645 void __iomem *IO_ADDR_W;
646
647 uint8_t (*read_byte)(struct mtd_info *mtd);
648 u16 (*read_word)(struct mtd_info *mtd);
649 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
650 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
651 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
652 void (*select_chip)(struct mtd_info *mtd, int chip);
653 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
654 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
655 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
656 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
657 u8 *id_data);
658 int (*dev_ready)(struct mtd_info *mtd);
659 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
660 int page_addr);
661 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
662 int (*erase)(struct mtd_info *mtd, int page);
663 int (*scan_bbt)(struct mtd_info *mtd);
664 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
665 int status, int page);
666 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
667 uint32_t offset, int data_len, const uint8_t *buf,
668 int oob_required, int page, int cached, int raw);
669 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
670 int feature_addr, uint8_t *subfeature_para);
671 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
672 int feature_addr, uint8_t *subfeature_para);
673 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
674
675 int chip_delay;
676 unsigned int options;
677 unsigned int bbt_options;
678
679 int page_shift;
680 int phys_erase_shift;
681 int bbt_erase_shift;
682 int chip_shift;
683 int numchips;
684 uint64_t chipsize;
685 int pagemask;
686 int pagebuf;
687 unsigned int pagebuf_bitflips;
688 int subpagesize;
689 uint8_t bits_per_cell;
690 uint16_t ecc_strength_ds;
691 uint16_t ecc_step_ds;
692 int onfi_timing_mode_default;
693 int badblockpos;
694 int badblockbits;
695
696 int onfi_version;
697 int jedec_version;
698 union {
699 struct nand_onfi_params onfi_params;
700 struct nand_jedec_params jedec_params;
701 };
702
703 int read_retries;
704
705 flstate_t state;
706
707 uint8_t *oob_poi;
708 struct nand_hw_control *controller;
709
710 struct nand_ecc_ctrl ecc;
711 struct nand_buffers *buffers;
712 struct nand_hw_control hwcontrol;
713
714 uint8_t *bbt;
715 struct nand_bbt_descr *bbt_td;
716 struct nand_bbt_descr *bbt_md;
717
718 struct nand_bbt_descr *badblock_pattern;
719
720 void *priv;
721};
722
723
724
725
726#define NAND_MFR_TOSHIBA 0x98
727#define NAND_MFR_SAMSUNG 0xec
728#define NAND_MFR_FUJITSU 0x04
729#define NAND_MFR_NATIONAL 0x8f
730#define NAND_MFR_RENESAS 0x07
731#define NAND_MFR_STMICRO 0x20
732#define NAND_MFR_HYNIX 0xad
733#define NAND_MFR_MICRON 0x2c
734#define NAND_MFR_AMD 0x01
735#define NAND_MFR_MACRONIX 0xc2
736#define NAND_MFR_EON 0x92
737#define NAND_MFR_SANDISK 0x45
738#define NAND_MFR_INTEL 0x89
739#define NAND_MFR_ATO 0x9b
740
741
742#define NAND_MAX_ID_LEN 8
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748
749#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
750 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
751 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
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763#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
764 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
765 .options = (opts) }
766
767#define NAND_ECC_INFO(_strength, _step) \
768 { .strength_ds = (_strength), .step_ds = (_step) }
769#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
770#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
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801struct nand_flash_dev {
802 char *name;
803 union {
804 struct {
805 uint8_t mfr_id;
806 uint8_t dev_id;
807 };
808 uint8_t id[NAND_MAX_ID_LEN];
809 };
810 unsigned int pagesize;
811 unsigned int chipsize;
812 unsigned int erasesize;
813 unsigned int options;
814 uint16_t id_len;
815 uint16_t oobsize;
816 struct {
817 uint16_t strength_ds;
818 uint16_t step_ds;
819 } ecc;
820 int onfi_timing_mode_default;
821};
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828struct nand_manufacturers {
829 int id;
830 char *name;
831};
832
833extern struct nand_flash_dev nand_flash_ids[];
834extern struct nand_manufacturers nand_manuf_ids[];
835
836extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
837extern int nand_default_bbt(struct mtd_info *mtd);
838extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
839extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
840extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
841extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
842 int allowbbt);
843extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
844 size_t *retlen, uint8_t *buf);
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858struct platform_nand_chip {
859 int nr_chips;
860 int chip_offset;
861 int nr_partitions;
862 struct mtd_partition *partitions;
863 struct nand_ecclayout *ecclayout;
864 int chip_delay;
865 unsigned int options;
866 unsigned int bbt_options;
867 const char **part_probe_types;
868};
869
870
871struct platform_device;
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889struct platform_nand_ctrl {
890 int (*probe)(struct platform_device *pdev);
891 void (*remove)(struct platform_device *pdev);
892 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
893 int (*dev_ready)(struct mtd_info *mtd);
894 void (*select_chip)(struct mtd_info *mtd, int chip);
895 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
896 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
897 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
898 unsigned char (*read_byte)(struct mtd_info *mtd);
899 void *priv;
900};
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907struct platform_nand_data {
908 struct platform_nand_chip chip;
909 struct platform_nand_ctrl ctrl;
910};
911
912
913static inline
914struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
915{
916 struct nand_chip *chip = mtd->priv;
917
918 return chip->priv;
919}
920
921
922static inline int onfi_feature(struct nand_chip *chip)
923{
924 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
925}
926
927
928static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
929{
930 if (!chip->onfi_version)
931 return ONFI_TIMING_MODE_UNKNOWN;
932 return le16_to_cpu(chip->onfi_params.async_timing_mode);
933}
934
935
936static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
937{
938 if (!chip->onfi_version)
939 return ONFI_TIMING_MODE_UNKNOWN;
940 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
941}
942
943
944
945
946
947
948static inline bool nand_is_slc(struct nand_chip *chip)
949{
950 return chip->bits_per_cell == 1;
951}
952
953
954
955
956
957static inline int nand_opcode_8bits(unsigned int command)
958{
959 switch (command) {
960 case NAND_CMD_READID:
961 case NAND_CMD_PARAM:
962 case NAND_CMD_GET_FEATURES:
963 case NAND_CMD_SET_FEATURES:
964 return 1;
965 default:
966 break;
967 }
968 return 0;
969}
970
971
972static inline int jedec_feature(struct nand_chip *chip)
973{
974 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
975 : 0;
976}
977
978
979
980
981
982
983
984
985
986
987
988
989
990struct nand_sdr_timings {
991 u32 tALH_min;
992 u32 tADL_min;
993 u32 tALS_min;
994 u32 tAR_min;
995 u32 tCEA_max;
996 u32 tCEH_min;
997 u32 tCH_min;
998 u32 tCHZ_max;
999 u32 tCLH_min;
1000 u32 tCLR_min;
1001 u32 tCLS_min;
1002 u32 tCOH_min;
1003 u32 tCS_min;
1004 u32 tDH_min;
1005 u32 tDS_min;
1006 u32 tFEAT_max;
1007 u32 tIR_min;
1008 u32 tITC_max;
1009 u32 tRC_min;
1010 u32 tREA_max;
1011 u32 tREH_min;
1012 u32 tRHOH_min;
1013 u32 tRHW_min;
1014 u32 tRHZ_max;
1015 u32 tRLOH_min;
1016 u32 tRP_min;
1017 u32 tRR_min;
1018 u64 tRST_max;
1019 u32 tWB_max;
1020 u32 tWC_min;
1021 u32 tWH_min;
1022 u32 tWHR_min;
1023 u32 tWP_min;
1024 u32 tWW_min;
1025};
1026
1027
1028const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1029#endif
1030