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22#ifndef __SOUND_EMU10K1_H
23#define __SOUND_EMU10K1_H
24
25
26#include <sound/pcm.h>
27#include <sound/rawmidi.h>
28#include <sound/hwdep.h>
29#include <sound/ac97_codec.h>
30#include <sound/util_mem.h>
31#include <sound/pcm-indirect.h>
32#include <sound/timer.h>
33#include <linux/interrupt.h>
34#include <linux/mutex.h>
35#include <linux/firmware.h>
36#include <linux/io.h>
37
38#include <uapi/sound/emu10k1.h>
39
40
41
42#define EMUPAGESIZE 4096
43#define MAXREQVOICES 8
44#define MAXPAGES 8192
45#define RESERVED 0
46#define NUM_MIDI 16
47#define NUM_G 64
48#define NUM_FXSENDS 4
49#define NUM_EFX_PLAYBACK 16
50
51
52#define EMU10K1_DMA_MASK 0x7fffffffUL
53#define AUDIGY_DMA_MASK 0x7fffffffUL
54
55
56#define TMEMSIZE 256*1024
57#define TMEMSIZEREG 4
58
59#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
60
61
62
63
64
65
66
67#define PTR 0x00
68
69
70#define PTR_CHANNELNUM_MASK 0x0000003f
71
72
73
74#define PTR_ADDRESS_MASK 0x07ff0000
75#define A_PTR_ADDRESS_MASK 0x0fff0000
76
77#define DATA 0x04
78
79#define IPR 0x08
80
81
82#define IPR_P16V 0x80000000
83
84#define IPR_GPIOMSG 0x20000000
85
86
87
88#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000
89#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000
90
91#define IPR_SPDIFBUFFULL 0x04000000
92#define IPR_SPDIFBUFHALFFULL 0x02000000
93
94#define IPR_SAMPLERATETRACKER 0x01000000
95#define IPR_FXDSP 0x00800000
96#define IPR_FORCEINT 0x00400000
97#define IPR_PCIERROR 0x00200000
98#define IPR_VOLINCR 0x00100000
99#define IPR_VOLDECR 0x00080000
100#define IPR_MUTE 0x00040000
101#define IPR_MICBUFFULL 0x00020000
102#define IPR_MICBUFHALFFULL 0x00010000
103#define IPR_ADCBUFFULL 0x00008000
104#define IPR_ADCBUFHALFFULL 0x00004000
105#define IPR_EFXBUFFULL 0x00002000
106#define IPR_EFXBUFHALFFULL 0x00001000
107#define IPR_GPSPDIFSTATUSCHANGE 0x00000800
108#define IPR_CDROMSTATUSCHANGE 0x00000400
109#define IPR_INTERVALTIMER 0x00000200
110#define IPR_MIDITRANSBUFEMPTY 0x00000100
111#define IPR_MIDIRECVBUFEMPTY 0x00000080
112#define IPR_CHANNELLOOP 0x00000040
113#define IPR_CHANNELNUMBERMASK 0x0000003f
114
115
116
117
118
119#define INTE 0x0c
120#define INTE_VIRTUALSB_MASK 0xc0000000
121#define INTE_VIRTUALSB_220 0x00000000
122#define INTE_VIRTUALSB_240 0x40000000
123#define INTE_VIRTUALSB_260 0x80000000
124#define INTE_VIRTUALSB_280 0xc0000000
125#define INTE_VIRTUALMPU_MASK 0x30000000
126#define INTE_VIRTUALMPU_300 0x00000000
127#define INTE_VIRTUALMPU_310 0x10000000
128#define INTE_VIRTUALMPU_320 0x20000000
129#define INTE_VIRTUALMPU_330 0x30000000
130#define INTE_MASTERDMAENABLE 0x08000000
131#define INTE_SLAVEDMAENABLE 0x04000000
132#define INTE_MASTERPICENABLE 0x02000000
133#define INTE_SLAVEPICENABLE 0x01000000
134#define INTE_VSBENABLE 0x00800000
135#define INTE_ADLIBENABLE 0x00400000
136#define INTE_MPUENABLE 0x00200000
137#define INTE_FORCEINT 0x00100000
138
139#define INTE_MRHANDENABLE 0x00080000
140
141
142
143
144
145
146#define INTE_A_MIDITXENABLE2 0x00020000
147#define INTE_A_MIDIRXENABLE2 0x00010000
148
149
150#define INTE_SAMPLERATETRACKER 0x00002000
151
152#define INTE_FXDSPENABLE 0x00001000
153#define INTE_PCIERRORENABLE 0x00000800
154#define INTE_VOLINCRENABLE 0x00000400
155#define INTE_VOLDECRENABLE 0x00000200
156#define INTE_MUTEENABLE 0x00000100
157#define INTE_MICBUFENABLE 0x00000080
158#define INTE_ADCBUFENABLE 0x00000040
159#define INTE_EFXBUFENABLE 0x00000020
160#define INTE_GPSPDIFENABLE 0x00000010
161#define INTE_CDSPDIFENABLE 0x00000008
162#define INTE_INTERVALTIMERENB 0x00000004
163#define INTE_MIDITXENABLE 0x00000002
164#define INTE_MIDIRXENABLE 0x00000001
165
166#define WC 0x10
167#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0
168#define WC_SAMPLECOUNTER 0x14060010
169#define WC_CURRENTCHANNEL 0x0000003F
170
171
172
173#define HCFG 0x14
174
175
176
177
178#define HCFG_LEGACYFUNC_MASK 0xe0000000
179#define HCFG_LEGACYFUNC_MPU 0x00000000
180#define HCFG_LEGACYFUNC_SB 0x40000000
181#define HCFG_LEGACYFUNC_AD 0x60000000
182#define HCFG_LEGACYFUNC_MPIC 0x80000000
183#define HCFG_LEGACYFUNC_MDMA 0xa0000000
184#define HCFG_LEGACYFUNC_SPCI 0xc0000000
185#define HCFG_LEGACYFUNC_SDMA 0xe0000000
186#define HCFG_IOCAPTUREADDR 0x1f000000
187#define HCFG_LEGACYWRITE 0x00800000
188#define HCFG_LEGACYWORD 0x00400000
189#define HCFG_LEGACYINT 0x00200000
190
191
192#define HCFG_PUSH_BUTTON_ENABLE 0x00100000
193#define HCFG_BAUD_RATE 0x00080000
194#define HCFG_EXPANDED_MEM 0x00040000
195#define HCFG_CODECFORMAT_MASK 0x00030000
196
197
198#define HCFG_CODECFORMAT_AC97_1 0x00000000
199#define HCFG_CODECFORMAT_AC97_2 0x00010000
200#define HCFG_AUTOMUTE_ASYNC 0x00008000
201
202
203
204#define HCFG_AUTOMUTE_SPDIF 0x00004000
205
206
207#define HCFG_EMU32_SLAVE 0x00002000
208#define HCFG_SLOW_RAMP 0x00001000
209
210#define HCFG_PHASE_TRACK_MASK 0x00000700
211
212
213#define HCFG_I2S_ASRC_ENABLE 0x00000070
214
215
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217
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219
220
221#define HCFG_CODECFORMAT_AC97 0x00000000
222#define HCFG_CODECFORMAT_I2S 0x00010000
223#define HCFG_GPINPUT0 0x00004000
224#define HCFG_GPINPUT1 0x00002000
225#define HCFG_GPOUTPUT_MASK 0x00001c00
226#define HCFG_GPOUT0 0x00001000
227#define HCFG_GPOUT1 0x00000800
228#define HCFG_GPOUT2 0x00000400
229#define HCFG_JOYENABLE 0x00000200
230#define HCFG_PHASETRACKENABLE 0x00000100
231
232
233#define HCFG_AC3ENABLE_MASK 0x000000e0
234#define HCFG_AC3ENABLE_ZVIDEO 0x00000080
235#define HCFG_AC3ENABLE_CDSPDIF 0x00000040
236#define HCFG_AC3ENABLE_GPSPDIF 0x00000020
237#define HCFG_AUTOMUTE 0x00000010
238
239
240
241#define HCFG_LOCKSOUNDCACHE 0x00000008
242
243#define HCFG_LOCKTANKCACHE_MASK 0x00000004
244
245#define HCFG_LOCKTANKCACHE 0x01020014
246#define HCFG_MUTEBUTTONENABLE 0x00000002
247
248
249
250
251
252#define HCFG_AUDIOENABLE 0x00000001
253
254
255
256
257
258#define MUDATA 0x18
259
260#define MUCMD 0x19
261#define MUCMD_RESET 0xff
262#define MUCMD_ENTERUARTMODE 0x3f
263
264
265#define MUSTAT MUCMD
266#define MUSTAT_IRDYN 0x80
267#define MUSTAT_ORDYN 0x40
268
269#define A_IOCFG 0x18
270#define A_GPINPUT_MASK 0xff00
271#define A_GPOUTPUT_MASK 0x00ff
272
273
274#define A_IOCFG_GPOUT0 0x0044
275#define A_IOCFG_DISABLE_ANALOG 0x0040
276#define A_IOCFG_ENABLE_DIGITAL 0x0004
277#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
278#define A_IOCFG_UNKNOWN_20 0x0020
279#define A_IOCFG_DISABLE_AC97_FRONT 0x0080
280#define A_IOCFG_GPOUT1 0x0002
281#define A_IOCFG_GPOUT2 0x0001
282#define A_IOCFG_MULTIPURPOSE_JACK 0x2000
283
284#define A_IOCFG_DIGITAL_JACK 0x1000
285#define A_IOCFG_FRONT_JACK 0x4000
286#define A_IOCFG_REAR_JACK 0x8000
287#define A_IOCFG_PHONES_JACK 0x0100
288
289
290
291
292
293
294
295#define TIMER 0x1a
296
297
298
299#define TIMER_RATE_MASK 0x000003ff
300
301#define TIMER_RATE 0x0a00001a
302
303#define AC97DATA 0x1c
304
305#define AC97ADDRESS 0x1e
306#define AC97ADDRESS_READY 0x80
307#define AC97ADDRESS_ADDRESS 0x7f
308
309
310#define PTR2 0x20
311#define DATA2 0x24
312#define IPR2 0x28
313#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000
314#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
315#define IPR2_CAPTURE_CH_0_LOOP 0x00100000
316#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000
317
318
319
320#define INTE2 0x2c
321#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000
322#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
323#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000
324#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200
325#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000
326#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400
327#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000
328#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800
329#define INTE2_CAPTURE_CH_0_LOOP 0x00100000
330#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000
331#define HCFG2 0x34
332
333
334
335
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337
338
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340
341
342
343
344
345
346
347#define IPR3 0x38
348#define INTE3 0x3c
349
350
351
352
353#define JOYSTICK1 0x00
354#define JOYSTICK2 0x01
355#define JOYSTICK3 0x02
356#define JOYSTICK4 0x03
357#define JOYSTICK5 0x04
358#define JOYSTICK6 0x05
359#define JOYSTICK7 0x06
360#define JOYSTICK8 0x07
361
362
363
364#define JOYSTICK_BUTTONS 0x0f
365#define JOYSTICK_COMPARATOR 0xf0
366
367
368
369
370
371
372#define CPF 0x00
373#define CPF_CURRENTPITCH_MASK 0xffff0000
374#define CPF_CURRENTPITCH 0x10100000
375#define CPF_STEREO_MASK 0x00008000
376#define CPF_STOP_MASK 0x00004000
377#define CPF_FRACADDRESS_MASK 0x00003fff
378
379#define PTRX 0x01
380#define PTRX_PITCHTARGET_MASK 0xffff0000
381#define PTRX_PITCHTARGET 0x10100001
382#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
383#define PTRX_FXSENDAMOUNT_A 0x08080001
384#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
385#define PTRX_FXSENDAMOUNT_B 0x08000001
386
387#define CVCF 0x02
388#define CVCF_CURRENTVOL_MASK 0xffff0000
389#define CVCF_CURRENTVOL 0x10100002
390#define CVCF_CURRENTFILTER_MASK 0x0000ffff
391#define CVCF_CURRENTFILTER 0x10000002
392
393#define VTFT 0x03
394#define VTFT_VOLUMETARGET_MASK 0xffff0000
395#define VTFT_VOLUMETARGET 0x10100003
396#define VTFT_FILTERTARGET_MASK 0x0000ffff
397#define VTFT_FILTERTARGET 0x10000003
398
399#define Z1 0x05
400
401#define Z2 0x04
402
403#define PSST 0x06
404#define PSST_FXSENDAMOUNT_C_MASK 0xff000000
405
406#define PSST_FXSENDAMOUNT_C 0x08180006
407
408#define PSST_LOOPSTARTADDR_MASK 0x00ffffff
409#define PSST_LOOPSTARTADDR 0x18000006
410
411#define DSL 0x07
412#define DSL_FXSENDAMOUNT_D_MASK 0xff000000
413
414#define DSL_FXSENDAMOUNT_D 0x08180007
415
416#define DSL_LOOPENDADDR_MASK 0x00ffffff
417#define DSL_LOOPENDADDR 0x18000007
418
419#define CCCA 0x08
420#define CCCA_RESONANCE 0xf0000000
421#define CCCA_INTERPROMMASK 0x0e000000
422
423
424
425
426
427#define CCCA_INTERPROM_0 0x00000000
428#define CCCA_INTERPROM_1 0x02000000
429#define CCCA_INTERPROM_2 0x04000000
430#define CCCA_INTERPROM_3 0x06000000
431#define CCCA_INTERPROM_4 0x08000000
432#define CCCA_INTERPROM_5 0x0a000000
433#define CCCA_INTERPROM_6 0x0c000000
434#define CCCA_INTERPROM_7 0x0e000000
435#define CCCA_8BITSELECT 0x01000000
436#define CCCA_CURRADDR_MASK 0x00ffffff
437#define CCCA_CURRADDR 0x18000008
438
439#define CCR 0x09
440#define CCR_CACHEINVALIDSIZE 0x07190009
441#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000
442#define CCR_CACHELOOPFLAG 0x01000000
443#define CCR_INTERLEAVEDSAMPLES 0x00800000
444#define CCR_WORDSIZEDSAMPLES 0x00400000
445#define CCR_READADDRESS 0x06100009
446#define CCR_READADDRESS_MASK 0x003f0000
447#define CCR_LOOPINVALSIZE 0x0000fe00
448
449#define CCR_LOOPFLAG 0x00000100
450#define CCR_CACHELOOPADDRHI 0x000000ff
451
452#define CLP 0x0a
453
454#define CLP_CACHELOOPADDR 0x0000ffff
455
456#define FXRT 0x0b
457
458
459#define FXRT_CHANNELA 0x000f0000
460#define FXRT_CHANNELB 0x00f00000
461#define FXRT_CHANNELC 0x0f000000
462#define FXRT_CHANNELD 0xf0000000
463
464#define A_HR 0x0b
465#define MAPA 0x0c
466
467#define MAPB 0x0d
468
469#define MAP_PTE_MASK 0xffffe000
470#define MAP_PTI_MASK 0x00001fff
471
472
473
474#define ENVVOL 0x10
475#define ENVVOL_MASK 0x0000ffff
476
477
478#define ATKHLDV 0x11
479#define ATKHLDV_PHASE0 0x00008000
480#define ATKHLDV_HOLDTIME_MASK 0x00007f00
481#define ATKHLDV_ATTACKTIME_MASK 0x0000007f
482
483
484#define DCYSUSV 0x12
485#define DCYSUSV_PHASE1_MASK 0x00008000
486#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00
487#define DCYSUSV_CHANNELENABLE_MASK 0x00000080
488
489
490#define DCYSUSV_DECAYTIME_MASK 0x0000007f
491
492
493#define LFOVAL1 0x13
494#define LFOVAL_MASK 0x0000ffff
495
496
497#define ENVVAL 0x14
498#define ENVVAL_MASK 0x0000ffff
499
500
501#define ATKHLDM 0x15
502#define ATKHLDM_PHASE0 0x00008000
503#define ATKHLDM_HOLDTIME 0x00007f00
504#define ATKHLDM_ATTACKTIME 0x0000007f
505
506
507#define DCYSUSM 0x16
508#define DCYSUSM_PHASE1_MASK 0x00008000
509#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00
510#define DCYSUSM_DECAYTIME_MASK 0x0000007f
511
512
513#define LFOVAL2 0x17
514#define LFOVAL2_MASK 0x0000ffff
515
516
517#define IP 0x18
518#define IP_MASK 0x0000ffff
519
520#define IP_UNITY 0x0000e000
521
522#define IFATN 0x19
523#define IFATN_FILTERCUTOFF_MASK 0x0000ff00
524
525
526#define IFATN_FILTERCUTOFF 0x08080019
527#define IFATN_ATTENUATION_MASK 0x000000ff
528#define IFATN_ATTENUATION 0x08000019
529
530
531#define PEFE 0x1a
532#define PEFE_PITCHAMOUNT_MASK 0x0000ff00
533
534#define PEFE_PITCHAMOUNT 0x0808001a
535#define PEFE_FILTERAMOUNT_MASK 0x000000ff
536
537#define PEFE_FILTERAMOUNT 0x0800001a
538#define FMMOD 0x1b
539#define FMMOD_MODVIBRATO 0x0000ff00
540
541#define FMMOD_MOFILTER 0x000000ff
542
543
544
545#define TREMFRQ 0x1c
546#define TREMFRQ_DEPTH 0x0000ff00
547
548
549#define TREMFRQ_FREQUENCY 0x000000ff
550
551#define FM2FRQ2 0x1d
552#define FM2FRQ2_DEPTH 0x0000ff00
553
554#define FM2FRQ2_FREQUENCY 0x000000ff
555
556
557#define TEMPENV 0x1e
558#define TEMPENV_MASK 0x0000ffff
559
560
561
562
563
564#define CD0 0x20
565#define CD1 0x21
566#define CD2 0x22
567#define CD3 0x23
568#define CD4 0x24
569#define CD5 0x25
570#define CD6 0x26
571#define CD7 0x27
572#define CD8 0x28
573#define CD9 0x29
574#define CDA 0x2a
575#define CDB 0x2b
576#define CDC 0x2c
577#define CDD 0x2d
578#define CDE 0x2e
579#define CDF 0x2f
580
581
582
583#define PTB 0x40
584#define PTB_MASK 0xfffff000
585
586#define TCB 0x41
587#define TCB_MASK 0xfffff000
588
589#define ADCCR 0x42
590#define ADCCR_RCHANENABLE 0x00000010
591#define ADCCR_LCHANENABLE 0x00000008
592
593
594#define A_ADCCR_RCHANENABLE 0x00000020
595#define A_ADCCR_LCHANENABLE 0x00000010
596
597#define A_ADCCR_SAMPLERATE_MASK 0x0000000F
598#define ADCCR_SAMPLERATE_MASK 0x00000007
599#define ADCCR_SAMPLERATE_48 0x00000000
600#define ADCCR_SAMPLERATE_44 0x00000001
601#define ADCCR_SAMPLERATE_32 0x00000002
602#define ADCCR_SAMPLERATE_24 0x00000003
603#define ADCCR_SAMPLERATE_22 0x00000004
604#define ADCCR_SAMPLERATE_16 0x00000005
605#define ADCCR_SAMPLERATE_11 0x00000006
606#define ADCCR_SAMPLERATE_8 0x00000007
607#define A_ADCCR_SAMPLERATE_12 0x00000006
608#define A_ADCCR_SAMPLERATE_11 0x00000007
609#define A_ADCCR_SAMPLERATE_8 0x00000008
610
611#define FXWC 0x43
612
613
614
615
616
617
618#define FXWC_DEFAULTROUTE_C (1<<0)
619#define FXWC_DEFAULTROUTE_B (1<<1)
620#define FXWC_DEFAULTROUTE_A (1<<12)
621#define FXWC_DEFAULTROUTE_D (1<<13)
622#define FXWC_ADCLEFT (1<<18)
623#define FXWC_CDROMSPDIFLEFT (1<<18)
624#define FXWC_ADCRIGHT (1<<19)
625#define FXWC_CDROMSPDIFRIGHT (1<<19)
626#define FXWC_MIC (1<<20)
627#define FXWC_ZOOMLEFT (1<<20)
628#define FXWC_ZOOMRIGHT (1<<21)
629#define FXWC_SPDIFLEFT (1<<22)
630#define FXWC_SPDIFRIGHT (1<<23)
631
632#define A_TBLSZ 0x43
633
634#define TCBS 0x44
635#define TCBS_MASK 0x00000007
636#define TCBS_BUFFSIZE_16K 0x00000000
637#define TCBS_BUFFSIZE_32K 0x00000001
638#define TCBS_BUFFSIZE_64K 0x00000002
639#define TCBS_BUFFSIZE_128K 0x00000003
640#define TCBS_BUFFSIZE_256K 0x00000004
641#define TCBS_BUFFSIZE_512K 0x00000005
642#define TCBS_BUFFSIZE_1024K 0x00000006
643#define TCBS_BUFFSIZE_2048K 0x00000007
644
645#define MICBA 0x45
646#define MICBA_MASK 0xfffff000
647
648#define ADCBA 0x46
649#define ADCBA_MASK 0xfffff000
650
651#define FXBA 0x47
652#define FXBA_MASK 0xfffff000
653
654#define A_HWM 0x48
655
656#define MICBS 0x49
657
658#define ADCBS 0x4a
659
660#define FXBS 0x4b
661
662
663
664
665#define ADCBS_BUFSIZE_NONE 0x00000000
666#define ADCBS_BUFSIZE_384 0x00000001
667#define ADCBS_BUFSIZE_448 0x00000002
668#define ADCBS_BUFSIZE_512 0x00000003
669#define ADCBS_BUFSIZE_640 0x00000004
670#define ADCBS_BUFSIZE_768 0x00000005
671#define ADCBS_BUFSIZE_896 0x00000006
672#define ADCBS_BUFSIZE_1024 0x00000007
673#define ADCBS_BUFSIZE_1280 0x00000008
674#define ADCBS_BUFSIZE_1536 0x00000009
675#define ADCBS_BUFSIZE_1792 0x0000000a
676#define ADCBS_BUFSIZE_2048 0x0000000b
677#define ADCBS_BUFSIZE_2560 0x0000000c
678#define ADCBS_BUFSIZE_3072 0x0000000d
679#define ADCBS_BUFSIZE_3584 0x0000000e
680#define ADCBS_BUFSIZE_4096 0x0000000f
681#define ADCBS_BUFSIZE_5120 0x00000010
682#define ADCBS_BUFSIZE_6144 0x00000011
683#define ADCBS_BUFSIZE_7168 0x00000012
684#define ADCBS_BUFSIZE_8192 0x00000013
685#define ADCBS_BUFSIZE_10240 0x00000014
686#define ADCBS_BUFSIZE_12288 0x00000015
687#define ADCBS_BUFSIZE_14366 0x00000016
688#define ADCBS_BUFSIZE_16384 0x00000017
689#define ADCBS_BUFSIZE_20480 0x00000018
690#define ADCBS_BUFSIZE_24576 0x00000019
691#define ADCBS_BUFSIZE_28672 0x0000001a
692#define ADCBS_BUFSIZE_32768 0x0000001b
693#define ADCBS_BUFSIZE_40960 0x0000001c
694#define ADCBS_BUFSIZE_49152 0x0000001d
695#define ADCBS_BUFSIZE_57344 0x0000001e
696#define ADCBS_BUFSIZE_65536 0x0000001f
697
698
699#define A_CSBA 0x4c
700
701
702#define A_CSDC 0x4d
703
704
705#define A_CSFE 0x4e
706
707
708#define A_CSHG 0x4f
709
710
711#define CDCS 0x50
712
713#define GPSCS 0x51
714
715#define DBG 0x52
716
717
718#define A_SPSC 0x52
719
720#define REG53 0x53
721
722#define A_DBG 0x53
723#define A_DBG_SINGLE_STEP 0x00020000
724#define A_DBG_ZC 0x40000000
725#define A_DBG_STEP_ADDR 0x000003ff
726#define A_DBG_SATURATION_OCCURED 0x20000000
727#define A_DBG_SATURATION_ADDR 0x0ffc0000
728
729
730#define SPCS0 0x54
731
732#define SPCS1 0x55
733
734#define SPCS2 0x56
735
736#define SPCS_CLKACCYMASK 0x30000000
737#define SPCS_CLKACCY_1000PPM 0x00000000
738#define SPCS_CLKACCY_50PPM 0x10000000
739#define SPCS_CLKACCY_VARIABLE 0x20000000
740#define SPCS_SAMPLERATEMASK 0x0f000000
741#define SPCS_SAMPLERATE_44 0x00000000
742#define SPCS_SAMPLERATE_48 0x02000000
743#define SPCS_SAMPLERATE_32 0x03000000
744#define SPCS_CHANNELNUMMASK 0x00f00000
745#define SPCS_CHANNELNUM_UNSPEC 0x00000000
746#define SPCS_CHANNELNUM_LEFT 0x00100000
747#define SPCS_CHANNELNUM_RIGHT 0x00200000
748#define SPCS_SOURCENUMMASK 0x000f0000
749#define SPCS_SOURCENUM_UNSPEC 0x00000000
750#define SPCS_GENERATIONSTATUS 0x00008000
751#define SPCS_CATEGORYCODEMASK 0x00007f00
752#define SPCS_MODEMASK 0x000000c0
753#define SPCS_EMPHASISMASK 0x00000038
754#define SPCS_EMPHASIS_NONE 0x00000000
755#define SPCS_EMPHASIS_50_15 0x00000008
756#define SPCS_COPYRIGHT 0x00000004
757#define SPCS_NOTAUDIODATA 0x00000002
758#define SPCS_PROFESSIONAL 0x00000001
759
760
761
762
763#define CLIEL 0x58
764
765#define CLIEH 0x59
766
767#define CLIPL 0x5a
768
769#define CLIPH 0x5b
770
771#define SOLEL 0x5c
772
773#define SOLEH 0x5d
774
775#define SPBYPASS 0x5e
776#define SPBYPASS_SPDIF0_MASK 0x00000003
777#define SPBYPASS_SPDIF1_MASK 0x0000000c
778
779#define SPBYPASS_FORMAT 0x00000f00
780
781#define AC97SLOT 0x5f
782#define AC97SLOT_REAR_RIGHT 0x01
783#define AC97SLOT_REAR_LEFT 0x02
784#define AC97SLOT_CNTR 0x10
785#define AC97SLOT_LFE 0x20
786
787
788#define A_PCB 0x5f
789
790
791#define CDSRCS 0x60
792
793#define GPSRCS 0x61
794
795#define ZVSRCS 0x62
796
797
798
799
800#define SRCS_SPDIFVALID 0x04000000
801#define SRCS_SPDIFLOCKED 0x02000000
802#define SRCS_RATELOCKED 0x01000000
803#define SRCS_ESTSAMPLERATE 0x0007ffff
804
805
806#define SRCS_SPDIFRATE_44 0x0003acd9
807#define SRCS_SPDIFRATE_48 0x00040000
808#define SRCS_SPDIFRATE_96 0x00080000
809
810#define MICIDX 0x63
811#define MICIDX_MASK 0x0000ffff
812#define MICIDX_IDX 0x10000063
813
814#define ADCIDX 0x64
815#define ADCIDX_MASK 0x0000ffff
816#define ADCIDX_IDX 0x10000064
817
818#define A_ADCIDX 0x63
819#define A_ADCIDX_IDX 0x10000063
820
821#define A_MICIDX 0x64
822#define A_MICIDX_IDX 0x10000064
823
824#define FXIDX 0x65
825#define FXIDX_MASK 0x0000ffff
826#define FXIDX_IDX 0x10000065
827
828
829#define HLIEL 0x66
830
831#define HLIEH 0x67
832
833#define HLIPL 0x68
834
835#define HLIPH 0x69
836
837
838#define A_SPRI 0x6a
839
840#define A_SPRA 0x6b
841
842#define A_SPRC 0x6c
843
844#define A_DICE 0x6d
845
846#define A_TTB 0x6e
847
848#define A_TDOF 0x6f
849
850
851#define A_MUDATA1 0x70
852#define A_MUCMD1 0x71
853#define A_MUSTAT1 A_MUCMD1
854
855
856#define A_MUDATA2 0x72
857#define A_MUCMD2 0x73
858#define A_MUSTAT2 A_MUCMD2
859
860
861
862
863#define A_FXWC1 0x74
864#define A_FXWC2 0x75
865
866
867#define A_SPDIF_SAMPLERATE 0x76
868#define A_SAMPLE_RATE 0x76
869#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e
870#define A_SAMPLE_RATE_UNKNOWN 0xf0030001
871#define A_SPDIF_RATE_MASK 0x000000e0
872#define A_SPDIF_48000 0x00000000
873#define A_SPDIF_192000 0x00000020
874#define A_SPDIF_96000 0x00000040
875#define A_SPDIF_44100 0x00000080
876
877#define A_I2S_CAPTURE_RATE_MASK 0x00000e00
878#define A_I2S_CAPTURE_48000 0x00000000
879#define A_I2S_CAPTURE_192000 0x00000200
880#define A_I2S_CAPTURE_96000 0x00000400
881#define A_I2S_CAPTURE_44100 0x00000800
882
883#define A_PCM_RATE_MASK 0x0000e000
884#define A_PCM_48000 0x00000000
885#define A_PCM_192000 0x00002000
886#define A_PCM_96000 0x00004000
887#define A_PCM_44100 0x00008000
888
889
890#define A_SRT3 0x77
891
892
893#define A_SRT4 0x78
894
895
896#define A_SRT5 0x79
897
898
899
900#define A_TTDA 0x7a
901
902#define A_TTDD 0x7b
903
904#define A_FXRT2 0x7c
905#define A_FXRT_CHANNELE 0x0000003f
906#define A_FXRT_CHANNELF 0x00003f00
907#define A_FXRT_CHANNELG 0x003f0000
908#define A_FXRT_CHANNELH 0x3f000000
909
910#define A_SENDAMOUNTS 0x7d
911#define A_FXSENDAMOUNT_E_MASK 0xFF000000
912#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
913#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
914#define A_FXSENDAMOUNT_H_MASK 0x000000FF
915
916
917
918#define A_FXRT1 0x7e
919#define A_FXRT_CHANNELA 0x0000003f
920#define A_FXRT_CHANNELB 0x00003f00
921#define A_FXRT_CHANNELC 0x003f0000
922#define A_FXRT_CHANNELD 0x3f000000
923
924
925
926#define FXGPREGBASE 0x100
927#define A_FXGPREGBASE 0x400
928
929#define A_TANKMEMCTLREGBASE 0x100
930#define A_TANKMEMCTLREG_MASK 0x1f
931
932
933
934
935#define TANKMEMDATAREGBASE 0x200
936#define TANKMEMDATAREG_MASK 0x000fffff
937
938
939#define TANKMEMADDRREGBASE 0x300
940#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
941#define TANKMEMADDRREG_CLEAR 0x00800000
942#define TANKMEMADDRREG_ALIGN 0x00400000
943#define TANKMEMADDRREG_WRITE 0x00200000
944#define TANKMEMADDRREG_READ 0x00100000
945
946#define MICROCODEBASE 0x400
947
948
949
950#define LOWORD_OPX_MASK 0x000ffc00
951#define LOWORD_OPY_MASK 0x000003ff
952#define HIWORD_OPCODE_MASK 0x00f00000
953#define HIWORD_RESULT_MASK 0x000ffc00
954#define HIWORD_OPA_MASK 0x000003ff
955
956
957
958#define A_MICROCODEBASE 0x600
959#define A_LOWORD_OPY_MASK 0x000007ff
960#define A_LOWORD_OPX_MASK 0x007ff000
961#define A_HIWORD_OPCODE_MASK 0x0f000000
962#define A_HIWORD_RESULT_MASK 0x007ff000
963#define A_HIWORD_OPA_MASK 0x000007ff
964
965
966
967
968#define EMU_HANA_DESTHI 0x00
969#define EMU_HANA_DESTLO 0x01
970#define EMU_HANA_SRCHI 0x02
971#define EMU_HANA_SRCLO 0x03
972#define EMU_HANA_DOCK_PWR 0x04
973#define EMU_HANA_DOCK_PWR_ON 0x01
974#define EMU_HANA_WCLOCK 0x05
975
976
977#define EMU_HANA_WCLOCK_SRC_MASK 0x07
978#define EMU_HANA_WCLOCK_INT_48K 0x00
979#define EMU_HANA_WCLOCK_INT_44_1K 0x01
980#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
981#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
982#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
983#define EMU_HANA_WCLOCK_2ND_HANA 0x05
984#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
985#define EMU_HANA_WCLOCK_OFF 0x07
986#define EMU_HANA_WCLOCK_MULT_MASK 0x18
987#define EMU_HANA_WCLOCK_1X 0x00
988#define EMU_HANA_WCLOCK_2X 0x08
989#define EMU_HANA_WCLOCK_4X 0x10
990#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
991
992#define EMU_HANA_DEFCLOCK 0x06
993#define EMU_HANA_DEFCLOCK_48K 0x00
994#define EMU_HANA_DEFCLOCK_44_1K 0x01
995
996#define EMU_HANA_UNMUTE 0x07
997#define EMU_MUTE 0x00
998#define EMU_UNMUTE 0x01
999
1000#define EMU_HANA_FPGA_CONFIG 0x08
1001#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01
1002#define EMU_HANA_FPGA_CONFIG_HANA 0x02
1003
1004#define EMU_HANA_IRQ_ENABLE 0x09
1005#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1006#define EMU_HANA_IRQ_ADAT 0x02
1007#define EMU_HANA_IRQ_DOCK 0x04
1008#define EMU_HANA_IRQ_DOCK_LOST 0x08
1009
1010#define EMU_HANA_SPDIF_MODE 0x0a
1011#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1012#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1013#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1014#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1015#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1016#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1017#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1018
1019#define EMU_HANA_OPTICAL_TYPE 0x0b
1020#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1021#define EMU_HANA_OPTICAL_IN_ADAT 0x01
1022#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1023#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1024
1025#define EMU_HANA_MIDI_IN 0x0c
1026#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00
1027#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01
1028
1029#define EMU_HANA_DOCK_LEDS_1 0x0d
1030#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01
1031#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02
1032#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04
1033#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08
1034
1035#define EMU_HANA_DOCK_LEDS_2 0x0e
1036#define EMU_HANA_DOCK_LEDS_2_44K 0x01
1037#define EMU_HANA_DOCK_LEDS_2_48K 0x02
1038#define EMU_HANA_DOCK_LEDS_2_96K 0x04
1039#define EMU_HANA_DOCK_LEDS_2_192K 0x08
1040#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10
1041#define EMU_HANA_DOCK_LEDS_2_EXT 0x20
1042
1043#define EMU_HANA_DOCK_LEDS_3 0x0f
1044#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01
1045#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02
1046#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04
1047#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08
1048#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10
1049#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20
1050
1051#define EMU_HANA_ADC_PADS 0x10
1052#define EMU_HANA_DOCK_ADC_PAD1 0x01
1053#define EMU_HANA_DOCK_ADC_PAD2 0x02
1054#define EMU_HANA_DOCK_ADC_PAD3 0x04
1055#define EMU_HANA_0202_ADC_PAD1 0x08
1056
1057#define EMU_HANA_DOCK_MISC 0x11
1058#define EMU_HANA_DOCK_DAC1_MUTE 0x01
1059#define EMU_HANA_DOCK_DAC2_MUTE 0x02
1060#define EMU_HANA_DOCK_DAC3_MUTE 0x04
1061#define EMU_HANA_DOCK_DAC4_MUTE 0x08
1062#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00
1063#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10
1064#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20
1065#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30
1066
1067#define EMU_HANA_MIDI_OUT 0x12
1068#define EMU_HANA_MIDI_OUT_0202 0x01
1069#define EMU_HANA_MIDI_OUT_DOCK1 0x02
1070#define EMU_HANA_MIDI_OUT_DOCK2 0x04
1071#define EMU_HANA_MIDI_OUT_SYNC2 0x08
1072#define EMU_HANA_MIDI_OUT_LOOP 0x10
1073
1074#define EMU_HANA_DAC_PADS 0x13
1075#define EMU_HANA_DOCK_DAC_PAD1 0x01
1076#define EMU_HANA_DOCK_DAC_PAD2 0x02
1077#define EMU_HANA_DOCK_DAC_PAD3 0x04
1078#define EMU_HANA_DOCK_DAC_PAD4 0x08
1079#define EMU_HANA_0202_DAC_PAD1 0x10
1080
1081
1082#define EMU_HANA_IRQ_STATUS 0x20
1083#if 0
1084#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1085#define EMU_HANA_IRQ_ADAT 0x02
1086#define EMU_HANA_IRQ_DOCK 0x04
1087#define EMU_HANA_IRQ_DOCK_LOST 0x08
1088#endif
1089
1090#define EMU_HANA_OPTION_CARDS 0x21
1091#define EMU_HANA_OPTION_HAMOA 0x01
1092#define EMU_HANA_OPTION_SYNC 0x02
1093#define EMU_HANA_OPTION_DOCK_ONLINE 0x04
1094#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08
1095
1096#define EMU_HANA_ID 0x22
1097
1098#define EMU_HANA_MAJOR_REV 0x23
1099#define EMU_HANA_MINOR_REV 0x24
1100
1101#define EMU_DOCK_MAJOR_REV 0x25
1102#define EMU_DOCK_MINOR_REV 0x26
1103
1104#define EMU_DOCK_BOARD_ID 0x27
1105#define EMU_DOCK_BOARD_ID0 0x00
1106#define EMU_DOCK_BOARD_ID1 0x03
1107
1108#define EMU_HANA_WC_SPDIF_HI 0x28
1109#define EMU_HANA_WC_SPDIF_LO 0x29
1110
1111#define EMU_HANA_WC_ADAT_HI 0x2a
1112#define EMU_HANA_WC_ADAT_LO 0x2b
1113
1114#define EMU_HANA_WC_BNC_LO 0x2c
1115#define EMU_HANA_WC_BNC_HI 0x2d
1116
1117#define EMU_HANA2_WC_SPDIF_HI 0x2e
1118#define EMU_HANA2_WC_SPDIF_LO 0x2f
1119
1120
1121
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1123
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1128
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1226
1227#define EMU_DST_ALICE2_EMU32_0 0x000f
1228#define EMU_DST_ALICE2_EMU32_1 0x0000
1229#define EMU_DST_ALICE2_EMU32_2 0x0001
1230#define EMU_DST_ALICE2_EMU32_3 0x0002
1231#define EMU_DST_ALICE2_EMU32_4 0x0003
1232#define EMU_DST_ALICE2_EMU32_5 0x0004
1233#define EMU_DST_ALICE2_EMU32_6 0x0005
1234#define EMU_DST_ALICE2_EMU32_7 0x0006
1235#define EMU_DST_ALICE2_EMU32_8 0x0007
1236#define EMU_DST_ALICE2_EMU32_9 0x0008
1237#define EMU_DST_ALICE2_EMU32_A 0x0009
1238#define EMU_DST_ALICE2_EMU32_B 0x000a
1239#define EMU_DST_ALICE2_EMU32_C 0x000b
1240#define EMU_DST_ALICE2_EMU32_D 0x000c
1241#define EMU_DST_ALICE2_EMU32_E 0x000d
1242#define EMU_DST_ALICE2_EMU32_F 0x000e
1243#define EMU_DST_DOCK_DAC1_LEFT1 0x0100
1244#define EMU_DST_DOCK_DAC1_LEFT2 0x0101
1245#define EMU_DST_DOCK_DAC1_LEFT3 0x0102
1246#define EMU_DST_DOCK_DAC1_LEFT4 0x0103
1247#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104
1248#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105
1249#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106
1250#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107
1251#define EMU_DST_DOCK_DAC2_LEFT1 0x0108
1252#define EMU_DST_DOCK_DAC2_LEFT2 0x0109
1253#define EMU_DST_DOCK_DAC2_LEFT3 0x010a
1254#define EMU_DST_DOCK_DAC2_LEFT4 0x010b
1255#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c
1256#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d
1257#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e
1258#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f
1259#define EMU_DST_DOCK_DAC3_LEFT1 0x0110
1260#define EMU_DST_DOCK_DAC3_LEFT2 0x0111
1261#define EMU_DST_DOCK_DAC3_LEFT3 0x0112
1262#define EMU_DST_DOCK_DAC3_LEFT4 0x0113
1263#define EMU_DST_DOCK_PHONES_LEFT1 0x0112
1264#define EMU_DST_DOCK_PHONES_LEFT2 0x0113
1265#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114
1266#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115
1267#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116
1268#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117
1269#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116
1270#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117
1271#define EMU_DST_DOCK_DAC4_LEFT1 0x0118
1272#define EMU_DST_DOCK_DAC4_LEFT2 0x0119
1273#define EMU_DST_DOCK_DAC4_LEFT3 0x011a
1274#define EMU_DST_DOCK_DAC4_LEFT4 0x011b
1275#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a
1276#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b
1277#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c
1278#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d
1279#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e
1280#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f
1281#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e
1282#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f
1283#define EMU_DST_HANA_SPDIF_LEFT1 0x0200
1284#define EMU_DST_HANA_SPDIF_LEFT2 0x0202
1285#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201
1286#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203
1287#define EMU_DST_HAMOA_DAC_LEFT1 0x0300
1288#define EMU_DST_HAMOA_DAC_LEFT2 0x0302
1289#define EMU_DST_HAMOA_DAC_LEFT3 0x0304
1290#define EMU_DST_HAMOA_DAC_LEFT4 0x0306
1291#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301
1292#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303
1293#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305
1294#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307
1295#define EMU_DST_HANA_ADAT 0x0400
1296#define EMU_DST_ALICE_I2S0_LEFT 0x0500
1297#define EMU_DST_ALICE_I2S0_RIGHT 0x0501
1298#define EMU_DST_ALICE_I2S1_LEFT 0x0600
1299#define EMU_DST_ALICE_I2S1_RIGHT 0x0601
1300#define EMU_DST_ALICE_I2S2_LEFT 0x0700
1301#define EMU_DST_ALICE_I2S2_RIGHT 0x0701
1302
1303
1304
1305#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1306
1307#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1308
1309#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1310
1311#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1312
1313#define EMU_DST_MDOCK_ADAT 0x0118
1314
1315
1316#define EMU_DST_MANA_DAC_LEFT 0x0300
1317
1318#define EMU_DST_MANA_DAC_RIGHT 0x0301
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1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425#define EMU_SRC_SILENCE 0x0000
1426#define EMU_SRC_DOCK_MIC_A1 0x0100
1427#define EMU_SRC_DOCK_MIC_A2 0x0101
1428#define EMU_SRC_DOCK_MIC_A3 0x0102
1429#define EMU_SRC_DOCK_MIC_A4 0x0103
1430#define EMU_SRC_DOCK_MIC_B1 0x0104
1431#define EMU_SRC_DOCK_MIC_B2 0x0105
1432#define EMU_SRC_DOCK_MIC_B3 0x0106
1433#define EMU_SRC_DOCK_MIC_B4 0x0107
1434#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108
1435#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109
1436#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a
1437#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b
1438#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c
1439#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d
1440#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e
1441#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f
1442#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110
1443#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111
1444#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112
1445#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113
1446#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114
1447#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115
1448#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116
1449#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117
1450#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118
1451#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119
1452#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a
1453#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b
1454#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c
1455#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d
1456#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e
1457#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f
1458#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200
1459#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202
1460#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204
1461#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206
1462#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201
1463#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203
1464#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205
1465#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207
1466#define EMU_SRC_ALICE_EMU32A 0x0300
1467#define EMU_SRC_ALICE_EMU32B 0x0310
1468#define EMU_SRC_HANA_ADAT 0x0400
1469#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500
1470#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502
1471#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501
1472#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503
1473
1474
1475
1476#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1477
1478#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1479
1480#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1481
1482#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1483
1484#define EMU_SRC_MDOCK_ADAT 0x0118
1485
1486
1487
1488
1489
1490enum {
1491 EMU10K1_EFX,
1492 EMU10K1_PCM,
1493 EMU10K1_SYNTH,
1494 EMU10K1_MIDI
1495};
1496
1497struct snd_emu10k1;
1498
1499struct snd_emu10k1_voice {
1500 struct snd_emu10k1 *emu;
1501 int number;
1502 unsigned int use: 1,
1503 pcm: 1,
1504 efx: 1,
1505 synth: 1,
1506 midi: 1;
1507 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1508
1509 struct snd_emu10k1_pcm *epcm;
1510};
1511
1512enum {
1513 PLAYBACK_EMUVOICE,
1514 PLAYBACK_EFX,
1515 CAPTURE_AC97ADC,
1516 CAPTURE_AC97MIC,
1517 CAPTURE_EFX
1518};
1519
1520struct snd_emu10k1_pcm {
1521 struct snd_emu10k1 *emu;
1522 int type;
1523 struct snd_pcm_substream *substream;
1524 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1525 struct snd_emu10k1_voice *extra;
1526 unsigned short running;
1527 unsigned short first_ptr;
1528 struct snd_util_memblk *memblk;
1529 unsigned int start_addr;
1530 unsigned int ccca_start_addr;
1531 unsigned int capture_ipr;
1532 unsigned int capture_inte;
1533 unsigned int capture_ba_reg;
1534 unsigned int capture_bs_reg;
1535 unsigned int capture_idx_reg;
1536 unsigned int capture_cr_val;
1537 unsigned int capture_cr_val2;
1538 unsigned int capture_bs_val;
1539 unsigned int capture_bufsize;
1540};
1541
1542struct snd_emu10k1_pcm_mixer {
1543
1544 unsigned char send_routing[3][8];
1545 unsigned char send_volume[3][8];
1546 unsigned short attn[3];
1547 struct snd_emu10k1_pcm *epcm;
1548};
1549
1550#define snd_emu10k1_compose_send_routing(route) \
1551((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1552
1553#define snd_emu10k1_compose_audigy_fxrt1(route) \
1554((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1555
1556#define snd_emu10k1_compose_audigy_fxrt2(route) \
1557((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1558
1559struct snd_emu10k1_memblk {
1560 struct snd_util_memblk mem;
1561
1562 int first_page, last_page, pages, mapped_page;
1563 unsigned int map_locked;
1564 struct list_head mapped_link;
1565 struct list_head mapped_order_link;
1566};
1567
1568#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1569
1570#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1571
1572struct snd_emu10k1_fx8010_ctl {
1573 struct list_head list;
1574 unsigned int vcount;
1575 unsigned int count;
1576 unsigned short gpr[32];
1577 unsigned int value[32];
1578 unsigned int min;
1579 unsigned int max;
1580 unsigned int translation;
1581 struct snd_kcontrol *kcontrol;
1582};
1583
1584typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1585
1586struct snd_emu10k1_fx8010_irq {
1587 struct snd_emu10k1_fx8010_irq *next;
1588 snd_fx8010_irq_handler_t *handler;
1589 unsigned short gpr_running;
1590 void *private_data;
1591};
1592
1593struct snd_emu10k1_fx8010_pcm {
1594 unsigned int valid: 1,
1595 opened: 1,
1596 active: 1;
1597 unsigned int channels;
1598 unsigned int tram_start;
1599 unsigned int buffer_size;
1600 unsigned short gpr_size;
1601 unsigned short gpr_ptr;
1602 unsigned short gpr_count;
1603 unsigned short gpr_tmpcount;
1604 unsigned short gpr_trigger;
1605 unsigned short gpr_running;
1606 unsigned char etram[32];
1607 struct snd_pcm_indirect pcm_rec;
1608 unsigned int tram_pos;
1609 unsigned int tram_shift;
1610 struct snd_emu10k1_fx8010_irq *irq;
1611};
1612
1613struct snd_emu10k1_fx8010 {
1614 unsigned short fxbus_mask;
1615 unsigned short extin_mask;
1616 unsigned short extout_mask;
1617 unsigned short pad1;
1618 unsigned int itram_size;
1619 struct snd_dma_buffer etram_pages;
1620 unsigned int dbg;
1621 unsigned char name[128];
1622 int gpr_size;
1623 int gpr_count;
1624 struct list_head gpr_ctl;
1625 struct mutex lock;
1626 struct snd_emu10k1_fx8010_pcm pcm[8];
1627 spinlock_t irq_lock;
1628 struct snd_emu10k1_fx8010_irq *irq_handlers;
1629};
1630
1631struct snd_emu10k1_midi {
1632 struct snd_emu10k1 *emu;
1633 struct snd_rawmidi *rmidi;
1634 struct snd_rawmidi_substream *substream_input;
1635 struct snd_rawmidi_substream *substream_output;
1636 unsigned int midi_mode;
1637 spinlock_t input_lock;
1638 spinlock_t output_lock;
1639 spinlock_t open_lock;
1640 int tx_enable, rx_enable;
1641 int port;
1642 int ipr_tx, ipr_rx;
1643 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1644};
1645
1646enum {
1647 EMU_MODEL_SB,
1648 EMU_MODEL_EMU1010,
1649 EMU_MODEL_EMU1010B,
1650 EMU_MODEL_EMU1616,
1651 EMU_MODEL_EMU0404,
1652};
1653
1654struct snd_emu_chip_details {
1655 u32 vendor;
1656 u32 device;
1657 u32 subsystem;
1658 unsigned char revision;
1659 unsigned char emu10k1_chip;
1660 unsigned char emu10k2_chip;
1661 unsigned char ca0102_chip;
1662 unsigned char ca0108_chip;
1663 unsigned char ca_cardbus_chip;
1664 unsigned char ca0151_chip;
1665 unsigned char spk71;
1666 unsigned char sblive51;
1667 unsigned char spdif_bug;
1668 unsigned char ac97_chip;
1669 unsigned char ecard;
1670 unsigned char emu_model;
1671 unsigned char spi_dac;
1672 unsigned char i2c_adc;
1673 unsigned char adc_1361t;
1674 unsigned char invert_shared_spdif;
1675 const char *driver;
1676 const char *name;
1677 const char *id;
1678};
1679
1680struct snd_emu1010 {
1681 unsigned int output_source[64];
1682 unsigned int input_source[64];
1683 unsigned int adc_pads;
1684 unsigned int dac_pads;
1685 unsigned int internal_clock;
1686 unsigned int optical_in;
1687 unsigned int optical_out;
1688 struct task_struct *firmware_thread;
1689};
1690
1691struct snd_emu10k1 {
1692 int irq;
1693
1694 unsigned long port;
1695 unsigned int tos_link: 1,
1696 rear_ac97: 1,
1697 enable_ir: 1;
1698 unsigned int support_tlv :1;
1699
1700 const struct snd_emu_chip_details *card_capabilities;
1701 unsigned int audigy;
1702 unsigned int revision;
1703 unsigned int serial;
1704 unsigned short model;
1705 unsigned int card_type;
1706 unsigned int ecard_ctrl;
1707 unsigned long dma_mask;
1708 unsigned int delay_pcm_irq;
1709 int max_cache_pages;
1710 struct snd_dma_buffer silent_page;
1711 struct snd_dma_buffer ptb_pages;
1712 struct snd_dma_device p16v_dma_dev;
1713 struct snd_dma_buffer p16v_buffer;
1714
1715 struct snd_util_memhdr *memhdr;
1716 struct snd_emu10k1_memblk *reserved_page;
1717
1718 struct list_head mapped_link_head;
1719 struct list_head mapped_order_link_head;
1720 void **page_ptr_table;
1721 unsigned long *page_addr_table;
1722 spinlock_t memblk_lock;
1723
1724 unsigned int spdif_bits[3];
1725 unsigned int i2c_capture_source;
1726 u8 i2c_capture_volume[4][2];
1727
1728 struct snd_emu10k1_fx8010 fx8010;
1729 int gpr_base;
1730
1731 struct snd_ac97 *ac97;
1732
1733 struct pci_dev *pci;
1734 struct snd_card *card;
1735 struct snd_pcm *pcm;
1736 struct snd_pcm *pcm_mic;
1737 struct snd_pcm *pcm_efx;
1738 struct snd_pcm *pcm_multi;
1739 struct snd_pcm *pcm_p16v;
1740
1741 spinlock_t synth_lock;
1742 void *synth;
1743 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1744
1745 spinlock_t reg_lock;
1746 spinlock_t emu_lock;
1747 spinlock_t voice_lock;
1748 spinlock_t spi_lock;
1749 spinlock_t i2c_lock;
1750
1751 struct snd_emu10k1_voice voices[NUM_G];
1752 struct snd_emu10k1_voice p16v_voices[4];
1753 struct snd_emu10k1_voice p16v_capture_voice;
1754 int p16v_device_offset;
1755 u32 p16v_capture_source;
1756 u32 p16v_capture_channel;
1757 struct snd_emu1010 emu1010;
1758 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1759 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1760 struct snd_kcontrol *ctl_send_routing;
1761 struct snd_kcontrol *ctl_send_volume;
1762 struct snd_kcontrol *ctl_attn;
1763 struct snd_kcontrol *ctl_efx_send_routing;
1764 struct snd_kcontrol *ctl_efx_send_volume;
1765 struct snd_kcontrol *ctl_efx_attn;
1766
1767 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1768 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1769 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1770 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1771 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1773
1774 struct snd_pcm_substream *pcm_capture_substream;
1775 struct snd_pcm_substream *pcm_capture_mic_substream;
1776 struct snd_pcm_substream *pcm_capture_efx_substream;
1777 struct snd_pcm_substream *pcm_playback_efx_substream;
1778
1779 struct snd_timer *timer;
1780
1781 struct snd_emu10k1_midi midi;
1782 struct snd_emu10k1_midi midi2;
1783
1784 unsigned int efx_voices_mask[2];
1785 unsigned int next_free_voice;
1786
1787 const struct firmware *firmware;
1788 const struct firmware *dock_fw;
1789
1790#ifdef CONFIG_PM_SLEEP
1791 unsigned int *saved_ptr;
1792 unsigned int *saved_gpr;
1793 unsigned int *tram_val_saved;
1794 unsigned int *tram_addr_saved;
1795 unsigned int *saved_icode;
1796 unsigned int *p16v_saved;
1797 unsigned int saved_a_iocfg, saved_hcfg;
1798 bool suspend;
1799#endif
1800
1801};
1802
1803int snd_emu10k1_create(struct snd_card *card,
1804 struct pci_dev *pci,
1805 unsigned short extin_mask,
1806 unsigned short extout_mask,
1807 long max_cache_bytes,
1808 int enable_ir,
1809 uint subsystem,
1810 struct snd_emu10k1 ** remu);
1811
1812int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
1813int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
1814int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
1815int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
1816int snd_p16v_free(struct snd_emu10k1 * emu);
1817int snd_p16v_mixer(struct snd_emu10k1 * emu);
1818int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
1819int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
1820int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1821int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1822int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
1823
1824irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1825
1826void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1827int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1828void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1829int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1830int snd_emu10k1_done(struct snd_emu10k1 * emu);
1831
1832
1833unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1834void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1835unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1836void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1837int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1838int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1839int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1840int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1841int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1842unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1843void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1844void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1845void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1846void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1847void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1848void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1849void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1850void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1851void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1852void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1853void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1854static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1855unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1856void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1857unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1858
1859#ifdef CONFIG_PM_SLEEP
1860void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1861void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1862void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1863int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1864void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1865void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1866void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1867int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1868void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1869void snd_p16v_suspend(struct snd_emu10k1 *emu);
1870void snd_p16v_resume(struct snd_emu10k1 *emu);
1871#endif
1872
1873
1874struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1875int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1876struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1877int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1878int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1879int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1880int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1881
1882
1883int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1884int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1885
1886
1887int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1888int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1889
1890
1891int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1892
1893
1894int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1895 snd_fx8010_irq_handler_t *handler,
1896 unsigned char gpr_running,
1897 void *private_data,
1898 struct snd_emu10k1_fx8010_irq **r_irq);
1899int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1900 struct snd_emu10k1_fx8010_irq *irq);
1901
1902#endif
1903