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13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/regmap.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "wm8983.h"
30
31static const struct reg_default wm8983_defaults[] = {
32 { 0x01, 0x0000 },
33 { 0x02, 0x0000 },
34 { 0x03, 0x0000 },
35 { 0x04, 0x0050 },
36 { 0x05, 0x0000 },
37 { 0x06, 0x0140 },
38 { 0x07, 0x0000 },
39 { 0x08, 0x0000 },
40 { 0x09, 0x0000 },
41 { 0x0A, 0x0000 },
42 { 0x0B, 0x00FF },
43 { 0x0C, 0x00FF },
44 { 0x0D, 0x0000 },
45 { 0x0E, 0x0100 },
46 { 0x0F, 0x00FF },
47 { 0x10, 0x00FF },
48 { 0x12, 0x012C },
49 { 0x13, 0x002C },
50 { 0x14, 0x002C },
51 { 0x15, 0x002C },
52 { 0x16, 0x002C },
53 { 0x18, 0x0032 },
54 { 0x19, 0x0000 },
55 { 0x1B, 0x0000 },
56 { 0x1C, 0x0000 },
57 { 0x1D, 0x0000 },
58 { 0x1E, 0x0000 },
59 { 0x20, 0x0038 },
60 { 0x21, 0x000B },
61 { 0x22, 0x0032 },
62 { 0x23, 0x0000 },
63 { 0x24, 0x0008 },
64 { 0x25, 0x000C },
65 { 0x26, 0x0093 },
66 { 0x27, 0x00E9 },
67 { 0x29, 0x0000 },
68 { 0x2A, 0x0000 },
69 { 0x2B, 0x0000 },
70 { 0x2C, 0x0033 },
71 { 0x2D, 0x0010 },
72 { 0x2E, 0x0010 },
73 { 0x2F, 0x0100 },
74 { 0x30, 0x0100 },
75 { 0x31, 0x0002 },
76 { 0x32, 0x0001 },
77 { 0x33, 0x0001 },
78 { 0x34, 0x0039 },
79 { 0x35, 0x0039 },
80 { 0x36, 0x0039 },
81 { 0x37, 0x0039 },
82 { 0x38, 0x0001 },
83 { 0x39, 0x0001 },
84 { 0x3D, 0x0000 },
85};
86
87static const struct wm8983_reg_access {
88 u16 read;
89 u16 write;
90} wm8983_access_masks[WM8983_MAX_REGISTER + 1] = {
91 [0x00] = { 0x0000, 0x01FF },
92 [0x01] = { 0x0000, 0x01FF },
93 [0x02] = { 0x0000, 0x01FF },
94 [0x03] = { 0x0000, 0x01EF },
95 [0x04] = { 0x0000, 0x01FF },
96 [0x05] = { 0x0000, 0x003F },
97 [0x06] = { 0x0000, 0x01FD },
98 [0x07] = { 0x0000, 0x000F },
99 [0x08] = { 0x0000, 0x003F },
100 [0x09] = { 0x0000, 0x0070 },
101 [0x0A] = { 0x0000, 0x004F },
102 [0x0B] = { 0x0000, 0x01FF },
103 [0x0C] = { 0x0000, 0x01FF },
104 [0x0D] = { 0x0000, 0x00FF },
105 [0x0E] = { 0x0000, 0x01FB },
106 [0x0F] = { 0x0000, 0x01FF },
107 [0x10] = { 0x0000, 0x01FF },
108 [0x12] = { 0x0000, 0x017F },
109 [0x13] = { 0x0000, 0x017F },
110 [0x14] = { 0x0000, 0x017F },
111 [0x15] = { 0x0000, 0x017F },
112 [0x16] = { 0x0000, 0x007F },
113 [0x18] = { 0x0000, 0x01FF },
114 [0x19] = { 0x0000, 0x007F },
115 [0x1B] = { 0x0000, 0x01FF },
116 [0x1C] = { 0x0000, 0x017F },
117 [0x1D] = { 0x0000, 0x017F },
118 [0x1E] = { 0x0000, 0x017F },
119 [0x20] = { 0x0000, 0x01BF },
120 [0x21] = { 0x0000, 0x00FF },
121 [0x22] = { 0x0000, 0x01FF },
122 [0x23] = { 0x0000, 0x000F },
123 [0x24] = { 0x0000, 0x001F },
124 [0x25] = { 0x0000, 0x003F },
125 [0x26] = { 0x0000, 0x01FF },
126 [0x27] = { 0x0000, 0x01FF },
127 [0x29] = { 0x0000, 0x000F },
128 [0x2A] = { 0x0000, 0x01E7 },
129 [0x2B] = { 0x0000, 0x01BF },
130 [0x2C] = { 0x0000, 0x0177 },
131 [0x2D] = { 0x0000, 0x01FF },
132 [0x2E] = { 0x0000, 0x01FF },
133 [0x2F] = { 0x0000, 0x0177 },
134 [0x30] = { 0x0000, 0x0177 },
135 [0x31] = { 0x0000, 0x007F },
136 [0x32] = { 0x0000, 0x01FF },
137 [0x33] = { 0x0000, 0x01FF },
138 [0x34] = { 0x0000, 0x01FF },
139 [0x35] = { 0x0000, 0x01FF },
140 [0x36] = { 0x0000, 0x01FF },
141 [0x37] = { 0x0000, 0x01FF },
142 [0x38] = { 0x0000, 0x004F },
143 [0x39] = { 0x0000, 0x00FF },
144 [0x3D] = { 0x0000, 0x0100 }
145};
146
147
148static const int vol_update_regs[] = {
149 WM8983_LEFT_DAC_DIGITAL_VOL,
150 WM8983_RIGHT_DAC_DIGITAL_VOL,
151 WM8983_LEFT_ADC_DIGITAL_VOL,
152 WM8983_RIGHT_ADC_DIGITAL_VOL,
153 WM8983_LOUT1_HP_VOLUME_CTRL,
154 WM8983_ROUT1_HP_VOLUME_CTRL,
155 WM8983_LOUT2_SPK_VOLUME_CTRL,
156 WM8983_ROUT2_SPK_VOLUME_CTRL,
157 WM8983_LEFT_INP_PGA_GAIN_CTRL,
158 WM8983_RIGHT_INP_PGA_GAIN_CTRL
159};
160
161struct wm8983_priv {
162 struct regmap *regmap;
163 u32 sysclk;
164 u32 bclk;
165};
166
167static const struct {
168 int div;
169 int ratio;
170} fs_ratios[] = {
171 { 10, 128 },
172 { 15, 192 },
173 { 20, 256 },
174 { 30, 384 },
175 { 40, 512 },
176 { 60, 768 },
177 { 80, 1024 },
178 { 120, 1536 }
179};
180
181static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
182
183static const int bclk_divs[] = {
184 1, 2, 4, 8, 16, 32
185};
186
187static int eqmode_get(struct snd_kcontrol *kcontrol,
188 struct snd_ctl_elem_value *ucontrol);
189static int eqmode_put(struct snd_kcontrol *kcontrol,
190 struct snd_ctl_elem_value *ucontrol);
191
192static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
193static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
194static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
195static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
196static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
197static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
198static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
199static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
200static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
201static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
202static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
203static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
204static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
205static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
206
207static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
208static SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7, alc_sel_text);
209
210static const char *alc_mode_text[] = { "ALC", "Limiter" };
211static SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8, alc_mode_text);
212
213static const char *filter_mode_text[] = { "Audio", "Application" };
214static SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
215 filter_mode_text);
216
217static const char *eq_bw_text[] = { "Narrow", "Wide" };
218static const char *eqmode_text[] = { "Capture", "Playback" };
219static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
220
221static const char *eq1_cutoff_text[] = {
222 "80Hz", "105Hz", "135Hz", "175Hz"
223};
224static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
225 eq1_cutoff_text);
226static const char *eq2_cutoff_text[] = {
227 "230Hz", "300Hz", "385Hz", "500Hz"
228};
229static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
230static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5, eq2_cutoff_text);
231static const char *eq3_cutoff_text[] = {
232 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
233};
234static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
235static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5, eq3_cutoff_text);
236static const char *eq4_cutoff_text[] = {
237 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
238};
239static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
240static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5, eq4_cutoff_text);
241static const char *eq5_cutoff_text[] = {
242 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
243};
244static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
245 eq5_cutoff_text);
246
247static const char *depth_3d_text[] = {
248 "Off",
249 "6.67%",
250 "13.3%",
251 "20%",
252 "26.7%",
253 "33.3%",
254 "40%",
255 "46.6%",
256 "53.3%",
257 "60%",
258 "66.7%",
259 "73.3%",
260 "80%",
261 "86.7%",
262 "93.3%",
263 "100%"
264};
265static SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
266 depth_3d_text);
267
268static const struct snd_kcontrol_new wm8983_snd_controls[] = {
269 SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
270 0, 1, 0),
271
272 SOC_ENUM("ALC Capture Function", alc_sel),
273 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
274 3, 7, 0, alc_max_tlv),
275 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
276 0, 7, 0, alc_min_tlv),
277 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
278 0, 15, 0, alc_tar_tlv),
279 SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
280 SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
281 SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
282 SOC_ENUM("ALC Mode", alc_mode),
283 SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
284 3, 1, 0),
285 SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
286 0, 7, 1),
287
288 SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
289 WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
290 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
291 WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
292 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
293 WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
294
295 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
296 WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
297 8, 1, 0, pga_boost_tlv),
298
299 SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
300 SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
301
302 SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
303 WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
304
305 SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
306 SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
307 SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
308 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
309 4, 7, 1, lim_thresh_tlv),
310 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
311 0, 12, 0, lim_boost_tlv),
312 SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
313 SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
314 SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
315
316 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
317 WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
318 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
319 WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
320 SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
321 WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
322
323 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
324 WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
325 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
326 WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
327 SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
328 WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
329
330 SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
331 6, 1, 1),
332
333 SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
334 6, 1, 1),
335
336 SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
337 SOC_ENUM("High Pass Filter Mode", filter_mode),
338 SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
339
340 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
341 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
342 aux_tlv),
343
344 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
345 WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
346 bypass_tlv),
347
348 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
349 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
350 SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
351 SOC_ENUM("EQ2 Bandwidth", eq2_bw),
352 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
353 SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
354 SOC_ENUM("EQ3 Bandwidth", eq3_bw),
355 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
356 SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
357 SOC_ENUM("EQ4 Bandwidth", eq4_bw),
358 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
359 SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
360 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
361 SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
362
363 SOC_ENUM("3D Depth", depth_3d),
364};
365
366static const struct snd_kcontrol_new left_out_mixer[] = {
367 SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
368 SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
369 SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
370};
371
372static const struct snd_kcontrol_new right_out_mixer[] = {
373 SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
374 SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
375 SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
376};
377
378static const struct snd_kcontrol_new left_input_mixer[] = {
379 SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
380 SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
381 SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
382};
383
384static const struct snd_kcontrol_new right_input_mixer[] = {
385 SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
386 SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
387 SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
388};
389
390static const struct snd_kcontrol_new left_boost_mixer[] = {
391 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
392 4, 7, 0, boost_tlv),
393 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
394 0, 7, 0, boost_tlv)
395};
396
397static const struct snd_kcontrol_new out3_mixer[] = {
398 SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
399 1, 1, 0),
400 SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
401 0, 1, 0),
402};
403
404static const struct snd_kcontrol_new out4_mixer[] = {
405 SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
406 4, 1, 0),
407 SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
408 1, 1, 0),
409 SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
410 3, 1, 0),
411 SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
412 0, 1, 0),
413};
414
415static const struct snd_kcontrol_new right_boost_mixer[] = {
416 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
417 4, 7, 0, boost_tlv),
418 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
419 0, 7, 0, boost_tlv)
420};
421
422static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
423 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
424 0, 0),
425 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
426 1, 0),
427 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
428 0, 0),
429 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
430 1, 0),
431
432 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
433 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
434 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
435 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
436
437 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
438 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
439 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
440 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
441
442 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
443 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
444 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
445 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
446
447 SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
448 6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
449
450 SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
451 7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
452
453 SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
454 6, 1, NULL, 0),
455 SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
456 6, 1, NULL, 0),
457
458 SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
459 7, 0, NULL, 0),
460 SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
461 8, 0, NULL, 0),
462
463 SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
464 5, 0, NULL, 0),
465 SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
466 6, 0, NULL, 0),
467
468 SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
469 7, 0, NULL, 0),
470
471 SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
472 8, 0, NULL, 0),
473
474 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
475 NULL, 0),
476
477 SND_SOC_DAPM_INPUT("LIN"),
478 SND_SOC_DAPM_INPUT("LIP"),
479 SND_SOC_DAPM_INPUT("RIN"),
480 SND_SOC_DAPM_INPUT("RIP"),
481 SND_SOC_DAPM_INPUT("AUXL"),
482 SND_SOC_DAPM_INPUT("AUXR"),
483 SND_SOC_DAPM_INPUT("L2"),
484 SND_SOC_DAPM_INPUT("R2"),
485 SND_SOC_DAPM_OUTPUT("HPL"),
486 SND_SOC_DAPM_OUTPUT("HPR"),
487 SND_SOC_DAPM_OUTPUT("SPKL"),
488 SND_SOC_DAPM_OUTPUT("SPKR"),
489 SND_SOC_DAPM_OUTPUT("OUT3"),
490 SND_SOC_DAPM_OUTPUT("OUT4")
491};
492
493static const struct snd_soc_dapm_route wm8983_audio_map[] = {
494 { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
495 { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
496
497 { "OUT3 Out", NULL, "OUT3 Mixer" },
498 { "OUT3", NULL, "OUT3 Out" },
499
500 { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
501 { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
502 { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
503 { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
504
505 { "OUT4 Out", NULL, "OUT4 Mixer" },
506 { "OUT4", NULL, "OUT4 Out" },
507
508 { "Right Output Mixer", "PCM Switch", "Right DAC" },
509 { "Right Output Mixer", "Aux Switch", "AUXR" },
510 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
511
512 { "Left Output Mixer", "PCM Switch", "Left DAC" },
513 { "Left Output Mixer", "Aux Switch", "AUXL" },
514 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
515
516 { "Right Headphone Out", NULL, "Right Output Mixer" },
517 { "HPR", NULL, "Right Headphone Out" },
518
519 { "Left Headphone Out", NULL, "Left Output Mixer" },
520 { "HPL", NULL, "Left Headphone Out" },
521
522 { "Right Speaker Out", NULL, "Right Output Mixer" },
523 { "SPKR", NULL, "Right Speaker Out" },
524
525 { "Left Speaker Out", NULL, "Left Output Mixer" },
526 { "SPKL", NULL, "Left Speaker Out" },
527
528 { "Right ADC", NULL, "Right Boost Mixer" },
529
530 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
531 { "Right Boost Mixer", NULL, "Right Capture PGA" },
532 { "Right Boost Mixer", "R2 Volume", "R2" },
533
534 { "Left ADC", NULL, "Left Boost Mixer" },
535
536 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
537 { "Left Boost Mixer", NULL, "Left Capture PGA" },
538 { "Left Boost Mixer", "L2 Volume", "L2" },
539
540 { "Right Capture PGA", NULL, "Right Input Mixer" },
541 { "Left Capture PGA", NULL, "Left Input Mixer" },
542
543 { "Right Input Mixer", "R2 Switch", "R2" },
544 { "Right Input Mixer", "MicN Switch", "RIN" },
545 { "Right Input Mixer", "MicP Switch", "RIP" },
546
547 { "Left Input Mixer", "L2 Switch", "L2" },
548 { "Left Input Mixer", "MicN Switch", "LIN" },
549 { "Left Input Mixer", "MicP Switch", "LIP" },
550};
551
552static int eqmode_get(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *ucontrol)
554{
555 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
556 unsigned int reg;
557
558 reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
559 if (reg & WM8983_EQ3DMODE)
560 ucontrol->value.integer.value[0] = 1;
561 else
562 ucontrol->value.integer.value[0] = 0;
563
564 return 0;
565}
566
567static int eqmode_put(struct snd_kcontrol *kcontrol,
568 struct snd_ctl_elem_value *ucontrol)
569{
570 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
571 unsigned int regpwr2, regpwr3;
572 unsigned int reg_eq;
573
574 if (ucontrol->value.integer.value[0] != 0
575 && ucontrol->value.integer.value[0] != 1)
576 return -EINVAL;
577
578 reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
579 switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
580 case 0:
581 if (!ucontrol->value.integer.value[0])
582 return 0;
583 break;
584 case 1:
585 if (ucontrol->value.integer.value[0])
586 return 0;
587 break;
588 }
589
590 regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2);
591 regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3);
592
593 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2,
594 WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
595 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3,
596 WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
597
598 snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF,
599 WM8983_EQ3DMODE_MASK,
600 ucontrol->value.integer.value[0]
601 << WM8983_EQ3DMODE_SHIFT);
602
603 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2);
604 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3);
605 return 0;
606}
607
608static bool wm8983_readable(struct device *dev, unsigned int reg)
609{
610 if (reg > WM8983_MAX_REGISTER)
611 return 0;
612
613 return wm8983_access_masks[reg].read != 0;
614}
615
616static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
617{
618 struct snd_soc_codec *codec = dai->codec;
619
620 return snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
621 WM8983_SOFTMUTE_MASK,
622 !!mute << WM8983_SOFTMUTE_SHIFT);
623}
624
625static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
626{
627 struct snd_soc_codec *codec = dai->codec;
628 u16 format, master, bcp, lrp;
629
630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
631 case SND_SOC_DAIFMT_I2S:
632 format = 0x2;
633 break;
634 case SND_SOC_DAIFMT_RIGHT_J:
635 format = 0x0;
636 break;
637 case SND_SOC_DAIFMT_LEFT_J:
638 format = 0x1;
639 break;
640 case SND_SOC_DAIFMT_DSP_A:
641 case SND_SOC_DAIFMT_DSP_B:
642 format = 0x3;
643 break;
644 default:
645 dev_err(dai->dev, "Unknown dai format\n");
646 return -EINVAL;
647 }
648
649 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
650 WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
651
652 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
653 case SND_SOC_DAIFMT_CBM_CFM:
654 master = 1;
655 break;
656 case SND_SOC_DAIFMT_CBS_CFS:
657 master = 0;
658 break;
659 default:
660 dev_err(dai->dev, "Unknown master/slave configuration\n");
661 return -EINVAL;
662 }
663
664 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
665 WM8983_MS_MASK, master << WM8983_MS_SHIFT);
666
667
668 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
669 case SND_SOC_DAIFMT_DSP_A:
670 case SND_SOC_DAIFMT_DSP_B:
671 dev_err(dai->dev, "DSP A/B modes are not supported\n");
672 return -EINVAL;
673 default:
674 break;
675 }
676
677 bcp = lrp = 0;
678 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
679 case SND_SOC_DAIFMT_NB_NF:
680 break;
681 case SND_SOC_DAIFMT_IB_IF:
682 bcp = lrp = 1;
683 break;
684 case SND_SOC_DAIFMT_IB_NF:
685 bcp = 1;
686 break;
687 case SND_SOC_DAIFMT_NB_IF:
688 lrp = 1;
689 break;
690 default:
691 dev_err(dai->dev, "Unknown polarity configuration\n");
692 return -EINVAL;
693 }
694
695 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
696 WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
697 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
698 WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
699 return 0;
700}
701
702static int wm8983_hw_params(struct snd_pcm_substream *substream,
703 struct snd_pcm_hw_params *params,
704 struct snd_soc_dai *dai)
705{
706 int i;
707 struct snd_soc_codec *codec = dai->codec;
708 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
709 u16 blen, srate_idx;
710 u32 tmp;
711 int srate_best;
712 int ret;
713
714 ret = snd_soc_params_to_bclk(params);
715 if (ret < 0) {
716 dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret);
717 return ret;
718 }
719
720 wm8983->bclk = ret;
721
722 switch (params_width(params)) {
723 case 16:
724 blen = 0x0;
725 break;
726 case 20:
727 blen = 0x1;
728 break;
729 case 24:
730 blen = 0x2;
731 break;
732 case 32:
733 blen = 0x3;
734 break;
735 default:
736 dev_err(dai->dev, "Unsupported word length %u\n",
737 params_width(params));
738 return -EINVAL;
739 }
740
741 snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
742 WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
743
744
745
746
747
748 srate_idx = 0;
749 srate_best = abs(srates[0] - params_rate(params));
750 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
751 if (abs(srates[i] - params_rate(params)) >= srate_best)
752 continue;
753 srate_idx = i;
754 srate_best = abs(srates[i] - params_rate(params));
755 }
756
757 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
758 snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL,
759 WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
760
761 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
762 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
763
764 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
765 if (wm8983->sysclk / params_rate(params)
766 == fs_ratios[i].ratio)
767 break;
768 }
769
770 if (i == ARRAY_SIZE(fs_ratios)) {
771 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
772 wm8983->sysclk, params_rate(params));
773 return -EINVAL;
774 }
775
776 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
777 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
778 WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
779
780
781 tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
782 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
783 if (wm8983->bclk == tmp / bclk_divs[i])
784 break;
785 }
786
787 if (i == ARRAY_SIZE(bclk_divs)) {
788 dev_err(dai->dev, "No matching BCLK divider found\n");
789 return -EINVAL;
790 }
791
792 dev_dbg(dai->dev, "BCLK div = %d\n", i);
793 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
794 WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
795
796 return 0;
797}
798
799struct pll_div {
800 u32 div2:1;
801 u32 n:4;
802 u32 k:24;
803};
804
805#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
806static int pll_factors(struct pll_div *pll_div, unsigned int target,
807 unsigned int source)
808{
809 u64 Kpart;
810 unsigned long int K, Ndiv, Nmod;
811
812 pll_div->div2 = 0;
813 Ndiv = target / source;
814 if (Ndiv < 6) {
815 source >>= 1;
816 pll_div->div2 = 1;
817 Ndiv = target / source;
818 }
819
820 if (Ndiv < 6 || Ndiv > 12) {
821 printk(KERN_ERR "%s: WM8983 N value is not within"
822 " the recommended range: %lu\n", __func__, Ndiv);
823 return -EINVAL;
824 }
825 pll_div->n = Ndiv;
826
827 Nmod = target % source;
828 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
829
830 do_div(Kpart, source);
831
832 K = Kpart & 0xffffffff;
833 if ((K % 10) >= 5)
834 K += 5;
835 K /= 10;
836 pll_div->k = K;
837 return 0;
838}
839
840static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
841 int source, unsigned int freq_in,
842 unsigned int freq_out)
843{
844 int ret;
845 struct snd_soc_codec *codec;
846 struct pll_div pll_div;
847
848 codec = dai->codec;
849 if (!freq_in || !freq_out) {
850
851 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
852 WM8983_PLLEN_MASK, 0);
853 return 0;
854 } else {
855 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
856 if (ret)
857 return ret;
858
859
860 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
861 WM8983_PLLEN_MASK, 0);
862
863
864 snd_soc_write(codec, WM8983_PLL_N,
865 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
866 | pll_div.n);
867
868 snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
869 snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
870 snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
871
872 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
873 WM8983_PLLEN_MASK, WM8983_PLLEN);
874 }
875
876 return 0;
877}
878
879static int wm8983_set_sysclk(struct snd_soc_dai *dai,
880 int clk_id, unsigned int freq, int dir)
881{
882 struct snd_soc_codec *codec = dai->codec;
883 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
884
885 switch (clk_id) {
886 case WM8983_CLKSRC_MCLK:
887 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
888 WM8983_CLKSEL_MASK, 0);
889 break;
890 case WM8983_CLKSRC_PLL:
891 snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
892 WM8983_CLKSEL_MASK, WM8983_CLKSEL);
893 break;
894 default:
895 dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
896 return -EINVAL;
897 }
898
899 wm8983->sysclk = freq;
900 return 0;
901}
902
903static int wm8983_set_bias_level(struct snd_soc_codec *codec,
904 enum snd_soc_bias_level level)
905{
906 struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
907 int ret;
908
909 switch (level) {
910 case SND_SOC_BIAS_ON:
911 case SND_SOC_BIAS_PREPARE:
912
913 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
914 WM8983_VMIDSEL_MASK,
915 1 << WM8983_VMIDSEL_SHIFT);
916 break;
917 case SND_SOC_BIAS_STANDBY:
918 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
919 ret = regcache_sync(wm8983->regmap);
920 if (ret < 0) {
921 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
922 return ret;
923 }
924
925 snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
926 WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
927 WM8983_POBCTRL | WM8983_DELEN);
928
929 snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
930 WM8983_TSDEN_MASK, WM8983_TSDEN);
931
932 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
933 WM8983_BIASEN_MASK, WM8983_BIASEN);
934
935 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
936 WM8983_VMIDSEL_MASK,
937 1 << WM8983_VMIDSEL_SHIFT);
938 msleep(250);
939
940 snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
941 WM8983_POBCTRL_MASK |
942 WM8983_DELEN_MASK, 0);
943 }
944
945
946 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
947 WM8983_VMIDSEL_MASK,
948 2 << WM8983_VMIDSEL_SHIFT);
949 break;
950 case SND_SOC_BIAS_OFF:
951
952 snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
953 WM8983_TSDEN_MASK, 0);
954
955 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
956 WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
957 0);
958
959 msleep(100);
960 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0);
961 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0);
962 snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0);
963 break;
964 }
965
966 codec->dapm.bias_level = level;
967 return 0;
968}
969
970static int wm8983_probe(struct snd_soc_codec *codec)
971{
972 int ret;
973 int i;
974
975 ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0);
976 if (ret < 0) {
977 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
978 return ret;
979 }
980
981
982 for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
983 snd_soc_update_bits(codec, vol_update_regs[i],
984 0x100, 0x100);
985
986
987 for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
988 i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
989 snd_soc_update_bits(codec, i, 0x40, 0x40);
990
991
992 snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
993 WM8983_SOFTMUTE_MASK,
994 WM8983_SOFTMUTE);
995
996
997 snd_soc_update_bits(codec, WM8983_BIAS_CTRL,
998 WM8983_BIASCUT, WM8983_BIASCUT);
999 return 0;
1000}
1001
1002static const struct snd_soc_dai_ops wm8983_dai_ops = {
1003 .digital_mute = wm8983_dac_mute,
1004 .hw_params = wm8983_hw_params,
1005 .set_fmt = wm8983_set_fmt,
1006 .set_sysclk = wm8983_set_sysclk,
1007 .set_pll = wm8983_set_pll
1008};
1009
1010#define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1011 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1012
1013static struct snd_soc_dai_driver wm8983_dai = {
1014 .name = "wm8983-hifi",
1015 .playback = {
1016 .stream_name = "Playback",
1017 .channels_min = 2,
1018 .channels_max = 2,
1019 .rates = SNDRV_PCM_RATE_8000_48000,
1020 .formats = WM8983_FORMATS,
1021 },
1022 .capture = {
1023 .stream_name = "Capture",
1024 .channels_min = 2,
1025 .channels_max = 2,
1026 .rates = SNDRV_PCM_RATE_8000_48000,
1027 .formats = WM8983_FORMATS,
1028 },
1029 .ops = &wm8983_dai_ops,
1030 .symmetric_rates = 1
1031};
1032
1033static struct snd_soc_codec_driver soc_codec_dev_wm8983 = {
1034 .probe = wm8983_probe,
1035 .set_bias_level = wm8983_set_bias_level,
1036 .suspend_bias_off = true,
1037 .controls = wm8983_snd_controls,
1038 .num_controls = ARRAY_SIZE(wm8983_snd_controls),
1039 .dapm_widgets = wm8983_dapm_widgets,
1040 .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
1041 .dapm_routes = wm8983_audio_map,
1042 .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
1043};
1044
1045static const struct regmap_config wm8983_regmap = {
1046 .reg_bits = 7,
1047 .val_bits = 9,
1048
1049 .reg_defaults = wm8983_defaults,
1050 .num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
1051 .cache_type = REGCACHE_RBTREE,
1052
1053 .readable_reg = wm8983_readable,
1054};
1055
1056#if defined(CONFIG_SPI_MASTER)
1057static int wm8983_spi_probe(struct spi_device *spi)
1058{
1059 struct wm8983_priv *wm8983;
1060 int ret;
1061
1062 wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
1063 if (!wm8983)
1064 return -ENOMEM;
1065
1066 wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
1067 if (IS_ERR(wm8983->regmap)) {
1068 ret = PTR_ERR(wm8983->regmap);
1069 dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
1070 return ret;
1071 }
1072
1073 spi_set_drvdata(spi, wm8983);
1074
1075 ret = snd_soc_register_codec(&spi->dev,
1076 &soc_codec_dev_wm8983, &wm8983_dai, 1);
1077 return ret;
1078}
1079
1080static int wm8983_spi_remove(struct spi_device *spi)
1081{
1082 snd_soc_unregister_codec(&spi->dev);
1083 return 0;
1084}
1085
1086static struct spi_driver wm8983_spi_driver = {
1087 .driver = {
1088 .name = "wm8983",
1089 .owner = THIS_MODULE,
1090 },
1091 .probe = wm8983_spi_probe,
1092 .remove = wm8983_spi_remove
1093};
1094#endif
1095
1096#if IS_ENABLED(CONFIG_I2C)
1097static int wm8983_i2c_probe(struct i2c_client *i2c,
1098 const struct i2c_device_id *id)
1099{
1100 struct wm8983_priv *wm8983;
1101 int ret;
1102
1103 wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
1104 if (!wm8983)
1105 return -ENOMEM;
1106
1107 wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
1108 if (IS_ERR(wm8983->regmap)) {
1109 ret = PTR_ERR(wm8983->regmap);
1110 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1111 return ret;
1112 }
1113
1114 i2c_set_clientdata(i2c, wm8983);
1115
1116 ret = snd_soc_register_codec(&i2c->dev,
1117 &soc_codec_dev_wm8983, &wm8983_dai, 1);
1118
1119 return ret;
1120}
1121
1122static int wm8983_i2c_remove(struct i2c_client *client)
1123{
1124 snd_soc_unregister_codec(&client->dev);
1125 return 0;
1126}
1127
1128static const struct i2c_device_id wm8983_i2c_id[] = {
1129 { "wm8983", 0 },
1130 { }
1131};
1132MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
1133
1134static struct i2c_driver wm8983_i2c_driver = {
1135 .driver = {
1136 .name = "wm8983",
1137 .owner = THIS_MODULE,
1138 },
1139 .probe = wm8983_i2c_probe,
1140 .remove = wm8983_i2c_remove,
1141 .id_table = wm8983_i2c_id
1142};
1143#endif
1144
1145static int __init wm8983_modinit(void)
1146{
1147 int ret = 0;
1148
1149#if IS_ENABLED(CONFIG_I2C)
1150 ret = i2c_add_driver(&wm8983_i2c_driver);
1151 if (ret) {
1152 printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
1153 ret);
1154 }
1155#endif
1156#if defined(CONFIG_SPI_MASTER)
1157 ret = spi_register_driver(&wm8983_spi_driver);
1158 if (ret != 0) {
1159 printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
1160 ret);
1161 }
1162#endif
1163 return ret;
1164}
1165module_init(wm8983_modinit);
1166
1167static void __exit wm8983_exit(void)
1168{
1169#if IS_ENABLED(CONFIG_I2C)
1170 i2c_del_driver(&wm8983_i2c_driver);
1171#endif
1172#if defined(CONFIG_SPI_MASTER)
1173 spi_unregister_driver(&wm8983_spi_driver);
1174#endif
1175}
1176module_exit(wm8983_exit);
1177
1178MODULE_DESCRIPTION("ASoC WM8983 driver");
1179MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1180MODULE_LICENSE("GPL");
1181
