linux/sound/soc/codecs/wm8996.c
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   1/*
   2 * wm8996.c - WM8996 audio codec interface
   3 *
   4 * Copyright 2011-2 Wolfson Microelectronics PLC.
   5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6 *
   7 *  This program is free software; you can redistribute  it and/or modify it
   8 *  under  the terms of  the GNU General  Public License as published by the
   9 *  Free Software Foundation;  either version 2 of the  License, or (at your
  10 *  option) any later version.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/moduleparam.h>
  15#include <linux/init.h>
  16#include <linux/completion.h>
  17#include <linux/delay.h>
  18#include <linux/pm.h>
  19#include <linux/gcd.h>
  20#include <linux/gpio.h>
  21#include <linux/i2c.h>
  22#include <linux/regmap.h>
  23#include <linux/regulator/consumer.h>
  24#include <linux/slab.h>
  25#include <linux/workqueue.h>
  26#include <sound/core.h>
  27#include <sound/jack.h>
  28#include <sound/pcm.h>
  29#include <sound/pcm_params.h>
  30#include <sound/soc.h>
  31#include <sound/initval.h>
  32#include <sound/tlv.h>
  33#include <trace/events/asoc.h>
  34
  35#include <sound/wm8996.h>
  36#include "wm8996.h"
  37
  38#define WM8996_AIFS 2
  39
  40#define HPOUT1L 1
  41#define HPOUT1R 2
  42#define HPOUT2L 4
  43#define HPOUT2R 8
  44
  45#define WM8996_NUM_SUPPLIES 3
  46static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
  47        "DBVDD",
  48        "AVDD1",
  49        "AVDD2",
  50};
  51
  52struct wm8996_priv {
  53        struct device *dev;
  54        struct regmap *regmap;
  55        struct snd_soc_codec *codec;
  56
  57        int ldo1ena;
  58
  59        int sysclk;
  60        int sysclk_src;
  61
  62        int fll_src;
  63        int fll_fref;
  64        int fll_fout;
  65
  66        struct completion fll_lock;
  67
  68        u16 dcs_pending;
  69        struct completion dcs_done;
  70
  71        u16 hpout_ena;
  72        u16 hpout_pending;
  73
  74        struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
  75        struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
  76        int bg_ena;
  77
  78        struct wm8996_pdata pdata;
  79
  80        int rx_rate[WM8996_AIFS];
  81        int bclk_rate[WM8996_AIFS];
  82
  83        /* Platform dependant ReTune mobile configuration */
  84        int num_retune_mobile_texts;
  85        const char **retune_mobile_texts;
  86        int retune_mobile_cfg[2];
  87        struct soc_enum retune_mobile_enum;
  88
  89        struct snd_soc_jack *jack;
  90        bool detecting;
  91        bool jack_mic;
  92        int jack_flips;
  93        wm8996_polarity_fn polarity_cb;
  94
  95#ifdef CONFIG_GPIOLIB
  96        struct gpio_chip gpio_chip;
  97#endif
  98};
  99
 100/* We can't use the same notifier block for more than one supply and
 101 * there's no way I can see to get from a callback to the caller
 102 * except container_of().
 103 */
 104#define WM8996_REGULATOR_EVENT(n) \
 105static int wm8996_regulator_event_##n(struct notifier_block *nb, \
 106                                    unsigned long event, void *data)    \
 107{ \
 108        struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
 109                                                  disable_nb[n]); \
 110        if (event & REGULATOR_EVENT_DISABLE) { \
 111                regcache_mark_dirty(wm8996->regmap);    \
 112        } \
 113        return 0; \
 114}
 115
 116WM8996_REGULATOR_EVENT(0)
 117WM8996_REGULATOR_EVENT(1)
 118WM8996_REGULATOR_EVENT(2)
 119
 120static struct reg_default wm8996_reg[] = {
 121        { WM8996_POWER_MANAGEMENT_1, 0x0 },
 122        { WM8996_POWER_MANAGEMENT_2, 0x0 },
 123        { WM8996_POWER_MANAGEMENT_3, 0x0 },
 124        { WM8996_POWER_MANAGEMENT_4, 0x0 },
 125        { WM8996_POWER_MANAGEMENT_5, 0x0 },
 126        { WM8996_POWER_MANAGEMENT_6, 0x0 },
 127        { WM8996_POWER_MANAGEMENT_7, 0x10 },
 128        { WM8996_POWER_MANAGEMENT_8, 0x0 },
 129        { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
 130        { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
 131        { WM8996_LINE_INPUT_CONTROL, 0x0 },
 132        { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
 133        { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
 134        { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
 135        { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
 136        { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
 137        { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
 138        { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
 139        { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
 140        { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
 141        { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
 142        { WM8996_MICBIAS_1, 0x39 },
 143        { WM8996_MICBIAS_2, 0x39 },
 144        { WM8996_LDO_1, 0x3 },
 145        { WM8996_LDO_2, 0x13 },
 146        { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
 147        { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
 148        { WM8996_HEADPHONE_DETECT_1, 0x20 },
 149        { WM8996_HEADPHONE_DETECT_2, 0x0 },
 150        { WM8996_MIC_DETECT_1, 0x7600 },
 151        { WM8996_MIC_DETECT_2, 0xbf },
 152        { WM8996_CHARGE_PUMP_1, 0x1f25 },
 153        { WM8996_CHARGE_PUMP_2, 0xab19 },
 154        { WM8996_DC_SERVO_1, 0x0 },
 155        { WM8996_DC_SERVO_3, 0x0 },
 156        { WM8996_DC_SERVO_5, 0x2a2a },
 157        { WM8996_DC_SERVO_6, 0x0 },
 158        { WM8996_DC_SERVO_7, 0x0 },
 159        { WM8996_ANALOGUE_HP_1, 0x0 },
 160        { WM8996_ANALOGUE_HP_2, 0x0 },
 161        { WM8996_CONTROL_INTERFACE_1, 0x8004 },
 162        { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
 163        { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
 164        { WM8996_AIF_CLOCKING_1, 0x0 },
 165        { WM8996_AIF_CLOCKING_2, 0x0 },
 166        { WM8996_CLOCKING_1, 0x10 },
 167        { WM8996_CLOCKING_2, 0x0 },
 168        { WM8996_AIF_RATE, 0x83 },
 169        { WM8996_FLL_CONTROL_1, 0x0 },
 170        { WM8996_FLL_CONTROL_2, 0x0 },
 171        { WM8996_FLL_CONTROL_3, 0x0 },
 172        { WM8996_FLL_CONTROL_4, 0x5dc0 },
 173        { WM8996_FLL_CONTROL_5, 0xc84 },
 174        { WM8996_FLL_EFS_1, 0x0 },
 175        { WM8996_FLL_EFS_2, 0x2 },
 176        { WM8996_AIF1_CONTROL, 0x0 },
 177        { WM8996_AIF1_BCLK, 0x0 },
 178        { WM8996_AIF1_TX_LRCLK_1, 0x80 },
 179        { WM8996_AIF1_TX_LRCLK_2, 0x8 },
 180        { WM8996_AIF1_RX_LRCLK_1, 0x80 },
 181        { WM8996_AIF1_RX_LRCLK_2, 0x0 },
 182        { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
 183        { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
 184        { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
 185        { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
 186        { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
 187        { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
 188        { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
 189        { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
 190        { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
 191        { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
 192        { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
 193        { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
 194        { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
 195        { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
 196        { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
 197        { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
 198        { WM8996_AIF1TX_TEST, 0x7 },
 199        { WM8996_AIF2_CONTROL, 0x0 },
 200        { WM8996_AIF2_BCLK, 0x0 },
 201        { WM8996_AIF2_TX_LRCLK_1, 0x80 },
 202        { WM8996_AIF2_TX_LRCLK_2, 0x8 },
 203        { WM8996_AIF2_RX_LRCLK_1, 0x80 },
 204        { WM8996_AIF2_RX_LRCLK_2, 0x0 },
 205        { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
 206        { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
 207        { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
 208        { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
 209        { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
 210        { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
 211        { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
 212        { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
 213        { WM8996_AIF2TX_TEST, 0x1 },
 214        { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
 215        { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
 216        { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
 217        { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
 218        { WM8996_DSP1_TX_FILTERS, 0x2000 },
 219        { WM8996_DSP1_RX_FILTERS_1, 0x200 },
 220        { WM8996_DSP1_RX_FILTERS_2, 0x10 },
 221        { WM8996_DSP1_DRC_1, 0x98 },
 222        { WM8996_DSP1_DRC_2, 0x845 },
 223        { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
 224        { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
 225        { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
 226        { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
 227        { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
 228        { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
 229        { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
 230        { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
 231        { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
 232        { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
 233        { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
 234        { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
 235        { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
 236        { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
 237        { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
 238        { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
 239        { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
 240        { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
 241        { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
 242        { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
 243        { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
 244        { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
 245        { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
 246        { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
 247        { WM8996_DSP2_TX_FILTERS, 0x2000 },
 248        { WM8996_DSP2_RX_FILTERS_1, 0x200 },
 249        { WM8996_DSP2_RX_FILTERS_2, 0x10 },
 250        { WM8996_DSP2_DRC_1, 0x98 },
 251        { WM8996_DSP2_DRC_2, 0x845 },
 252        { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
 253        { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
 254        { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
 255        { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
 256        { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
 257        { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
 258        { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
 259        { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
 260        { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
 261        { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
 262        { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
 263        { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
 264        { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
 265        { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
 266        { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
 267        { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
 268        { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
 269        { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
 270        { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
 271        { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
 272        { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
 273        { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
 274        { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
 275        { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
 276        { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
 277        { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
 278        { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
 279        { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
 280        { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
 281        { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
 282        { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
 283        { WM8996_DAC_SOFTMUTE, 0x0 },
 284        { WM8996_OVERSAMPLING, 0xd },
 285        { WM8996_SIDETONE, 0x1040 },
 286        { WM8996_GPIO_1, 0xa101 },
 287        { WM8996_GPIO_2, 0xa101 },
 288        { WM8996_GPIO_3, 0xa101 },
 289        { WM8996_GPIO_4, 0xa101 },
 290        { WM8996_GPIO_5, 0xa101 },
 291        { WM8996_PULL_CONTROL_1, 0x0 },
 292        { WM8996_PULL_CONTROL_2, 0x140 },
 293        { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
 294        { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
 295        { WM8996_LEFT_PDM_SPEAKER, 0x0 },
 296        { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
 297        { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
 298        { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
 299};
 300
 301static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
 302static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
 303static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 304static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
 305static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
 306static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
 307static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 308static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
 309
 310static const char *sidetone_hpf_text[] = {
 311        "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
 312};
 313
 314static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
 315                            WM8996_SIDETONE, 7, sidetone_hpf_text);
 316
 317static const char *hpf_mode_text[] = {
 318        "HiFi", "Custom", "Voice"
 319};
 320
 321static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
 322                            WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
 323
 324static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
 325                            WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
 326
 327static const char *hpf_cutoff_text[] = {
 328        "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 329};
 330
 331static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
 332                            WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
 333
 334static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
 335                            WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
 336
 337static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
 338{
 339        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 340        struct wm8996_pdata *pdata = &wm8996->pdata;
 341        int base, best, best_val, save, i, cfg, iface;
 342
 343        if (!wm8996->num_retune_mobile_texts)
 344                return;
 345
 346        switch (block) {
 347        case 0:
 348                base = WM8996_DSP1_RX_EQ_GAINS_1;
 349                if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 350                    WM8996_DSP1RX_SRC)
 351                        iface = 1;
 352                else
 353                        iface = 0;
 354                break;
 355        case 1:
 356                base = WM8996_DSP1_RX_EQ_GAINS_2;
 357                if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
 358                    WM8996_DSP2RX_SRC)
 359                        iface = 1;
 360                else
 361                        iface = 0;
 362                break;
 363        default:
 364                return;
 365        }
 366
 367        /* Find the version of the currently selected configuration
 368         * with the nearest sample rate. */
 369        cfg = wm8996->retune_mobile_cfg[block];
 370        best = 0;
 371        best_val = INT_MAX;
 372        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 373                if (strcmp(pdata->retune_mobile_cfgs[i].name,
 374                           wm8996->retune_mobile_texts[cfg]) == 0 &&
 375                    abs(pdata->retune_mobile_cfgs[i].rate
 376                        - wm8996->rx_rate[iface]) < best_val) {
 377                        best = i;
 378                        best_val = abs(pdata->retune_mobile_cfgs[i].rate
 379                                       - wm8996->rx_rate[iface]);
 380                }
 381        }
 382
 383        dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 384                block,
 385                pdata->retune_mobile_cfgs[best].name,
 386                pdata->retune_mobile_cfgs[best].rate,
 387                wm8996->rx_rate[iface]);
 388
 389        /* The EQ will be disabled while reconfiguring it, remember the
 390         * current configuration. 
 391         */
 392        save = snd_soc_read(codec, base);
 393        save &= WM8996_DSP1RX_EQ_ENA;
 394
 395        for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
 396                snd_soc_update_bits(codec, base + i, 0xffff,
 397                                    pdata->retune_mobile_cfgs[best].regs[i]);
 398
 399        snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
 400}
 401
 402/* Icky as hell but saves code duplication */
 403static int wm8996_get_retune_mobile_block(const char *name)
 404{
 405        if (strcmp(name, "DSP1 EQ Mode") == 0)
 406                return 0;
 407        if (strcmp(name, "DSP2 EQ Mode") == 0)
 408                return 1;
 409        return -EINVAL;
 410}
 411
 412static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 413                                         struct snd_ctl_elem_value *ucontrol)
 414{
 415        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 416        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 417        struct wm8996_pdata *pdata = &wm8996->pdata;
 418        int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 419        int value = ucontrol->value.integer.value[0];
 420
 421        if (block < 0)
 422                return block;
 423
 424        if (value >= pdata->num_retune_mobile_cfgs)
 425                return -EINVAL;
 426
 427        wm8996->retune_mobile_cfg[block] = value;
 428
 429        wm8996_set_retune_mobile(codec, block);
 430
 431        return 0;
 432}
 433
 434static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 435                                         struct snd_ctl_elem_value *ucontrol)
 436{
 437        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 438        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 439        int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
 440
 441        if (block < 0)
 442                return block;
 443        ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
 444
 445        return 0;
 446}
 447
 448static const struct snd_kcontrol_new wm8996_snd_controls[] = {
 449SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
 450                 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
 451SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
 452             WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
 453
 454SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
 455               0, 5, 24, 0, sidetone_tlv),
 456SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
 457               0, 5, 24, 0, sidetone_tlv),
 458SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
 459SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
 460SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
 461
 462SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
 463                 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 464SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
 465                 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 466
 467SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
 468           13, 1, 0),
 469SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
 470SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
 471SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
 472
 473SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
 474           13, 1, 0),
 475SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
 476SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
 477SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
 478
 479SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
 480                 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 481SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
 482
 483SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
 484                 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 485SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
 486
 487SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
 488                 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 489SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
 490             WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
 491
 492SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
 493                 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 494SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
 495             WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
 496
 497SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
 498SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
 499SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
 500SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
 501
 502SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
 503SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
 504
 505SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
 506SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
 507
 508SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
 509                0, threedstereo_tlv),
 510SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
 511                0, threedstereo_tlv),
 512
 513SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
 514               8, 0, out_digital_tlv),
 515SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
 516               8, 0, out_digital_tlv),
 517
 518SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
 519                 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 520SOC_DOUBLE_R("Output 1 ZC Switch",  WM8996_OUTPUT1_LEFT_VOLUME,
 521             WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
 522
 523SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
 524                 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 525SOC_DOUBLE_R("Output 2 ZC Switch",  WM8996_OUTPUT2_LEFT_VOLUME,
 526             WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
 527
 528SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
 529               spk_tlv),
 530SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
 531             WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
 532SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
 533             WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
 534
 535SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
 536SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
 537
 538SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
 539SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
 540SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
 541SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
 542                   WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
 543                   WM8996_DSP1TXR_DRC_ENA),
 544
 545SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
 546SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
 547SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
 548SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
 549                   WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
 550                   WM8996_DSP2TXR_DRC_ENA),
 551};
 552
 553static const struct snd_kcontrol_new wm8996_eq_controls[] = {
 554SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
 555               eq_tlv),
 556SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
 557               eq_tlv),
 558SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
 559               eq_tlv),
 560SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
 561               eq_tlv),
 562SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
 563               eq_tlv),
 564
 565SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
 566               eq_tlv),
 567SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
 568               eq_tlv),
 569SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
 570               eq_tlv),
 571SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
 572               eq_tlv),
 573SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
 574               eq_tlv),
 575};
 576
 577static void wm8996_bg_enable(struct snd_soc_codec *codec)
 578{
 579        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 580
 581        wm8996->bg_ena++;
 582        if (wm8996->bg_ena == 1) {
 583                snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
 584                                    WM8996_BG_ENA, WM8996_BG_ENA);
 585                msleep(2);
 586        }
 587}
 588
 589static void wm8996_bg_disable(struct snd_soc_codec *codec)
 590{
 591        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 592
 593        wm8996->bg_ena--;
 594        if (!wm8996->bg_ena)
 595                snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
 596                                    WM8996_BG_ENA, 0);
 597}
 598
 599static int bg_event(struct snd_soc_dapm_widget *w,
 600                    struct snd_kcontrol *kcontrol, int event)
 601{
 602        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 603        int ret = 0;
 604
 605        switch (event) {
 606        case SND_SOC_DAPM_PRE_PMU:
 607                wm8996_bg_enable(codec);
 608                break;
 609        case SND_SOC_DAPM_POST_PMD:
 610                wm8996_bg_disable(codec);
 611                break;
 612        default:
 613                WARN(1, "Invalid event %d\n", event);
 614                ret = -EINVAL;
 615        }
 616
 617        return ret;
 618}
 619
 620static int cp_event(struct snd_soc_dapm_widget *w,
 621                    struct snd_kcontrol *kcontrol, int event)
 622{
 623        switch (event) {
 624        case SND_SOC_DAPM_POST_PMU:
 625                msleep(5);
 626                break;
 627        default:
 628                WARN(1, "Invalid event %d\n", event);
 629        }
 630
 631        return 0;
 632}
 633
 634static int rmv_short_event(struct snd_soc_dapm_widget *w,
 635                           struct snd_kcontrol *kcontrol, int event)
 636{
 637        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 638        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 639
 640        /* Record which outputs we enabled */
 641        switch (event) {
 642        case SND_SOC_DAPM_PRE_PMD:
 643                wm8996->hpout_pending &= ~w->shift;
 644                break;
 645        case SND_SOC_DAPM_PRE_PMU:
 646                wm8996->hpout_pending |= w->shift;
 647                break;
 648        default:
 649                WARN(1, "Invalid event %d\n", event);
 650                return -EINVAL;
 651        }
 652
 653        return 0;
 654}
 655
 656static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
 657{
 658        struct i2c_client *i2c = to_i2c_client(codec->dev);
 659        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 660        int ret;
 661        unsigned long timeout = 200;
 662
 663        snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
 664
 665        /* Use the interrupt if possible */
 666        do {
 667                if (i2c->irq) {
 668                        timeout = wait_for_completion_timeout(&wm8996->dcs_done,
 669                                                              msecs_to_jiffies(200));
 670                        if (timeout == 0)
 671                                dev_err(codec->dev, "DC servo timed out\n");
 672
 673                } else {
 674                        msleep(1);
 675                        timeout--;
 676                }
 677
 678                ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
 679                dev_dbg(codec->dev, "DC servo state: %x\n", ret);
 680        } while (timeout && ret & mask);
 681
 682        if (timeout == 0)
 683                dev_err(codec->dev, "DC servo timed out for %x\n", mask);
 684        else
 685                dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
 686}
 687
 688static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
 689                                enum snd_soc_dapm_type event, int subseq)
 690{
 691        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
 692        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 693        u16 val, mask;
 694
 695        /* Complete any pending DC servo starts */
 696        if (wm8996->dcs_pending) {
 697                dev_dbg(codec->dev, "Starting DC servo for %x\n",
 698                        wm8996->dcs_pending);
 699
 700                /* Trigger a startup sequence */
 701                wait_for_dc_servo(codec, wm8996->dcs_pending
 702                                         << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
 703
 704                wm8996->dcs_pending = 0;
 705        }
 706
 707        if (wm8996->hpout_pending != wm8996->hpout_ena) {
 708                dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
 709                        wm8996->hpout_ena, wm8996->hpout_pending);
 710
 711                val = 0;
 712                mask = 0;
 713                if (wm8996->hpout_pending & HPOUT1L) {
 714                        val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
 715                        mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
 716                } else {
 717                        mask |= WM8996_HPOUT1L_RMV_SHORT |
 718                                WM8996_HPOUT1L_OUTP |
 719                                WM8996_HPOUT1L_DLY;
 720                }
 721
 722                if (wm8996->hpout_pending & HPOUT1R) {
 723                        val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
 724                        mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
 725                } else {
 726                        mask |= WM8996_HPOUT1R_RMV_SHORT |
 727                                WM8996_HPOUT1R_OUTP |
 728                                WM8996_HPOUT1R_DLY;
 729                }
 730
 731                snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
 732
 733                val = 0;
 734                mask = 0;
 735                if (wm8996->hpout_pending & HPOUT2L) {
 736                        val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
 737                        mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
 738                } else {
 739                        mask |= WM8996_HPOUT2L_RMV_SHORT |
 740                                WM8996_HPOUT2L_OUTP |
 741                                WM8996_HPOUT2L_DLY;
 742                }
 743
 744                if (wm8996->hpout_pending & HPOUT2R) {
 745                        val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
 746                        mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
 747                } else {
 748                        mask |= WM8996_HPOUT2R_RMV_SHORT |
 749                                WM8996_HPOUT2R_OUTP |
 750                                WM8996_HPOUT2R_DLY;
 751                }
 752
 753                snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
 754
 755                wm8996->hpout_ena = wm8996->hpout_pending;
 756        }
 757}
 758
 759static int dcs_start(struct snd_soc_dapm_widget *w,
 760                     struct snd_kcontrol *kcontrol, int event)
 761{
 762        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 763        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
 764
 765        switch (event) {
 766        case SND_SOC_DAPM_POST_PMU:
 767                wm8996->dcs_pending |= 1 << w->shift;
 768                break;
 769        default:
 770                WARN(1, "Invalid event %d\n", event);
 771                return -EINVAL;
 772        }
 773
 774        return 0;
 775}
 776
 777static const char *sidetone_text[] = {
 778        "IN1", "IN2",
 779};
 780
 781static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
 782                            WM8996_SIDETONE, 0, sidetone_text);
 783
 784static const struct snd_kcontrol_new left_sidetone =
 785        SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
 786
 787static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
 788                            WM8996_SIDETONE, 1, sidetone_text);
 789
 790static const struct snd_kcontrol_new right_sidetone =
 791        SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
 792
 793static const char *spk_text[] = {
 794        "DAC1L", "DAC1R", "DAC2L", "DAC2R"
 795};
 796
 797static SOC_ENUM_SINGLE_DECL(spkl_enum,
 798                            WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
 799
 800static const struct snd_kcontrol_new spkl_mux =
 801        SOC_DAPM_ENUM("SPKL", spkl_enum);
 802
 803static SOC_ENUM_SINGLE_DECL(spkr_enum,
 804                            WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
 805
 806static const struct snd_kcontrol_new spkr_mux =
 807        SOC_DAPM_ENUM("SPKR", spkr_enum);
 808
 809static const char *dsp1rx_text[] = {
 810        "AIF1", "AIF2"
 811};
 812
 813static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
 814                            WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
 815
 816static const struct snd_kcontrol_new dsp1rx =
 817        SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
 818
 819static const char *dsp2rx_text[] = {
 820         "AIF2", "AIF1"
 821};
 822
 823static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
 824                            WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
 825
 826static const struct snd_kcontrol_new dsp2rx =
 827        SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
 828
 829static const char *aif2tx_text[] = {
 830        "DSP2", "DSP1", "AIF1"
 831};
 832
 833static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
 834                            WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
 835
 836static const struct snd_kcontrol_new aif2tx =
 837        SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
 838
 839static const char *inmux_text[] = {
 840        "ADC", "DMIC1", "DMIC2"
 841};
 842
 843static SOC_ENUM_SINGLE_DECL(in1_enum,
 844                            WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
 845
 846static const struct snd_kcontrol_new in1_mux =
 847        SOC_DAPM_ENUM("IN1 Mux", in1_enum);
 848
 849static SOC_ENUM_SINGLE_DECL(in2_enum,
 850                            WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
 851
 852static const struct snd_kcontrol_new in2_mux =
 853        SOC_DAPM_ENUM("IN2 Mux", in2_enum);
 854
 855static const struct snd_kcontrol_new dac2r_mix[] = {
 856SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
 857                5, 1, 0),
 858SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
 859                4, 1, 0),
 860SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
 861SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
 862};
 863
 864static const struct snd_kcontrol_new dac2l_mix[] = {
 865SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
 866                5, 1, 0),
 867SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
 868                4, 1, 0),
 869SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
 870SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
 871};
 872
 873static const struct snd_kcontrol_new dac1r_mix[] = {
 874SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
 875                5, 1, 0),
 876SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
 877                4, 1, 0),
 878SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
 879SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
 880};
 881
 882static const struct snd_kcontrol_new dac1l_mix[] = {
 883SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
 884                5, 1, 0),
 885SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
 886                4, 1, 0),
 887SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
 888SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
 889};
 890
 891static const struct snd_kcontrol_new dsp1txl[] = {
 892SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
 893                1, 1, 0),
 894SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
 895                0, 1, 0),
 896};
 897
 898static const struct snd_kcontrol_new dsp1txr[] = {
 899SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
 900                1, 1, 0),
 901SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
 902                0, 1, 0),
 903};
 904
 905static const struct snd_kcontrol_new dsp2txl[] = {
 906SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
 907                1, 1, 0),
 908SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
 909                0, 1, 0),
 910};
 911
 912static const struct snd_kcontrol_new dsp2txr[] = {
 913SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
 914                1, 1, 0),
 915SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
 916                0, 1, 0),
 917};
 918
 919
 920static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
 921SND_SOC_DAPM_INPUT("IN1LN"),
 922SND_SOC_DAPM_INPUT("IN1LP"),
 923SND_SOC_DAPM_INPUT("IN1RN"),
 924SND_SOC_DAPM_INPUT("IN1RP"),
 925
 926SND_SOC_DAPM_INPUT("IN2LN"),
 927SND_SOC_DAPM_INPUT("IN2LP"),
 928SND_SOC_DAPM_INPUT("IN2RN"),
 929SND_SOC_DAPM_INPUT("IN2RP"),
 930
 931SND_SOC_DAPM_INPUT("DMIC1DAT"),
 932SND_SOC_DAPM_INPUT("DMIC2DAT"),
 933
 934SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
 935SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
 936SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
 937SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
 938SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
 939                      SND_SOC_DAPM_POST_PMU),
 940SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
 941                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 942SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
 943SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
 944SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
 945SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
 946SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
 947
 948SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
 949SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
 950
 951SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
 952SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
 953SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
 954SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
 955
 956SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
 957SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
 958
 959SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
 960SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
 961SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
 962SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
 963
 964SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
 965SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
 966
 967SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
 968SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
 969
 970SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
 971SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
 972SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
 973SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
 974
 975SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
 976                   dsp2txl, ARRAY_SIZE(dsp2txl)),
 977SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
 978                   dsp2txr, ARRAY_SIZE(dsp2txr)),
 979SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
 980                   dsp1txl, ARRAY_SIZE(dsp1txl)),
 981SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
 982                   dsp1txr, ARRAY_SIZE(dsp1txr)),
 983
 984SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
 985                   dac2l_mix, ARRAY_SIZE(dac2l_mix)),
 986SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
 987                   dac2r_mix, ARRAY_SIZE(dac2r_mix)),
 988SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
 989                   dac1l_mix, ARRAY_SIZE(dac1l_mix)),
 990SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
 991                   dac1r_mix, ARRAY_SIZE(dac1r_mix)),
 992
 993SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
 994SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
 995SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
 996SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
 997
 998SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
 999SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
1000
1001SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
1002SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
1003
1004SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1005SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1006SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1007SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1008SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1009SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1010
1011SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1012SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1013SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1014SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1015SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1016SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1017
1018/* We route as stereo pairs so define some dummy widgets to squash
1019 * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
1020SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1021SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1022SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1023SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1024SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1025
1026SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1027SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1028SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1029
1030SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1031SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1032SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1033SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1034
1035SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1036SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1037SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1038                   SND_SOC_DAPM_POST_PMU),
1039SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1040                   rmv_short_event,
1041                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1042
1043SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1044SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1045SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1046                   SND_SOC_DAPM_POST_PMU),
1047SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1048                   rmv_short_event,
1049                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1050
1051SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1052SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1053SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1054                   SND_SOC_DAPM_POST_PMU),
1055SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1056                   rmv_short_event,
1057                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1058
1059SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1060SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1061SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1062                   SND_SOC_DAPM_POST_PMU),
1063SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1064                   rmv_short_event,
1065                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1066
1067SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1068SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1069SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1070SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1071SND_SOC_DAPM_OUTPUT("SPKDAT"),
1072};
1073
1074static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1075        { "AIFCLK", NULL, "SYSCLK" },
1076        { "SYSDSPCLK", NULL, "SYSCLK" },
1077        { "Charge Pump", NULL, "SYSCLK" },
1078        { "Charge Pump", NULL, "CPVDD" },
1079
1080        { "MICB1", NULL, "LDO2" },
1081        { "MICB1", NULL, "MICB1 Audio" },
1082        { "MICB1", NULL, "Bandgap" },
1083        { "MICB2", NULL, "LDO2" },
1084        { "MICB2", NULL, "MICB2 Audio" },
1085        { "MICB2", NULL, "Bandgap" },
1086
1087        { "AIF1RX0", NULL, "AIF1 Playback" },
1088        { "AIF1RX1", NULL, "AIF1 Playback" },
1089        { "AIF1RX2", NULL, "AIF1 Playback" },
1090        { "AIF1RX3", NULL, "AIF1 Playback" },
1091        { "AIF1RX4", NULL, "AIF1 Playback" },
1092        { "AIF1RX5", NULL, "AIF1 Playback" },
1093
1094        { "AIF2RX0", NULL, "AIF2 Playback" },
1095        { "AIF2RX1", NULL, "AIF2 Playback" },
1096
1097        { "AIF1 Capture", NULL, "AIF1TX0" },
1098        { "AIF1 Capture", NULL, "AIF1TX1" },
1099        { "AIF1 Capture", NULL, "AIF1TX2" },
1100        { "AIF1 Capture", NULL, "AIF1TX3" },
1101        { "AIF1 Capture", NULL, "AIF1TX4" },
1102        { "AIF1 Capture", NULL, "AIF1TX5" },
1103
1104        { "AIF2 Capture", NULL, "AIF2TX0" },
1105        { "AIF2 Capture", NULL, "AIF2TX1" },
1106
1107        { "IN1L PGA", NULL, "IN2LN" },
1108        { "IN1L PGA", NULL, "IN2LP" },
1109        { "IN1L PGA", NULL, "IN1LN" },
1110        { "IN1L PGA", NULL, "IN1LP" },
1111        { "IN1L PGA", NULL, "Bandgap" },
1112
1113        { "IN1R PGA", NULL, "IN2RN" },
1114        { "IN1R PGA", NULL, "IN2RP" },
1115        { "IN1R PGA", NULL, "IN1RN" },
1116        { "IN1R PGA", NULL, "IN1RP" },
1117        { "IN1R PGA", NULL, "Bandgap" },
1118
1119        { "ADCL", NULL, "IN1L PGA" },
1120
1121        { "ADCR", NULL, "IN1R PGA" },
1122
1123        { "DMIC1L", NULL, "DMIC1DAT" },
1124        { "DMIC1R", NULL, "DMIC1DAT" },
1125        { "DMIC2L", NULL, "DMIC2DAT" },
1126        { "DMIC2R", NULL, "DMIC2DAT" },
1127
1128        { "DMIC2L", NULL, "DMIC2" },
1129        { "DMIC2R", NULL, "DMIC2" },
1130        { "DMIC1L", NULL, "DMIC1" },
1131        { "DMIC1R", NULL, "DMIC1" },
1132
1133        { "IN1L Mux", "ADC", "ADCL" },
1134        { "IN1L Mux", "DMIC1", "DMIC1L" },
1135        { "IN1L Mux", "DMIC2", "DMIC2L" },
1136
1137        { "IN1R Mux", "ADC", "ADCR" },
1138        { "IN1R Mux", "DMIC1", "DMIC1R" },
1139        { "IN1R Mux", "DMIC2", "DMIC2R" },
1140
1141        { "IN2L Mux", "ADC", "ADCL" },
1142        { "IN2L Mux", "DMIC1", "DMIC1L" },
1143        { "IN2L Mux", "DMIC2", "DMIC2L" },
1144
1145        { "IN2R Mux", "ADC", "ADCR" },
1146        { "IN2R Mux", "DMIC1", "DMIC1R" },
1147        { "IN2R Mux", "DMIC2", "DMIC2R" },
1148
1149        { "Left Sidetone", "IN1", "IN1L Mux" },
1150        { "Left Sidetone", "IN2", "IN2L Mux" },
1151
1152        { "Right Sidetone", "IN1", "IN1R Mux" },
1153        { "Right Sidetone", "IN2", "IN2R Mux" },
1154
1155        { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1156        { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1157
1158        { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1159        { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1160
1161        { "AIF1TX0", NULL, "DSP1TXL" },
1162        { "AIF1TX1", NULL, "DSP1TXR" },
1163        { "AIF1TX2", NULL, "DSP2TXL" },
1164        { "AIF1TX3", NULL, "DSP2TXR" },
1165        { "AIF1TX4", NULL, "AIF2RX0" },
1166        { "AIF1TX5", NULL, "AIF2RX1" },
1167
1168        { "AIF1RX0", NULL, "AIFCLK" },
1169        { "AIF1RX1", NULL, "AIFCLK" },
1170        { "AIF1RX2", NULL, "AIFCLK" },
1171        { "AIF1RX3", NULL, "AIFCLK" },
1172        { "AIF1RX4", NULL, "AIFCLK" },
1173        { "AIF1RX5", NULL, "AIFCLK" },
1174
1175        { "AIF2RX0", NULL, "AIFCLK" },
1176        { "AIF2RX1", NULL, "AIFCLK" },
1177
1178        { "AIF1TX0", NULL, "AIFCLK" },
1179        { "AIF1TX1", NULL, "AIFCLK" },
1180        { "AIF1TX2", NULL, "AIFCLK" },
1181        { "AIF1TX3", NULL, "AIFCLK" },
1182        { "AIF1TX4", NULL, "AIFCLK" },
1183        { "AIF1TX5", NULL, "AIFCLK" },
1184
1185        { "AIF2TX0", NULL, "AIFCLK" },
1186        { "AIF2TX1", NULL, "AIFCLK" },
1187
1188        { "DSP1RXL", NULL, "SYSDSPCLK" },
1189        { "DSP1RXR", NULL, "SYSDSPCLK" },
1190        { "DSP2RXL", NULL, "SYSDSPCLK" },
1191        { "DSP2RXR", NULL, "SYSDSPCLK" },
1192        { "DSP1TXL", NULL, "SYSDSPCLK" },
1193        { "DSP1TXR", NULL, "SYSDSPCLK" },
1194        { "DSP2TXL", NULL, "SYSDSPCLK" },
1195        { "DSP2TXR", NULL, "SYSDSPCLK" },
1196
1197        { "AIF1RXA", NULL, "AIF1RX0" },
1198        { "AIF1RXA", NULL, "AIF1RX1" },
1199        { "AIF1RXB", NULL, "AIF1RX2" },
1200        { "AIF1RXB", NULL, "AIF1RX3" },
1201        { "AIF1RXC", NULL, "AIF1RX4" },
1202        { "AIF1RXC", NULL, "AIF1RX5" },
1203
1204        { "AIF2RX", NULL, "AIF2RX0" },
1205        { "AIF2RX", NULL, "AIF2RX1" },
1206
1207        { "AIF2TX", "DSP2", "DSP2TX" },
1208        { "AIF2TX", "DSP1", "DSP1RX" },
1209        { "AIF2TX", "AIF1", "AIF1RXC" },
1210
1211        { "DSP1RXL", NULL, "DSP1RX" },
1212        { "DSP1RXR", NULL, "DSP1RX" },
1213        { "DSP2RXL", NULL, "DSP2RX" },
1214        { "DSP2RXR", NULL, "DSP2RX" },
1215
1216        { "DSP2TX", NULL, "DSP2TXL" },
1217        { "DSP2TX", NULL, "DSP2TXR" },
1218
1219        { "DSP1RX", "AIF1", "AIF1RXA" },
1220        { "DSP1RX", "AIF2", "AIF2RX" },
1221
1222        { "DSP2RX", "AIF1", "AIF1RXB" },
1223        { "DSP2RX", "AIF2", "AIF2RX" },
1224
1225        { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1226        { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1227        { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1228        { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1229
1230        { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1231        { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1232        { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1233        { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1234
1235        { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1236        { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1237        { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1238        { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1239
1240        { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1241        { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1242        { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1243        { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1244
1245        { "DAC1L", NULL, "DAC1L Mixer" },
1246        { "DAC1R", NULL, "DAC1R Mixer" },
1247        { "DAC2L", NULL, "DAC2L Mixer" },
1248        { "DAC2R", NULL, "DAC2R Mixer" },
1249
1250        { "HPOUT2L PGA", NULL, "Charge Pump" },
1251        { "HPOUT2L PGA", NULL, "Bandgap" },
1252        { "HPOUT2L PGA", NULL, "DAC2L" },
1253        { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1254        { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1255        { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1256
1257        { "HPOUT2R PGA", NULL, "Charge Pump" },
1258        { "HPOUT2R PGA", NULL, "Bandgap" },
1259        { "HPOUT2R PGA", NULL, "DAC2R" },
1260        { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1261        { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1262        { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1263
1264        { "HPOUT1L PGA", NULL, "Charge Pump" },
1265        { "HPOUT1L PGA", NULL, "Bandgap" },
1266        { "HPOUT1L PGA", NULL, "DAC1L" },
1267        { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1268        { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1269        { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1270
1271        { "HPOUT1R PGA", NULL, "Charge Pump" },
1272        { "HPOUT1R PGA", NULL, "Bandgap" },
1273        { "HPOUT1R PGA", NULL, "DAC1R" },
1274        { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1275        { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1276        { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1277
1278        { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1279        { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1280        { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1281        { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1282
1283        { "SPKL", "DAC1L", "DAC1L" },
1284        { "SPKL", "DAC1R", "DAC1R" },
1285        { "SPKL", "DAC2L", "DAC2L" },
1286        { "SPKL", "DAC2R", "DAC2R" },
1287
1288        { "SPKR", "DAC1L", "DAC1L" },
1289        { "SPKR", "DAC1R", "DAC1R" },
1290        { "SPKR", "DAC2L", "DAC2L" },
1291        { "SPKR", "DAC2R", "DAC2R" },
1292
1293        { "SPKL PGA", NULL, "SPKL" },
1294        { "SPKR PGA", NULL, "SPKR" },
1295
1296        { "SPKDAT", NULL, "SPKL PGA" },
1297        { "SPKDAT", NULL, "SPKR PGA" },
1298};
1299
1300static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1301{
1302        /* Due to the sparseness of the register map the compiler
1303         * output from an explicit switch statement ends up being much
1304         * more efficient than a table.
1305         */
1306        switch (reg) {
1307        case WM8996_SOFTWARE_RESET:
1308        case WM8996_POWER_MANAGEMENT_1:
1309        case WM8996_POWER_MANAGEMENT_2:
1310        case WM8996_POWER_MANAGEMENT_3:
1311        case WM8996_POWER_MANAGEMENT_4:
1312        case WM8996_POWER_MANAGEMENT_5:
1313        case WM8996_POWER_MANAGEMENT_6:
1314        case WM8996_POWER_MANAGEMENT_7:
1315        case WM8996_POWER_MANAGEMENT_8:
1316        case WM8996_LEFT_LINE_INPUT_VOLUME:
1317        case WM8996_RIGHT_LINE_INPUT_VOLUME:
1318        case WM8996_LINE_INPUT_CONTROL:
1319        case WM8996_DAC1_HPOUT1_VOLUME:
1320        case WM8996_DAC2_HPOUT2_VOLUME:
1321        case WM8996_DAC1_LEFT_VOLUME:
1322        case WM8996_DAC1_RIGHT_VOLUME:
1323        case WM8996_DAC2_LEFT_VOLUME:
1324        case WM8996_DAC2_RIGHT_VOLUME:
1325        case WM8996_OUTPUT1_LEFT_VOLUME:
1326        case WM8996_OUTPUT1_RIGHT_VOLUME:
1327        case WM8996_OUTPUT2_LEFT_VOLUME:
1328        case WM8996_OUTPUT2_RIGHT_VOLUME:
1329        case WM8996_MICBIAS_1:
1330        case WM8996_MICBIAS_2:
1331        case WM8996_LDO_1:
1332        case WM8996_LDO_2:
1333        case WM8996_ACCESSORY_DETECT_MODE_1:
1334        case WM8996_ACCESSORY_DETECT_MODE_2:
1335        case WM8996_HEADPHONE_DETECT_1:
1336        case WM8996_HEADPHONE_DETECT_2:
1337        case WM8996_MIC_DETECT_1:
1338        case WM8996_MIC_DETECT_2:
1339        case WM8996_MIC_DETECT_3:
1340        case WM8996_CHARGE_PUMP_1:
1341        case WM8996_CHARGE_PUMP_2:
1342        case WM8996_DC_SERVO_1:
1343        case WM8996_DC_SERVO_2:
1344        case WM8996_DC_SERVO_3:
1345        case WM8996_DC_SERVO_5:
1346        case WM8996_DC_SERVO_6:
1347        case WM8996_DC_SERVO_7:
1348        case WM8996_DC_SERVO_READBACK_0:
1349        case WM8996_ANALOGUE_HP_1:
1350        case WM8996_ANALOGUE_HP_2:
1351        case WM8996_CHIP_REVISION:
1352        case WM8996_CONTROL_INTERFACE_1:
1353        case WM8996_WRITE_SEQUENCER_CTRL_1:
1354        case WM8996_WRITE_SEQUENCER_CTRL_2:
1355        case WM8996_AIF_CLOCKING_1:
1356        case WM8996_AIF_CLOCKING_2:
1357        case WM8996_CLOCKING_1:
1358        case WM8996_CLOCKING_2:
1359        case WM8996_AIF_RATE:
1360        case WM8996_FLL_CONTROL_1:
1361        case WM8996_FLL_CONTROL_2:
1362        case WM8996_FLL_CONTROL_3:
1363        case WM8996_FLL_CONTROL_4:
1364        case WM8996_FLL_CONTROL_5:
1365        case WM8996_FLL_CONTROL_6:
1366        case WM8996_FLL_EFS_1:
1367        case WM8996_FLL_EFS_2:
1368        case WM8996_AIF1_CONTROL:
1369        case WM8996_AIF1_BCLK:
1370        case WM8996_AIF1_TX_LRCLK_1:
1371        case WM8996_AIF1_TX_LRCLK_2:
1372        case WM8996_AIF1_RX_LRCLK_1:
1373        case WM8996_AIF1_RX_LRCLK_2:
1374        case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1375        case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1376        case WM8996_AIF1RX_DATA_CONFIGURATION:
1377        case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1378        case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1379        case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1380        case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1381        case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1382        case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1383        case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1384        case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1385        case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1386        case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1387        case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1388        case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1389        case WM8996_AIF1RX_MONO_CONFIGURATION:
1390        case WM8996_AIF1TX_TEST:
1391        case WM8996_AIF2_CONTROL:
1392        case WM8996_AIF2_BCLK:
1393        case WM8996_AIF2_TX_LRCLK_1:
1394        case WM8996_AIF2_TX_LRCLK_2:
1395        case WM8996_AIF2_RX_LRCLK_1:
1396        case WM8996_AIF2_RX_LRCLK_2:
1397        case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1398        case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1399        case WM8996_AIF2RX_DATA_CONFIGURATION:
1400        case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1401        case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1402        case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1403        case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1404        case WM8996_AIF2RX_MONO_CONFIGURATION:
1405        case WM8996_AIF2TX_TEST:
1406        case WM8996_DSP1_TX_LEFT_VOLUME:
1407        case WM8996_DSP1_TX_RIGHT_VOLUME:
1408        case WM8996_DSP1_RX_LEFT_VOLUME:
1409        case WM8996_DSP1_RX_RIGHT_VOLUME:
1410        case WM8996_DSP1_TX_FILTERS:
1411        case WM8996_DSP1_RX_FILTERS_1:
1412        case WM8996_DSP1_RX_FILTERS_2:
1413        case WM8996_DSP1_DRC_1:
1414        case WM8996_DSP1_DRC_2:
1415        case WM8996_DSP1_DRC_3:
1416        case WM8996_DSP1_DRC_4:
1417        case WM8996_DSP1_DRC_5:
1418        case WM8996_DSP1_RX_EQ_GAINS_1:
1419        case WM8996_DSP1_RX_EQ_GAINS_2:
1420        case WM8996_DSP1_RX_EQ_BAND_1_A:
1421        case WM8996_DSP1_RX_EQ_BAND_1_B:
1422        case WM8996_DSP1_RX_EQ_BAND_1_PG:
1423        case WM8996_DSP1_RX_EQ_BAND_2_A:
1424        case WM8996_DSP1_RX_EQ_BAND_2_B:
1425        case WM8996_DSP1_RX_EQ_BAND_2_C:
1426        case WM8996_DSP1_RX_EQ_BAND_2_PG:
1427        case WM8996_DSP1_RX_EQ_BAND_3_A:
1428        case WM8996_DSP1_RX_EQ_BAND_3_B:
1429        case WM8996_DSP1_RX_EQ_BAND_3_C:
1430        case WM8996_DSP1_RX_EQ_BAND_3_PG:
1431        case WM8996_DSP1_RX_EQ_BAND_4_A:
1432        case WM8996_DSP1_RX_EQ_BAND_4_B:
1433        case WM8996_DSP1_RX_EQ_BAND_4_C:
1434        case WM8996_DSP1_RX_EQ_BAND_4_PG:
1435        case WM8996_DSP1_RX_EQ_BAND_5_A:
1436        case WM8996_DSP1_RX_EQ_BAND_5_B:
1437        case WM8996_DSP1_RX_EQ_BAND_5_PG:
1438        case WM8996_DSP2_TX_LEFT_VOLUME:
1439        case WM8996_DSP2_TX_RIGHT_VOLUME:
1440        case WM8996_DSP2_RX_LEFT_VOLUME:
1441        case WM8996_DSP2_RX_RIGHT_VOLUME:
1442        case WM8996_DSP2_TX_FILTERS:
1443        case WM8996_DSP2_RX_FILTERS_1:
1444        case WM8996_DSP2_RX_FILTERS_2:
1445        case WM8996_DSP2_DRC_1:
1446        case WM8996_DSP2_DRC_2:
1447        case WM8996_DSP2_DRC_3:
1448        case WM8996_DSP2_DRC_4:
1449        case WM8996_DSP2_DRC_5:
1450        case WM8996_DSP2_RX_EQ_GAINS_1:
1451        case WM8996_DSP2_RX_EQ_GAINS_2:
1452        case WM8996_DSP2_RX_EQ_BAND_1_A:
1453        case WM8996_DSP2_RX_EQ_BAND_1_B:
1454        case WM8996_DSP2_RX_EQ_BAND_1_PG:
1455        case WM8996_DSP2_RX_EQ_BAND_2_A:
1456        case WM8996_DSP2_RX_EQ_BAND_2_B:
1457        case WM8996_DSP2_RX_EQ_BAND_2_C:
1458        case WM8996_DSP2_RX_EQ_BAND_2_PG:
1459        case WM8996_DSP2_RX_EQ_BAND_3_A:
1460        case WM8996_DSP2_RX_EQ_BAND_3_B:
1461        case WM8996_DSP2_RX_EQ_BAND_3_C:
1462        case WM8996_DSP2_RX_EQ_BAND_3_PG:
1463        case WM8996_DSP2_RX_EQ_BAND_4_A:
1464        case WM8996_DSP2_RX_EQ_BAND_4_B:
1465        case WM8996_DSP2_RX_EQ_BAND_4_C:
1466        case WM8996_DSP2_RX_EQ_BAND_4_PG:
1467        case WM8996_DSP2_RX_EQ_BAND_5_A:
1468        case WM8996_DSP2_RX_EQ_BAND_5_B:
1469        case WM8996_DSP2_RX_EQ_BAND_5_PG:
1470        case WM8996_DAC1_MIXER_VOLUMES:
1471        case WM8996_DAC1_LEFT_MIXER_ROUTING:
1472        case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1473        case WM8996_DAC2_MIXER_VOLUMES:
1474        case WM8996_DAC2_LEFT_MIXER_ROUTING:
1475        case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1476        case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1477        case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1478        case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1479        case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1480        case WM8996_DSP_TX_MIXER_SELECT:
1481        case WM8996_DAC_SOFTMUTE:
1482        case WM8996_OVERSAMPLING:
1483        case WM8996_SIDETONE:
1484        case WM8996_GPIO_1:
1485        case WM8996_GPIO_2:
1486        case WM8996_GPIO_3:
1487        case WM8996_GPIO_4:
1488        case WM8996_GPIO_5:
1489        case WM8996_PULL_CONTROL_1:
1490        case WM8996_PULL_CONTROL_2:
1491        case WM8996_INTERRUPT_STATUS_1:
1492        case WM8996_INTERRUPT_STATUS_2:
1493        case WM8996_INTERRUPT_RAW_STATUS_2:
1494        case WM8996_INTERRUPT_STATUS_1_MASK:
1495        case WM8996_INTERRUPT_STATUS_2_MASK:
1496        case WM8996_INTERRUPT_CONTROL:
1497        case WM8996_LEFT_PDM_SPEAKER:
1498        case WM8996_RIGHT_PDM_SPEAKER:
1499        case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1500        case WM8996_PDM_SPEAKER_VOLUME:
1501                return 1;
1502        default:
1503                return 0;
1504        }
1505}
1506
1507static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1508{
1509        switch (reg) {
1510        case WM8996_SOFTWARE_RESET:
1511        case WM8996_CHIP_REVISION:
1512        case WM8996_LDO_1:
1513        case WM8996_LDO_2:
1514        case WM8996_INTERRUPT_STATUS_1:
1515        case WM8996_INTERRUPT_STATUS_2:
1516        case WM8996_INTERRUPT_RAW_STATUS_2:
1517        case WM8996_DC_SERVO_READBACK_0:
1518        case WM8996_DC_SERVO_2:
1519        case WM8996_DC_SERVO_6:
1520        case WM8996_DC_SERVO_7:
1521        case WM8996_FLL_CONTROL_6:
1522        case WM8996_MIC_DETECT_3:
1523        case WM8996_HEADPHONE_DETECT_1:
1524        case WM8996_HEADPHONE_DETECT_2:
1525                return 1;
1526        default:
1527                return 0;
1528        }
1529}
1530
1531static const int bclk_divs[] = {
1532        1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1533};
1534
1535static void wm8996_update_bclk(struct snd_soc_codec *codec)
1536{
1537        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1538        int aif, best, cur_val, bclk_rate, bclk_reg, i;
1539
1540        /* Don't bother if we're in a low frequency idle mode that
1541         * can't support audio.
1542         */
1543        if (wm8996->sysclk < 64000)
1544                return;
1545
1546        for (aif = 0; aif < WM8996_AIFS; aif++) {
1547                switch (aif) {
1548                case 0:
1549                        bclk_reg = WM8996_AIF1_BCLK;
1550                        break;
1551                case 1:
1552                        bclk_reg = WM8996_AIF2_BCLK;
1553                        break;
1554                }
1555
1556                bclk_rate = wm8996->bclk_rate[aif];
1557
1558                /* Pick a divisor for BCLK as close as we can get to ideal */
1559                best = 0;
1560                for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1561                        cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1562                        if (cur_val < 0) /* BCLK table is sorted */
1563                                break;
1564                        best = i;
1565                }
1566                bclk_rate = wm8996->sysclk / bclk_divs[best];
1567                dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1568                        bclk_divs[best], bclk_rate);
1569
1570                snd_soc_update_bits(codec, bclk_reg,
1571                                    WM8996_AIF1_BCLK_DIV_MASK, best);
1572        }
1573}
1574
1575static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1576                                 enum snd_soc_bias_level level)
1577{
1578        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1579        int ret;
1580
1581        switch (level) {
1582        case SND_SOC_BIAS_ON:
1583                break;
1584        case SND_SOC_BIAS_PREPARE:
1585                /* Put the MICBIASes into regulating mode */
1586                snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1587                                    WM8996_MICB1_MODE, 0);
1588                snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1589                                    WM8996_MICB2_MODE, 0);
1590                break;
1591
1592        case SND_SOC_BIAS_STANDBY:
1593                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1594                        ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1595                                                    wm8996->supplies);
1596                        if (ret != 0) {
1597                                dev_err(codec->dev,
1598                                        "Failed to enable supplies: %d\n",
1599                                        ret);
1600                                return ret;
1601                        }
1602
1603                        if (wm8996->pdata.ldo_ena >= 0) {
1604                                gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1605                                                        1);
1606                                msleep(5);
1607                        }
1608
1609                        regcache_cache_only(wm8996->regmap, false);
1610                        regcache_sync(wm8996->regmap);
1611                }
1612
1613                /* Bypass the MICBIASes for lowest power */
1614                snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1615                                    WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1616                snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1617                                    WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1618                break;
1619
1620        case SND_SOC_BIAS_OFF:
1621                regcache_cache_only(wm8996->regmap, true);
1622                if (wm8996->pdata.ldo_ena >= 0) {
1623                        gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1624                        regcache_cache_only(wm8996->regmap, true);
1625                }
1626                regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1627                                       wm8996->supplies);
1628                break;
1629        }
1630
1631        codec->dapm.bias_level = level;
1632
1633        return 0;
1634}
1635
1636static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1637{
1638        struct snd_soc_codec *codec = dai->codec;
1639        int aifctrl = 0;
1640        int bclk = 0;
1641        int lrclk_tx = 0;
1642        int lrclk_rx = 0;
1643        int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1644
1645        switch (dai->id) {
1646        case 0:
1647                aifctrl_reg = WM8996_AIF1_CONTROL;
1648                bclk_reg = WM8996_AIF1_BCLK;
1649                lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1650                lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1651                break;
1652        case 1:
1653                aifctrl_reg = WM8996_AIF2_CONTROL;
1654                bclk_reg = WM8996_AIF2_BCLK;
1655                lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1656                lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1657                break;
1658        default:
1659                WARN(1, "Invalid dai id %d\n", dai->id);
1660                return -EINVAL;
1661        }
1662
1663        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1664        case SND_SOC_DAIFMT_NB_NF:
1665                break;
1666        case SND_SOC_DAIFMT_IB_NF:
1667                bclk |= WM8996_AIF1_BCLK_INV;
1668                break;
1669        case SND_SOC_DAIFMT_NB_IF:
1670                lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1671                lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1672                break;
1673        case SND_SOC_DAIFMT_IB_IF:
1674                bclk |= WM8996_AIF1_BCLK_INV;
1675                lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1676                lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1677                break;
1678        }
1679
1680        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1681        case SND_SOC_DAIFMT_CBS_CFS:
1682                break;
1683        case SND_SOC_DAIFMT_CBS_CFM:
1684                lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1685                lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1686                break;
1687        case SND_SOC_DAIFMT_CBM_CFS:
1688                bclk |= WM8996_AIF1_BCLK_MSTR;
1689                break;
1690        case SND_SOC_DAIFMT_CBM_CFM:
1691                bclk |= WM8996_AIF1_BCLK_MSTR;
1692                lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1693                lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1694                break;
1695        default:
1696                return -EINVAL;
1697        }
1698
1699        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1700        case SND_SOC_DAIFMT_DSP_A:
1701                break;
1702        case SND_SOC_DAIFMT_DSP_B:
1703                aifctrl |= 1;
1704                break;
1705        case SND_SOC_DAIFMT_I2S:
1706                aifctrl |= 2;
1707                break;
1708        case SND_SOC_DAIFMT_LEFT_J:
1709                aifctrl |= 3;
1710                break;
1711        default:
1712                return -EINVAL;
1713        }
1714
1715        snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1716        snd_soc_update_bits(codec, bclk_reg,
1717                            WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1718                            bclk);
1719        snd_soc_update_bits(codec, lrclk_tx_reg,
1720                            WM8996_AIF1TX_LRCLK_INV |
1721                            WM8996_AIF1TX_LRCLK_MSTR,
1722                            lrclk_tx);
1723        snd_soc_update_bits(codec, lrclk_rx_reg,
1724                            WM8996_AIF1RX_LRCLK_INV |
1725                            WM8996_AIF1RX_LRCLK_MSTR,
1726                            lrclk_rx);
1727
1728        return 0;
1729}
1730
1731static const int dsp_divs[] = {
1732        48000, 32000, 16000, 8000
1733};
1734
1735static int wm8996_hw_params(struct snd_pcm_substream *substream,
1736                            struct snd_pcm_hw_params *params,
1737                            struct snd_soc_dai *dai)
1738{
1739        struct snd_soc_codec *codec = dai->codec;
1740        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1741        int bits, i, bclk_rate, best;
1742        int aifdata = 0;
1743        int lrclk = 0;
1744        int dsp = 0;
1745        int aifdata_reg, lrclk_reg, dsp_shift;
1746
1747        switch (dai->id) {
1748        case 0:
1749                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1750                    (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1751                        aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1752                        lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1753                } else {
1754                        aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1755                        lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1756                }
1757                dsp_shift = 0;
1758                break;
1759        case 1:
1760                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1761                    (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1762                        aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1763                        lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1764                } else {
1765                        aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1766                        lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1767                }
1768                dsp_shift = WM8996_DSP2_DIV_SHIFT;
1769                break;
1770        default:
1771                WARN(1, "Invalid dai id %d\n", dai->id);
1772                return -EINVAL;
1773        }
1774
1775        bclk_rate = snd_soc_params_to_bclk(params);
1776        if (bclk_rate < 0) {
1777                dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1778                return bclk_rate;
1779        }
1780
1781        wm8996->bclk_rate[dai->id] = bclk_rate;
1782        wm8996->rx_rate[dai->id] = params_rate(params);
1783
1784        /* Needs looking at for TDM */
1785        bits = snd_pcm_format_width(params_format(params));
1786        if (bits < 0)
1787                return bits;
1788        aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1789
1790        best = 0;
1791        for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1792                if (abs(dsp_divs[i] - params_rate(params)) <
1793                    abs(dsp_divs[best] - params_rate(params)))
1794                        best = i;
1795        }
1796        dsp |= i << dsp_shift;
1797
1798        wm8996_update_bclk(codec);
1799
1800        lrclk = bclk_rate / params_rate(params);
1801        dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1802                lrclk, bclk_rate / lrclk);
1803
1804        snd_soc_update_bits(codec, aifdata_reg,
1805                            WM8996_AIF1TX_WL_MASK |
1806                            WM8996_AIF1TX_SLOT_LEN_MASK,
1807                            aifdata);
1808        snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1809                            lrclk);
1810        snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1811                            WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1812
1813        return 0;
1814}
1815
1816static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1817                int clk_id, unsigned int freq, int dir)
1818{
1819        struct snd_soc_codec *codec = dai->codec;
1820        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1821        int lfclk = 0;
1822        int ratediv = 0;
1823        int sync = WM8996_REG_SYNC;
1824        int src;
1825        int old;
1826
1827        if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1828                return 0;
1829
1830        /* Disable SYSCLK while we reconfigure */
1831        old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1832        snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1833                            WM8996_SYSCLK_ENA, 0);
1834
1835        switch (clk_id) {
1836        case WM8996_SYSCLK_MCLK1:
1837                wm8996->sysclk = freq;
1838                src = 0;
1839                break;
1840        case WM8996_SYSCLK_MCLK2:
1841                wm8996->sysclk = freq;
1842                src = 1;
1843                break;
1844        case WM8996_SYSCLK_FLL:
1845                wm8996->sysclk = freq;
1846                src = 2;
1847                break;
1848        default:
1849                dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1850                return -EINVAL;
1851        }
1852
1853        switch (wm8996->sysclk) {
1854        case 5644800:
1855        case 6144000:
1856                snd_soc_update_bits(codec, WM8996_AIF_RATE,
1857                                    WM8996_SYSCLK_RATE, 0);
1858                break;
1859        case 22579200:
1860        case 24576000:
1861                ratediv = WM8996_SYSCLK_DIV;
1862                wm8996->sysclk /= 2;
1863        case 11289600:
1864        case 12288000:
1865                snd_soc_update_bits(codec, WM8996_AIF_RATE,
1866                                    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1867                break;
1868        case 32000:
1869        case 32768:
1870                lfclk = WM8996_LFCLK_ENA;
1871                sync = 0;
1872                break;
1873        default:
1874                dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1875                         wm8996->sysclk);
1876                return -EINVAL;
1877        }
1878
1879        wm8996_update_bclk(codec);
1880
1881        snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1882                            WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1883                            src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1884        snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1885        snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
1886                            WM8996_REG_SYNC, sync);
1887        snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1888                            WM8996_SYSCLK_ENA, old);
1889
1890        wm8996->sysclk_src = clk_id;
1891
1892        return 0;
1893}
1894
1895struct _fll_div {
1896        u16 fll_fratio;
1897        u16 fll_outdiv;
1898        u16 fll_refclk_div;
1899        u16 fll_loop_gain;
1900        u16 fll_ref_freq;
1901        u16 n;
1902        u16 theta;
1903        u16 lambda;
1904};
1905
1906static struct {
1907        unsigned int min;
1908        unsigned int max;
1909        u16 fll_fratio;
1910        int ratio;
1911} fll_fratios[] = {
1912        {       0,    64000, 4, 16 },
1913        {   64000,   128000, 3,  8 },
1914        {  128000,   256000, 2,  4 },
1915        {  256000,  1000000, 1,  2 },
1916        { 1000000, 13500000, 0,  1 },
1917};
1918
1919static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1920                       unsigned int Fout)
1921{
1922        unsigned int target;
1923        unsigned int div;
1924        unsigned int fratio, gcd_fll;
1925        int i;
1926
1927        /* Fref must be <=13.5MHz */
1928        div = 1;
1929        fll_div->fll_refclk_div = 0;
1930        while ((Fref / div) > 13500000) {
1931                div *= 2;
1932                fll_div->fll_refclk_div++;
1933
1934                if (div > 8) {
1935                        pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1936                               Fref);
1937                        return -EINVAL;
1938                }
1939        }
1940
1941        pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1942
1943        /* Apply the division for our remaining calculations */
1944        Fref /= div;
1945
1946        if (Fref >= 3000000)
1947                fll_div->fll_loop_gain = 5;
1948        else
1949                fll_div->fll_loop_gain = 0;
1950
1951        if (Fref >= 48000)
1952                fll_div->fll_ref_freq = 0;
1953        else
1954                fll_div->fll_ref_freq = 1;
1955
1956        /* Fvco should be 90-100MHz; don't check the upper bound */
1957        div = 2;
1958        while (Fout * div < 90000000) {
1959                div++;
1960                if (div > 64) {
1961                        pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1962                               Fout);
1963                        return -EINVAL;
1964                }
1965        }
1966        target = Fout * div;
1967        fll_div->fll_outdiv = div - 1;
1968
1969        pr_debug("FLL Fvco=%dHz\n", target);
1970
1971        /* Find an appropraite FLL_FRATIO and factor it out of the target */
1972        for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1973                if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1974                        fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1975                        fratio = fll_fratios[i].ratio;
1976                        break;
1977                }
1978        }
1979        if (i == ARRAY_SIZE(fll_fratios)) {
1980                pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1981                return -EINVAL;
1982        }
1983
1984        fll_div->n = target / (fratio * Fref);
1985
1986        if (target % Fref == 0) {
1987                fll_div->theta = 0;
1988                fll_div->lambda = 0;
1989        } else {
1990                gcd_fll = gcd(target, fratio * Fref);
1991
1992                fll_div->theta = (target - (fll_div->n * fratio * Fref))
1993                        / gcd_fll;
1994                fll_div->lambda = (fratio * Fref) / gcd_fll;
1995        }
1996
1997        pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1998                 fll_div->n, fll_div->theta, fll_div->lambda);
1999        pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2000                 fll_div->fll_fratio, fll_div->fll_outdiv,
2001                 fll_div->fll_refclk_div);
2002
2003        return 0;
2004}
2005
2006static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2007                          unsigned int Fref, unsigned int Fout)
2008{
2009        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2010        struct i2c_client *i2c = to_i2c_client(codec->dev);
2011        struct _fll_div fll_div;
2012        unsigned long timeout;
2013        int ret, reg, retry;
2014
2015        /* Any change? */
2016        if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2017            Fout == wm8996->fll_fout)
2018                return 0;
2019
2020        if (Fout == 0) {
2021                dev_dbg(codec->dev, "FLL disabled\n");
2022
2023                wm8996->fll_fref = 0;
2024                wm8996->fll_fout = 0;
2025
2026                snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2027                                    WM8996_FLL_ENA, 0);
2028
2029                wm8996_bg_disable(codec);
2030
2031                return 0;
2032        }
2033
2034        ret = fll_factors(&fll_div, Fref, Fout);
2035        if (ret != 0)
2036                return ret;
2037
2038        switch (source) {
2039        case WM8996_FLL_MCLK1:
2040                reg = 0;
2041                break;
2042        case WM8996_FLL_MCLK2:
2043                reg = 1;
2044                break;
2045        case WM8996_FLL_DACLRCLK1:
2046                reg = 2;
2047                break;
2048        case WM8996_FLL_BCLK1:
2049                reg = 3;
2050                break;
2051        default:
2052                dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2053                return -EINVAL;
2054        }
2055
2056        reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2057        reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2058
2059        snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2060                            WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2061                            WM8996_FLL_REFCLK_SRC_MASK, reg);
2062
2063        reg = 0;
2064        if (fll_div.theta || fll_div.lambda)
2065                reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2066        else
2067                reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2068        snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2069
2070        snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2071                            WM8996_FLL_OUTDIV_MASK |
2072                            WM8996_FLL_FRATIO_MASK,
2073                            (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2074                            (fll_div.fll_fratio));
2075
2076        snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2077
2078        snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2079                            WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2080                            (fll_div.n << WM8996_FLL_N_SHIFT) |
2081                            fll_div.fll_loop_gain);
2082
2083        snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2084
2085        /* Enable the bandgap if it's not already enabled */
2086        ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2087        if (!(ret & WM8996_FLL_ENA))
2088                wm8996_bg_enable(codec);
2089
2090        /* Clear any pending completions (eg, from failed startups) */
2091        try_wait_for_completion(&wm8996->fll_lock);
2092
2093        snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2094                            WM8996_FLL_ENA, WM8996_FLL_ENA);
2095
2096        /* The FLL supports live reconfiguration - kick that in case we were
2097         * already enabled.
2098         */
2099        snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2100
2101        /* Wait for the FLL to lock, using the interrupt if possible */
2102        if (Fref > 1000000)
2103                timeout = usecs_to_jiffies(300);
2104        else
2105                timeout = msecs_to_jiffies(2);
2106
2107        /* Allow substantially longer if we've actually got the IRQ, poll
2108         * at a slightly higher rate if we don't.
2109         */
2110        if (i2c->irq)
2111                timeout *= 10;
2112        else
2113                timeout /= 2;
2114
2115        for (retry = 0; retry < 10; retry++) {
2116                ret = wait_for_completion_timeout(&wm8996->fll_lock,
2117                                                  timeout);
2118                if (ret != 0) {
2119                        WARN_ON(!i2c->irq);
2120                        break;
2121                }
2122
2123                ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2124                if (ret & WM8996_FLL_LOCK_STS)
2125                        break;
2126        }
2127        if (retry == 10) {
2128                dev_err(codec->dev, "Timed out waiting for FLL\n");
2129                ret = -ETIMEDOUT;
2130        }
2131
2132        dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2133
2134        wm8996->fll_fref = Fref;
2135        wm8996->fll_fout = Fout;
2136        wm8996->fll_src = source;
2137
2138        return ret;
2139}
2140
2141#ifdef CONFIG_GPIOLIB
2142static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2143{
2144        return container_of(chip, struct wm8996_priv, gpio_chip);
2145}
2146
2147static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2148{
2149        struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2150
2151        regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2152                           WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2153}
2154
2155static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2156                                     unsigned offset, int value)
2157{
2158        struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2159        int val;
2160
2161        val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2162
2163        return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2164                                  WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2165                                  WM8996_GP1_LVL, val);
2166}
2167
2168static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2169{
2170        struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2171        unsigned int reg;
2172        int ret;
2173
2174        ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
2175        if (ret < 0)
2176                return ret;
2177
2178        return (reg & WM8996_GP1_LVL) != 0;
2179}
2180
2181static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2182{
2183        struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2184
2185        return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2186                                  WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2187                                  (1 << WM8996_GP1_FN_SHIFT) |
2188                                  (1 << WM8996_GP1_DIR_SHIFT));
2189}
2190
2191static struct gpio_chip wm8996_template_chip = {
2192        .label                  = "wm8996",
2193        .owner                  = THIS_MODULE,
2194        .direction_output       = wm8996_gpio_direction_out,
2195        .set                    = wm8996_gpio_set,
2196        .direction_input        = wm8996_gpio_direction_in,
2197        .get                    = wm8996_gpio_get,
2198        .can_sleep              = 1,
2199};
2200
2201static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2202{
2203        int ret;
2204
2205        wm8996->gpio_chip = wm8996_template_chip;
2206        wm8996->gpio_chip.ngpio = 5;
2207        wm8996->gpio_chip.dev = wm8996->dev;
2208
2209        if (wm8996->pdata.gpio_base)
2210                wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2211        else
2212                wm8996->gpio_chip.base = -1;
2213
2214        ret = gpiochip_add(&wm8996->gpio_chip);
2215        if (ret != 0)
2216                dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2217}
2218
2219static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2220{
2221        gpiochip_remove(&wm8996->gpio_chip);
2222}
2223#else
2224static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2225{
2226}
2227
2228static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2229{
2230}
2231#endif
2232
2233/**
2234 * wm8996_detect - Enable default WM8996 jack detection
2235 *
2236 * The WM8996 has advanced accessory detection support for headsets.
2237 * This function provides a default implementation which integrates
2238 * the majority of this functionality with minimal user configuration.
2239 *
2240 * This will detect headset, headphone and short circuit button and
2241 * will also detect inverted microphone ground connections and update
2242 * the polarity of the connections.
2243 */
2244int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2245                  wm8996_polarity_fn polarity_cb)
2246{
2247        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2248        struct snd_soc_dapm_context *dapm = &codec->dapm;
2249
2250        wm8996->jack = jack;
2251        wm8996->detecting = true;
2252        wm8996->polarity_cb = polarity_cb;
2253        wm8996->jack_flips = 0;
2254
2255        if (wm8996->polarity_cb)
2256                wm8996->polarity_cb(codec, 0);
2257
2258        /* Clear discarge to avoid noise during detection */
2259        snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2260                            WM8996_MICB1_DISCH, 0);
2261        snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2262                            WM8996_MICB2_DISCH, 0);
2263
2264        /* LDO2 powers the microphones, SYSCLK clocks detection */
2265        snd_soc_dapm_mutex_lock(dapm);
2266
2267        snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2268        snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2269
2270        snd_soc_dapm_mutex_unlock(dapm);
2271
2272        /* We start off just enabling microphone detection - even a
2273         * plain headphone will trigger detection.
2274         */
2275        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2276                            WM8996_MICD_ENA, WM8996_MICD_ENA);
2277
2278        /* Slowest detection rate, gives debounce for initial detection */
2279        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2280                            WM8996_MICD_RATE_MASK,
2281                            WM8996_MICD_RATE_MASK);
2282
2283        /* Enable interrupts and we're off */
2284        snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2285                            WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2286
2287        return 0;
2288}
2289EXPORT_SYMBOL_GPL(wm8996_detect);
2290
2291static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2292{
2293        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2294        int val, reg, report;
2295
2296        /* Assume headphone in error conditions; we need to report
2297         * something or we stall our state machine.
2298         */
2299        report = SND_JACK_HEADPHONE;
2300
2301        reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2302        if (reg < 0) {
2303                dev_err(codec->dev, "Failed to read HPDET status\n");
2304                goto out;
2305        }
2306
2307        if (!(reg & WM8996_HP_DONE)) {
2308                dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2309                goto out;
2310        }
2311
2312        val = reg & WM8996_HP_LVL_MASK;
2313
2314        dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2315
2316        /* If we've got high enough impedence then report as line,
2317         * otherwise assume headphone.
2318         */
2319        if (val >= 126)
2320                report = SND_JACK_LINEOUT;
2321        else
2322                report = SND_JACK_HEADPHONE;
2323
2324out:
2325        if (wm8996->jack_mic)
2326                report |= SND_JACK_MICROPHONE;
2327
2328        snd_soc_jack_report(wm8996->jack, report,
2329                            SND_JACK_LINEOUT | SND_JACK_HEADSET);
2330
2331        wm8996->detecting = false;
2332
2333        /* If the output isn't running re-clamp it */
2334        if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2335              (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2336                snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2337                                    WM8996_HPOUT1L_RMV_SHORT |
2338                                    WM8996_HPOUT1R_RMV_SHORT, 0);
2339
2340        /* Go back to looking at the microphone */
2341        snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2342                            WM8996_JD_MODE_MASK, 0);
2343        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2344                            WM8996_MICD_ENA);
2345
2346        snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2347        snd_soc_dapm_sync(&codec->dapm);
2348}
2349
2350static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2351{
2352        /* Unclamp the output, we can't measure while we're shorting it */
2353        snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2354                            WM8996_HPOUT1L_RMV_SHORT |
2355                            WM8996_HPOUT1R_RMV_SHORT,
2356                            WM8996_HPOUT1L_RMV_SHORT |
2357                            WM8996_HPOUT1R_RMV_SHORT);
2358
2359        /* We need bandgap for HPDET */
2360        snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2361        snd_soc_dapm_sync(&codec->dapm);
2362
2363        /* Go into headphone detect left mode */
2364        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2365        snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2366                            WM8996_JD_MODE_MASK, 1);
2367
2368        /* Trigger a measurement */
2369        snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2370                            WM8996_HP_POLL, WM8996_HP_POLL);
2371}
2372
2373static void wm8996_report_headphone(struct snd_soc_codec *codec)
2374{
2375        dev_dbg(codec->dev, "Headphone detected\n");
2376        wm8996_hpdet_start(codec);
2377
2378        /* Increase the detection rate a bit for responsiveness. */
2379        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2380                            WM8996_MICD_RATE_MASK |
2381                            WM8996_MICD_BIAS_STARTTIME_MASK,
2382                            7 << WM8996_MICD_RATE_SHIFT |
2383                            7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2384}
2385
2386static void wm8996_micd(struct snd_soc_codec *codec)
2387{
2388        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2389        int val, reg;
2390
2391        val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2392
2393        dev_dbg(codec->dev, "Microphone event: %x\n", val);
2394
2395        if (!(val & WM8996_MICD_VALID)) {
2396                dev_warn(codec->dev, "Microphone detection state invalid\n");
2397                return;
2398        }
2399
2400        /* No accessory, reset everything and report removal */
2401        if (!(val & WM8996_MICD_STS)) {
2402                dev_dbg(codec->dev, "Jack removal detected\n");
2403                wm8996->jack_mic = false;
2404                wm8996->detecting = true;
2405                wm8996->jack_flips = 0;
2406                snd_soc_jack_report(wm8996->jack, 0,
2407                                    SND_JACK_LINEOUT | SND_JACK_HEADSET |
2408                                    SND_JACK_BTN_0);
2409
2410                snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2411                                    WM8996_MICD_RATE_MASK |
2412                                    WM8996_MICD_BIAS_STARTTIME_MASK,
2413                                    WM8996_MICD_RATE_MASK |
2414                                    9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2415                return;
2416        }
2417
2418        /* If the measurement is very high we've got a microphone,
2419         * either we just detected one or if we already reported then
2420         * we've got a button release event.
2421         */
2422        if (val & 0x400) {
2423                if (wm8996->detecting) {
2424                        dev_dbg(codec->dev, "Microphone detected\n");
2425                        wm8996->jack_mic = true;
2426                        wm8996_hpdet_start(codec);
2427
2428                        /* Increase poll rate to give better responsiveness
2429                         * for buttons */
2430                        snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2431                                            WM8996_MICD_RATE_MASK |
2432                                            WM8996_MICD_BIAS_STARTTIME_MASK,
2433                                            5 << WM8996_MICD_RATE_SHIFT |
2434                                            7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2435                } else {
2436                        dev_dbg(codec->dev, "Mic button up\n");
2437                        snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2438                }
2439
2440                return;
2441        }
2442
2443        /* If we detected a lower impedence during initial startup
2444         * then we probably have the wrong polarity, flip it.  Don't
2445         * do this for the lowest impedences to speed up detection of
2446         * plain headphones.  If both polarities report a low
2447         * impedence then give up and report headphones.
2448         */
2449        if (wm8996->detecting && (val & 0x3f0)) {
2450                wm8996->jack_flips++;
2451
2452                if (wm8996->jack_flips > 1) {
2453                        wm8996_report_headphone(codec);
2454                        return;
2455                }
2456
2457                reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2458                reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2459                        WM8996_MICD_BIAS_SRC;
2460                snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2461                                    WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2462                                    WM8996_MICD_BIAS_SRC, reg);
2463
2464                if (wm8996->polarity_cb)
2465                        wm8996->polarity_cb(codec,
2466                                            (reg & WM8996_MICD_SRC) != 0);
2467
2468                dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2469                        (reg & WM8996_MICD_SRC) != 0);
2470
2471                return;
2472        }
2473
2474        /* Don't distinguish between buttons, just report any low
2475         * impedence as BTN_0.
2476         */
2477        if (val & 0x3fc) {
2478                if (wm8996->jack_mic) {
2479                        dev_dbg(codec->dev, "Mic button detected\n");
2480                        snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2481                                            SND_JACK_BTN_0);
2482                } else if (wm8996->detecting) {
2483                        wm8996_report_headphone(codec);
2484                }
2485        }
2486}
2487
2488static irqreturn_t wm8996_irq(int irq, void *data)
2489{
2490        struct snd_soc_codec *codec = data;
2491        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2492        int irq_val;
2493
2494        irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2495        if (irq_val < 0) {
2496                dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2497                        irq_val);
2498                return IRQ_NONE;
2499        }
2500        irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2501
2502        if (!irq_val)
2503                return IRQ_NONE;
2504
2505        snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2506
2507        if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2508                dev_dbg(codec->dev, "DC servo IRQ\n");
2509                complete(&wm8996->dcs_done);
2510        }
2511
2512        if (irq_val & WM8996_FIFOS_ERR_EINT)
2513                dev_err(codec->dev, "Digital core FIFO error\n");
2514
2515        if (irq_val & WM8996_FLL_LOCK_EINT) {
2516                dev_dbg(codec->dev, "FLL locked\n");
2517                complete(&wm8996->fll_lock);
2518        }
2519
2520        if (irq_val & WM8996_MICD_EINT)
2521                wm8996_micd(codec);
2522
2523        if (irq_val & WM8996_HP_DONE_EINT)
2524                wm8996_hpdet_irq(codec);
2525
2526        return IRQ_HANDLED;
2527}
2528
2529static irqreturn_t wm8996_edge_irq(int irq, void *data)
2530{
2531        irqreturn_t ret = IRQ_NONE;
2532        irqreturn_t val;
2533
2534        do {
2535                val = wm8996_irq(irq, data);
2536                if (val != IRQ_NONE)
2537                        ret = val;
2538        } while (val != IRQ_NONE);
2539
2540        return ret;
2541}
2542
2543static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2544{
2545        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2546        struct wm8996_pdata *pdata = &wm8996->pdata;
2547
2548        struct snd_kcontrol_new controls[] = {
2549                SOC_ENUM_EXT("DSP1 EQ Mode",
2550                             wm8996->retune_mobile_enum,
2551                             wm8996_get_retune_mobile_enum,
2552                             wm8996_put_retune_mobile_enum),
2553                SOC_ENUM_EXT("DSP2 EQ Mode",
2554                             wm8996->retune_mobile_enum,
2555                             wm8996_get_retune_mobile_enum,
2556                             wm8996_put_retune_mobile_enum),
2557        };
2558        int ret, i, j;
2559        const char **t;
2560
2561        /* We need an array of texts for the enum API but the number
2562         * of texts is likely to be less than the number of
2563         * configurations due to the sample rate dependency of the
2564         * configurations. */
2565        wm8996->num_retune_mobile_texts = 0;
2566        wm8996->retune_mobile_texts = NULL;
2567        for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2568                for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2569                        if (strcmp(pdata->retune_mobile_cfgs[i].name,
2570                                   wm8996->retune_mobile_texts[j]) == 0)
2571                                break;
2572                }
2573
2574                if (j != wm8996->num_retune_mobile_texts)
2575                        continue;
2576
2577                /* Expand the array... */
2578                t = krealloc(wm8996->retune_mobile_texts,
2579                             sizeof(char *) * 
2580                             (wm8996->num_retune_mobile_texts + 1),
2581                             GFP_KERNEL);
2582                if (t == NULL)
2583                        continue;
2584
2585                /* ...store the new entry... */
2586                t[wm8996->num_retune_mobile_texts] = 
2587                        pdata->retune_mobile_cfgs[i].name;
2588
2589                /* ...and remember the new version. */
2590                wm8996->num_retune_mobile_texts++;
2591                wm8996->retune_mobile_texts = t;
2592        }
2593
2594        dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2595                wm8996->num_retune_mobile_texts);
2596
2597        wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
2598        wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2599
2600        ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
2601        if (ret != 0)
2602                dev_err(codec->dev,
2603                        "Failed to add ReTune Mobile controls: %d\n", ret);
2604}
2605
2606static const struct regmap_config wm8996_regmap = {
2607        .reg_bits = 16,
2608        .val_bits = 16,
2609
2610        .max_register = WM8996_MAX_REGISTER,
2611        .reg_defaults = wm8996_reg,
2612        .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2613        .volatile_reg = wm8996_volatile_register,
2614        .readable_reg = wm8996_readable_register,
2615        .cache_type = REGCACHE_RBTREE,
2616};
2617
2618static int wm8996_probe(struct snd_soc_codec *codec)
2619{
2620        int ret;
2621        struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2622        struct i2c_client *i2c = to_i2c_client(codec->dev);
2623        int irq_flags;
2624
2625        wm8996->codec = codec;
2626
2627        init_completion(&wm8996->dcs_done);
2628        init_completion(&wm8996->fll_lock);
2629
2630        if (wm8996->pdata.num_retune_mobile_cfgs)
2631                wm8996_retune_mobile_pdata(codec);
2632        else
2633                snd_soc_add_codec_controls(codec, wm8996_eq_controls,
2634                                     ARRAY_SIZE(wm8996_eq_controls));
2635
2636        if (i2c->irq) {
2637                if (wm8996->pdata.irq_flags)
2638                        irq_flags = wm8996->pdata.irq_flags;
2639                else
2640                        irq_flags = IRQF_TRIGGER_LOW;
2641
2642                irq_flags |= IRQF_ONESHOT;
2643
2644                if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2645                        ret = request_threaded_irq(i2c->irq, NULL,
2646                                                   wm8996_edge_irq,
2647                                                   irq_flags, "wm8996", codec);
2648                else
2649                        ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2650                                                   irq_flags, "wm8996", codec);
2651
2652                if (ret == 0) {
2653                        /* Unmask the interrupt */
2654                        snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2655                                            WM8996_IM_IRQ, 0);
2656
2657                        /* Enable error reporting and DC servo status */
2658                        snd_soc_update_bits(codec,
2659                                            WM8996_INTERRUPT_STATUS_2_MASK,
2660                                            WM8996_IM_DCS_DONE_23_EINT |
2661                                            WM8996_IM_DCS_DONE_01_EINT |
2662                                            WM8996_IM_FLL_LOCK_EINT |
2663                                            WM8996_IM_FIFOS_ERR_EINT,
2664                                            0);
2665                } else {
2666                        dev_err(codec->dev, "Failed to request IRQ: %d\n",
2667                                ret);
2668                        return ret;
2669                }
2670        }
2671
2672        return 0;
2673}
2674
2675static int wm8996_remove(struct snd_soc_codec *codec)
2676{
2677        struct i2c_client *i2c = to_i2c_client(codec->dev);
2678
2679        snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2680                            WM8996_IM_IRQ, WM8996_IM_IRQ);
2681
2682        if (i2c->irq)
2683                free_irq(i2c->irq, codec);
2684
2685        return 0;
2686}
2687
2688static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2689        .probe =        wm8996_probe,
2690        .remove =       wm8996_remove,
2691        .set_bias_level = wm8996_set_bias_level,
2692        .idle_bias_off  = true,
2693        .seq_notifier = wm8996_seq_notifier,
2694        .controls = wm8996_snd_controls,
2695        .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2696        .dapm_widgets = wm8996_dapm_widgets,
2697        .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2698        .dapm_routes = wm8996_dapm_routes,
2699        .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2700        .set_pll = wm8996_set_fll,
2701};
2702
2703#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2704                      SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
2705                      SNDRV_PCM_RATE_48000)
2706#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2707                        SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2708                        SNDRV_PCM_FMTBIT_S32_LE)
2709
2710static const struct snd_soc_dai_ops wm8996_dai_ops = {
2711        .set_fmt = wm8996_set_fmt,
2712        .hw_params = wm8996_hw_params,
2713        .set_sysclk = wm8996_set_sysclk,
2714};
2715
2716static struct snd_soc_dai_driver wm8996_dai[] = {
2717        {
2718                .name = "wm8996-aif1",
2719                .playback = {
2720                        .stream_name = "AIF1 Playback",
2721                        .channels_min = 1,
2722                        .channels_max = 6,
2723                        .rates = WM8996_RATES,
2724                        .formats = WM8996_FORMATS,
2725                        .sig_bits = 24,
2726                },
2727                .capture = {
2728                         .stream_name = "AIF1 Capture",
2729                         .channels_min = 1,
2730                         .channels_max = 6,
2731                         .rates = WM8996_RATES,
2732                         .formats = WM8996_FORMATS,
2733                         .sig_bits = 24,
2734                 },
2735                .ops = &wm8996_dai_ops,
2736        },
2737        {
2738                .name = "wm8996-aif2",
2739                .playback = {
2740                        .stream_name = "AIF2 Playback",
2741                        .channels_min = 1,
2742                        .channels_max = 2,
2743                        .rates = WM8996_RATES,
2744                        .formats = WM8996_FORMATS,
2745                        .sig_bits = 24,
2746                },
2747                .capture = {
2748                         .stream_name = "AIF2 Capture",
2749                         .channels_min = 1,
2750                         .channels_max = 2,
2751                         .rates = WM8996_RATES,
2752                         .formats = WM8996_FORMATS,
2753                        .sig_bits = 24,
2754                 },
2755                .ops = &wm8996_dai_ops,
2756        },
2757};
2758
2759static int wm8996_i2c_probe(struct i2c_client *i2c,
2760                            const struct i2c_device_id *id)
2761{
2762        struct wm8996_priv *wm8996;
2763        int ret, i;
2764        unsigned int reg;
2765
2766        wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
2767                              GFP_KERNEL);
2768        if (wm8996 == NULL)
2769                return -ENOMEM;
2770
2771        i2c_set_clientdata(i2c, wm8996);
2772        wm8996->dev = &i2c->dev;
2773
2774        if (dev_get_platdata(&i2c->dev))
2775                memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2776                       sizeof(wm8996->pdata));
2777
2778        if (wm8996->pdata.ldo_ena > 0) {
2779                ret = gpio_request_one(wm8996->pdata.ldo_ena,
2780                                       GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2781                if (ret < 0) {
2782                        dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2783                                wm8996->pdata.ldo_ena, ret);
2784                        goto err;
2785                }
2786        }
2787
2788        for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2789                wm8996->supplies[i].supply = wm8996_supply_names[i];
2790
2791        ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
2792                                      wm8996->supplies);
2793        if (ret != 0) {
2794                dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2795                goto err_gpio;
2796        }
2797
2798        wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2799        wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2800        wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2801
2802        /* This should really be moved into the regulator core */
2803        for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2804                ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2805                                                  &wm8996->disable_nb[i]);
2806                if (ret != 0) {
2807                        dev_err(&i2c->dev,
2808                                "Failed to register regulator notifier: %d\n",
2809                                ret);
2810                }
2811        }
2812
2813        ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2814                                    wm8996->supplies);
2815        if (ret != 0) {
2816                dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2817                goto err_gpio;
2818        }
2819
2820        if (wm8996->pdata.ldo_ena > 0) {
2821                gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2822                msleep(5);
2823        }
2824
2825        wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
2826        if (IS_ERR(wm8996->regmap)) {
2827                ret = PTR_ERR(wm8996->regmap);
2828                dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
2829                goto err_enable;
2830        }
2831
2832        ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
2833        if (ret < 0) {
2834                dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2835                goto err_regmap;
2836        }
2837        if (reg != 0x8915) {
2838                dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
2839                ret = -EINVAL;
2840                goto err_regmap;
2841        }
2842
2843        ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
2844        if (ret < 0) {
2845                dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2846                        ret);
2847                goto err_regmap;
2848        }
2849
2850        dev_info(&i2c->dev, "revision %c\n",
2851                 (reg & WM8996_CHIP_REV_MASK) + 'A');
2852
2853        if (wm8996->pdata.ldo_ena > 0) {
2854                gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2855                regcache_cache_only(wm8996->regmap, true);
2856        } else {
2857                ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
2858                                   0x8915);
2859                if (ret != 0) {
2860                        dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2861                        goto err_regmap;
2862                }
2863        }
2864
2865        regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2866
2867        /* Apply platform data settings */
2868        regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2869                           WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2870                           wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2871                           wm8996->pdata.inr_mode);
2872
2873        for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2874                if (!wm8996->pdata.gpio_default[i])
2875                        continue;
2876
2877                regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2878                             wm8996->pdata.gpio_default[i] & 0xffff);
2879        }
2880
2881        if (wm8996->pdata.spkmute_seq)
2882                regmap_update_bits(wm8996->regmap,
2883                                   WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2884                                   WM8996_SPK_MUTE_ENDIAN |
2885                                   WM8996_SPK_MUTE_SEQ1_MASK,
2886                                   wm8996->pdata.spkmute_seq);
2887
2888        regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2889                           WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2890                           WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2891
2892        /* Latch volume update bits */
2893        regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2894                           WM8996_IN1_VU, WM8996_IN1_VU);
2895        regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2896                           WM8996_IN1_VU, WM8996_IN1_VU);
2897
2898        regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2899                           WM8996_DAC1_VU, WM8996_DAC1_VU);
2900        regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2901                           WM8996_DAC1_VU, WM8996_DAC1_VU);
2902        regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2903                           WM8996_DAC2_VU, WM8996_DAC2_VU);
2904        regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2905                           WM8996_DAC2_VU, WM8996_DAC2_VU);
2906
2907        regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2908                           WM8996_DAC1_VU, WM8996_DAC1_VU);
2909        regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2910                           WM8996_DAC1_VU, WM8996_DAC1_VU);
2911        regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2912                           WM8996_DAC2_VU, WM8996_DAC2_VU);
2913        regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2914                           WM8996_DAC2_VU, WM8996_DAC2_VU);
2915
2916        regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2917                           WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2918        regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2919                           WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2920        regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2921                           WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2922        regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2923                           WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2924
2925        regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2926                           WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2927        regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2928                           WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2929        regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2930                           WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2931        regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2932                           WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2933
2934        /* No support currently for the underclocked TDM modes and
2935         * pick a default TDM layout with each channel pair working with
2936         * slots 0 and 1. */
2937        regmap_update_bits(wm8996->regmap,
2938                           WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2939                           WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2940                           WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2941                           1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2942        regmap_update_bits(wm8996->regmap,
2943                           WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2944                           WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2945                           WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2946                           1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2947        regmap_update_bits(wm8996->regmap,
2948                           WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2949                           WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2950                           WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2951                           1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2952        regmap_update_bits(wm8996->regmap,
2953                           WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2954                           WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2955                           WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2956                           1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2957        regmap_update_bits(wm8996->regmap,
2958                           WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2959                           WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2960                           WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2961                           1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2962        regmap_update_bits(wm8996->regmap,
2963                           WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2964                           WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2965                           WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2966                           1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2967
2968        regmap_update_bits(wm8996->regmap,
2969                           WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2970                           WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2971                           WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2972                           1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2973        regmap_update_bits(wm8996->regmap,
2974                           WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2975                           WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2976                           WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2977                           1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2978
2979        regmap_update_bits(wm8996->regmap,
2980                           WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2981                           WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2982                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2983                           1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2984        regmap_update_bits(wm8996->regmap,
2985                           WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2986                           WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2987                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2988                           1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2989        regmap_update_bits(wm8996->regmap,
2990                           WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2991                           WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2992                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2993                           1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2994        regmap_update_bits(wm8996->regmap,
2995                           WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2996                           WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2997                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2998                           1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2999        regmap_update_bits(wm8996->regmap,
3000                           WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
3001                           WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3002                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3003                           1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3004        regmap_update_bits(wm8996->regmap,
3005                           WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3006                           WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3007                           WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3008                           1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3009
3010        regmap_update_bits(wm8996->regmap,
3011                           WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3012                           WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3013                           WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3014                           1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3015        regmap_update_bits(wm8996->regmap,
3016                           WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3017                           WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3018                           WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3019                           1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3020
3021        /* If the TX LRCLK pins are not in LRCLK mode configure the
3022         * AIFs to source their clocks from the RX LRCLKs.
3023         */
3024        ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
3025        if (ret != 0) {
3026                dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3027                goto err_regmap;
3028        }
3029
3030        if (reg & WM8996_GP1_FN_MASK)
3031                regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3032                                   WM8996_AIF1TX_LRCLK_MODE,
3033                                   WM8996_AIF1TX_LRCLK_MODE);
3034
3035        ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
3036        if (ret != 0) {
3037                dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3038                goto err_regmap;
3039        }
3040
3041        if (reg & WM8996_GP2_FN_MASK)
3042                regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3043                                   WM8996_AIF2TX_LRCLK_MODE,
3044                                   WM8996_AIF2TX_LRCLK_MODE);
3045
3046        wm8996_init_gpio(wm8996);
3047
3048        ret = snd_soc_register_codec(&i2c->dev,
3049                                     &soc_codec_dev_wm8996, wm8996_dai,
3050                                     ARRAY_SIZE(wm8996_dai));
3051        if (ret < 0)
3052                goto err_gpiolib;
3053
3054        return ret;
3055
3056err_gpiolib:
3057        wm8996_free_gpio(wm8996);
3058err_regmap:
3059err_enable:
3060        if (wm8996->pdata.ldo_ena > 0)
3061                gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3062        regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3063err_gpio:
3064        if (wm8996->pdata.ldo_ena > 0)
3065                gpio_free(wm8996->pdata.ldo_ena);
3066err:
3067
3068        return ret;
3069}
3070
3071static int wm8996_i2c_remove(struct i2c_client *client)
3072{
3073        struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3074        int i;
3075
3076        snd_soc_unregister_codec(&client->dev);
3077        wm8996_free_gpio(wm8996);
3078        if (wm8996->pdata.ldo_ena > 0) {
3079                gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3080                gpio_free(wm8996->pdata.ldo_ena);
3081        }
3082        for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3083                regulator_unregister_notifier(wm8996->supplies[i].consumer,
3084                                              &wm8996->disable_nb[i]);
3085
3086        return 0;
3087}
3088
3089static const struct i2c_device_id wm8996_i2c_id[] = {
3090        { "wm8996", 0 },
3091        { }
3092};
3093MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3094
3095static struct i2c_driver wm8996_i2c_driver = {
3096        .driver = {
3097                .name = "wm8996",
3098                .owner = THIS_MODULE,
3099        },
3100        .probe =    wm8996_i2c_probe,
3101        .remove =   wm8996_i2c_remove,
3102        .id_table = wm8996_i2c_id,
3103};
3104
3105module_i2c_driver(wm8996_i2c_driver);
3106
3107MODULE_DESCRIPTION("ASoC WM8996 driver");
3108MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3109MODULE_LICENSE("GPL");
3110