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15#ifndef __IOP3XX_H
16#define __IOP3XX_H
17
18
19
20
21#define IOP3XX_GPIO_LINE(x) (x)
22
23#ifndef __ASSEMBLY__
24extern int init_atu;
25extern int iop3xx_get_init_atu(void);
26#endif
27
28
29
30
31
32#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
33#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
34#define IOP3XX_PERIPHERAL_SIZE 0x00002000
35#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
36 IOP3XX_PERIPHERAL_SIZE - 1)
37#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
38 IOP3XX_PERIPHERAL_SIZE - 1)
39#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
40 (IOP3XX_PERIPHERAL_PHYS_BASE\
41 - IOP3XX_PERIPHERAL_VIRT_BASE))
42#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
43
44
45#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
46#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
47#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
48#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
49#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
50#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
51#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
52#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
53#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
54#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
55#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
56#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
57#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
58#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
59#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
60#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
61#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
62#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
63#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
64#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
65#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
66#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
67#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
68#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
69#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
70#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
71#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
72#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
73#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
74#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
75#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
76#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
77#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
78#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
79#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
80#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
81#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
82#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
83#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
84#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
85#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
86#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
87#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
88#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
89#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
90#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
91#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
92#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
93#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
94#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
95#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
96#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
97#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
98#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
99#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
100#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
101#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
102#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
103#define IOP3XX_ATUCR_OUT_EN (1 << 1)
104
105#define IOP3XX_INIT_ATU_DEFAULT 0
106#define IOP3XX_INIT_ATU_DISABLE -1
107#define IOP3XX_INIT_ATU_ENABLE 1
108
109
110#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
111#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
112#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
113#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
114#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
115#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
116#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
117#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
118#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
119#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
120#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
121#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
122#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
123#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
124#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
125#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
126#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
127#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
128#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
129#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
130#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
131
132
133#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
134 (0x400 + (chan << 6)))
135#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
136
137
138#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
139#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
140#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
141#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
142#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
143#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
144#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
145#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
146#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
147#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
148#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
149#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
150#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
151#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
152#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
153#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
154#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
155
156
157#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
158#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
159#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
160#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
161
162#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
163
164
165#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
166#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
167#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
168#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
169#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
170#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
171#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
172#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
173#define IOP_TMR_EN 0x02
174#define IOP_TMR_RELOAD 0x04
175#define IOP_TMR_PRIVILEGED 0x08
176#define IOP_TMR_RATIO_1_1 0x00
177
178
179#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
180#define IOP_WDTCR_EN 0xe1e1e1e1
181
182#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
183#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
184
185
186#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
187#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
188
189
190#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
191#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
192#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
193#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
194#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
195#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
196#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
197#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
198#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
199#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
200
201
202
203
204
205#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
206#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
207
208#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
209#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
210
211#ifndef __ASSEMBLY__
212
213#include <linux/types.h>
214#include <linux/reboot.h>
215
216void iop3xx_map_io(void);
217void iop_init_cp6_handler(void);
218void iop_init_time(unsigned long tickrate);
219void iop3xx_restart(enum reboot_mode, const char *);
220
221static inline u32 read_tmr0(void)
222{
223 u32 val;
224 asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
225 return val;
226}
227
228static inline void write_tmr0(u32 val)
229{
230 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
231}
232
233static inline void write_tmr1(u32 val)
234{
235 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
236}
237
238static inline u32 read_tcr0(void)
239{
240 u32 val;
241 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
242 return val;
243}
244
245static inline void write_tcr0(u32 val)
246{
247 asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
248}
249
250static inline u32 read_tcr1(void)
251{
252 u32 val;
253 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
254 return val;
255}
256
257static inline void write_tcr1(u32 val)
258{
259 asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
260}
261
262static inline void write_trr0(u32 val)
263{
264 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
265}
266
267static inline void write_trr1(u32 val)
268{
269 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
270}
271
272static inline void write_tisr(u32 val)
273{
274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
275}
276
277static inline u32 read_wdtcr(void)
278{
279 u32 val;
280 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
281 return val;
282}
283static inline void write_wdtcr(u32 val)
284{
285 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
286}
287
288extern unsigned long get_iop_tick_rate(void);
289
290
291
292
293#define IOP_RCSR_WDT (0)
294static inline u32 read_rcsr(void)
295{
296 return 0;
297}
298static inline void write_wdtsr(u32 val)
299{
300 do { } while (0);
301}
302
303extern struct platform_device iop3xx_dma_0_channel;
304extern struct platform_device iop3xx_dma_1_channel;
305extern struct platform_device iop3xx_aau_channel;
306extern struct platform_device iop3xx_i2c0_device;
307extern struct platform_device iop3xx_i2c1_device;
308
309#endif
310
311
312#endif
313