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23#include <linux/kernel.h>
24#include <linux/pci.h>
25#include <linux/ioport.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/init.h>
29#include <linux/io.h>
30#include <linux/platform_device.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <video/vga.h>
36
37#include <asm/mach/map.h>
38#include <asm/signal.h>
39#include <asm/mach/pci.h>
40#include <asm/irq_regs.h>
41
42#include "pci_v3.h"
43#include "hardware.h"
44
45
46
47
48
49
50
51
52#define PHYS_PCI_MEM_BASE 0x40000000
53#define PHYS_PCI_PRE_BASE 0x50000000
54#define PHYS_PCI_IO_BASE 0x60000000
55#define PHYS_PCI_CONFIG_BASE 0x61000000
56#define PHYS_PCI_V3_BASE 0x62000000
57
58#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
59#define PCI_CONFIG_VADDR IOMEM(0xec000000)
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69
70
71#define V3_PCI_VENDOR 0x00000000
72#define V3_PCI_DEVICE 0x00000002
73#define V3_PCI_CMD 0x00000004
74#define V3_PCI_STAT 0x00000006
75#define V3_PCI_CC_REV 0x00000008
76#define V3_PCI_HDR_CFG 0x0000000C
77#define V3_PCI_IO_BASE 0x00000010
78#define V3_PCI_BASE0 0x00000014
79#define V3_PCI_BASE1 0x00000018
80#define V3_PCI_SUB_VENDOR 0x0000002C
81#define V3_PCI_SUB_ID 0x0000002E
82#define V3_PCI_ROM 0x00000030
83#define V3_PCI_BPARAM 0x0000003C
84#define V3_PCI_MAP0 0x00000040
85#define V3_PCI_MAP1 0x00000044
86#define V3_PCI_INT_STAT 0x00000048
87#define V3_PCI_INT_CFG 0x0000004C
88#define V3_LB_BASE0 0x00000054
89#define V3_LB_BASE1 0x00000058
90#define V3_LB_MAP0 0x0000005E
91#define V3_LB_MAP1 0x00000062
92#define V3_LB_BASE2 0x00000064
93#define V3_LB_MAP2 0x00000066
94#define V3_LB_SIZE 0x00000068
95#define V3_LB_IO_BASE 0x0000006E
96#define V3_FIFO_CFG 0x00000070
97#define V3_FIFO_PRIORITY 0x00000072
98#define V3_FIFO_STAT 0x00000074
99#define V3_LB_ISTAT 0x00000076
100#define V3_LB_IMASK 0x00000077
101#define V3_SYSTEM 0x00000078
102#define V3_LB_CFG 0x0000007A
103#define V3_PCI_CFG 0x0000007C
104#define V3_DMA_PCI_ADR0 0x00000080
105#define V3_DMA_PCI_ADR1 0x00000090
106#define V3_DMA_LOCAL_ADR0 0x00000084
107#define V3_DMA_LOCAL_ADR1 0x00000094
108#define V3_DMA_LENGTH0 0x00000088
109#define V3_DMA_LENGTH1 0x00000098
110#define V3_DMA_CSR0 0x0000008B
111#define V3_DMA_CSR1 0x0000009B
112#define V3_DMA_CTLB_ADR0 0x0000008C
113#define V3_DMA_CTLB_ADR1 0x0000009C
114#define V3_DMA_DELAY 0x000000E0
115#define V3_MAIL_DATA 0x000000C0
116#define V3_PCI_MAIL_IEWR 0x000000D0
117#define V3_PCI_MAIL_IERD 0x000000D2
118#define V3_LB_MAIL_IEWR 0x000000D4
119#define V3_LB_MAIL_IERD 0x000000D6
120#define V3_MAIL_WR_STAT 0x000000D8
121#define V3_MAIL_RD_STAT 0x000000DA
122#define V3_QBA_MAP 0x000000DC
123
124
125
126#define V3_COMMAND_M_FBB_EN (1 << 9)
127#define V3_COMMAND_M_SERR_EN (1 << 8)
128#define V3_COMMAND_M_PAR_EN (1 << 6)
129#define V3_COMMAND_M_MASTER_EN (1 << 2)
130#define V3_COMMAND_M_MEM_EN (1 << 1)
131#define V3_COMMAND_M_IO_EN (1 << 0)
132
133
134
135#define V3_SYSTEM_M_RST_OUT (1 << 15)
136#define V3_SYSTEM_M_LOCK (1 << 14)
137
138
139
140#define V3_PCI_CFG_M_I2O_EN (1 << 15)
141#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
142#define V3_PCI_CFG_M_IO_DIS (1 << 13)
143#define V3_PCI_CFG_M_EN3V (1 << 12)
144#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
145#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
146#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
147
148
149
150#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
151#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
152#define V3_PCI_BASE_M_PREFETCH (1 << 3)
153#define V3_PCI_BASE_M_TYPE (3 << 1)
154#define V3_PCI_BASE_M_IO (1 << 0)
155
156
157
158#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
159#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
160#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
161#define V3_PCI_MAP_M_SWAP (3 << 8)
162#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
163#define V3_PCI_MAP_M_REG_EN (1 << 1)
164#define V3_PCI_MAP_M_ENABLE (1 << 0)
165
166
167
168
169#define V3_LB_BASE_ADR_BASE 0xfff00000
170#define V3_LB_BASE_SWAP (3 << 8)
171#define V3_LB_BASE_ADR_SIZE (15 << 4)
172#define V3_LB_BASE_PREFETCH (1 << 3)
173#define V3_LB_BASE_ENABLE (1 << 0)
174
175#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
176#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
177#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
178#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
179#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
180#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
181#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
182#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
183#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
184#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
185#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
186#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
187
188#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
189
190
191
192
193#define V3_LB_MAP_MAP_ADR 0xfff0
194#define V3_LB_MAP_TYPE (7 << 1)
195#define V3_LB_MAP_AD_LOW_EN (1 << 0)
196
197#define V3_LB_MAP_TYPE_IACK (0 << 1)
198#define V3_LB_MAP_TYPE_IO (1 << 1)
199#define V3_LB_MAP_TYPE_MEM (3 << 1)
200#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
201#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
202
203#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
204
205
206
207
208#define V3_LB_BASE2_ADR_BASE 0xff00
209#define V3_LB_BASE2_SWAP (3 << 6)
210#define V3_LB_BASE2_ENABLE (1 << 0)
211
212#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
213
214
215
216
217#define V3_LB_MAP2_MAP_ADR 0xff00
218
219#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
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285static void __iomem *pci_v3_base;
286
287static struct resource conf_mem;
288static struct resource io_mem;
289static struct resource non_mem;
290static struct resource pre_mem;
291
292static u64 non_mem_pci;
293static u64 non_mem_pci_sz;
294static u64 pre_mem_pci;
295static u64 pre_mem_pci_sz;
296
297
298#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
299#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
300
301#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
302#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
303
304#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
305#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
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360#undef V3_LB_BASE_PREFETCH
361#define V3_LB_BASE_PREFETCH 0
362
363static void __iomem *v3_open_config_window(struct pci_bus *bus,
364 unsigned int devfn, int offset)
365{
366 unsigned int address, mapaddress, busnr;
367
368 busnr = bus->number;
369
370
371
372
373 BUG_ON(offset > 255);
374 BUG_ON(busnr > 255);
375 BUG_ON(devfn > 255);
376
377 if (busnr == 0) {
378 int slot = PCI_SLOT(devfn);
379
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390 address = PCI_FUNC(devfn) << 8;
391 mapaddress = V3_LB_MAP_TYPE_CONFIG;
392
393 if (slot > 12)
394
395
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397 mapaddress |= 1 << (slot - 5);
398 else
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402 address |= 1 << (slot + 11);
403 } else {
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416 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
417 address = (busnr << 16) | (devfn << 8);
418 }
419
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421
422
423
424
425 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
426 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
427
428
429
430
431 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
432 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
433 v3_writew(V3_LB_MAP1, mapaddress);
434
435 return PCI_CONFIG_VADDR + address + offset;
436}
437
438static void v3_close_config_window(void)
439{
440
441
442
443 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
444 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
445 V3_LB_BASE_ENABLE);
446 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
447 V3_LB_MAP_TYPE_MEM_MULTIPLE);
448
449
450
451
452 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
453 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
454}
455
456static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
457 int size, u32 *val)
458{
459 int ret = pci_generic_config_read(bus, devfn, where, size, val);
460 v3_close_config_window();
461 return ret;
462}
463
464static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
465 int size, u32 val)
466{
467 int ret = pci_generic_config_write(bus, devfn, where, size, val);
468 v3_close_config_window();
469 return ret;
470}
471
472static struct pci_ops pci_v3_ops = {
473 .map_bus = v3_open_config_window,
474 .read = v3_read_config,
475 .write = v3_write_config,
476};
477
478static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
479{
480 if (request_resource(&iomem_resource, &non_mem)) {
481 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
482 "memory region\n");
483 return -EBUSY;
484 }
485 if (request_resource(&iomem_resource, &pre_mem)) {
486 release_resource(&non_mem);
487 printk(KERN_ERR "PCI: unable to allocate prefetchable "
488 "memory region\n");
489 return -EBUSY;
490 }
491
492
493
494
495
496 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
497 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
498
499 return 1;
500}
501
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506
507static void __iomem *ap_syscon_base;
508#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
509#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
510#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
511
512static int
513v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
514{
515 unsigned long pc = instruction_pointer(regs);
516 unsigned long instr = *(unsigned long *)pc;
517#if 0
518 char buf[128];
519
520 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
521 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
522 v3_readb(V3_LB_ISTAT));
523 printk(KERN_DEBUG "%s", buf);
524#endif
525
526 v3_writeb(V3_LB_ISTAT, 0);
527 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
528
529
530
531
532
533 if ((instr & 0x0c100000) == 0x04100000) {
534 int reg = (instr >> 12) & 15;
535 unsigned long val;
536
537 if (instr & 0x00400000)
538 val = 255;
539 else
540 val = -1;
541
542 regs->uregs[reg] = val;
543 regs->ARM_pc += 4;
544 return 0;
545 }
546
547 if ((instr & 0x0e100090) == 0x00100090) {
548 int reg = (instr >> 12) & 15;
549
550 regs->uregs[reg] = -1;
551 regs->ARM_pc += 4;
552 return 0;
553 }
554
555 return 1;
556}
557
558static irqreturn_t v3_irq(int irq, void *devid)
559{
560#ifdef CONFIG_DEBUG_LL
561 struct pt_regs *regs = get_irq_regs();
562 unsigned long pc = instruction_pointer(regs);
563 unsigned long instr = *(unsigned long *)pc;
564 char buf[128];
565 extern void printascii(const char *);
566
567 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
568 "ISTAT=%02x\n", irq, pc, instr,
569 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
570 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
571 v3_readb(V3_LB_ISTAT));
572 printascii(buf);
573#endif
574
575 v3_writew(V3_PCI_STAT, 0xf000);
576 v3_writeb(V3_LB_ISTAT, 0);
577 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
578
579#ifdef CONFIG_DEBUG_LL
580
581
582
583
584 if ((instr & 0x0c100000) == 0x04100000) {
585 int reg = (instr >> 16) & 15;
586 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
587 printascii(buf);
588 }
589#endif
590 return IRQ_HANDLED;
591}
592
593static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
594{
595 int ret = 0;
596
597 if (!ap_syscon_base)
598 return -EINVAL;
599
600 if (nr == 0) {
601 sys->mem_offset = non_mem.start;
602 ret = pci_v3_setup_resources(sys);
603 }
604
605 return ret;
606}
607
608
609
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611
612static void __init pci_v3_preinit(void)
613{
614 unsigned int temp;
615 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
616
617 pcibios_min_mem = 0x00100000;
618
619
620
621
622 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
623 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
624 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
625 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
626
627
628
629
630 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
631 v3_writew(V3_SYSTEM, 0xa05f);
632
633
634
635
636
637 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
638 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
639 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
640 V3_LB_MAP_TYPE_MEM);
641
642
643
644
645
646 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
647 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
648 V3_LB_BASE_ENABLE);
649 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
650 V3_LB_MAP_TYPE_MEM_MULTIPLE);
651
652
653
654
655 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_address) |
656 V3_LB_BASE_ENABLE);
657 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
658
659
660
661
662 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
663 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
664 v3_writew(V3_PCI_CFG, temp);
665
666 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
667 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
668
669
670
671
672
673
674 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
675
676
677
678
679 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
680 v3_writew(V3_SYSTEM, temp);
681
682
683
684
685 v3_writeb(V3_LB_ISTAT, 0);
686 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
687 v3_writeb(V3_LB_IMASK, 0x28);
688 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
689}
690
691static void __init pci_v3_postinit(void)
692{
693 unsigned int pci_cmd;
694 phys_addr_t io_address = pci_pio_to_address(io_mem.start);
695
696 pci_cmd = PCI_COMMAND_MEMORY |
697 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
698
699 v3_writew(V3_PCI_CMD, pci_cmd);
700
701 v3_writeb(V3_LB_ISTAT, ~0x40);
702 v3_writeb(V3_LB_IMASK, 0x68);
703
704#if 0
705 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
706 if (ret)
707 printk(KERN_ERR "PCI: unable to grab local bus timeout "
708 "interrupt: %d\n", ret);
709#endif
710
711 register_isa_ports(non_mem.start, io_address, 0);
712}
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751static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
752{
753 if (*pinp == 0)
754 *pinp = 1;
755
756 return pci_common_swizzle(dev, pinp);
757}
758
759static struct hw_pci pci_v3 __initdata = {
760 .swizzle = pci_v3_swizzle,
761 .setup = pci_v3_setup,
762 .nr_controllers = 1,
763 .ops = &pci_v3_ops,
764 .preinit = pci_v3_preinit,
765 .postinit = pci_v3_postinit,
766};
767
768static int __init pci_v3_probe(struct platform_device *pdev)
769{
770 struct device_node *np = pdev->dev.of_node;
771 struct of_pci_range_parser parser;
772 struct of_pci_range range;
773 struct resource *res;
774 int irq, ret;
775
776
777 ap_syscon_base = devm_ioremap(&pdev->dev, INTEGRATOR_SC_BASE, 0x100);
778 if (!ap_syscon_base) {
779 dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
780 return -ENODEV;
781 }
782
783
784 if (!np) {
785 dev_err(&pdev->dev, "no device tree node for PCIv3\n");
786 return -ENODEV;
787 }
788
789 if (of_pci_range_parser_init(&parser, np))
790 return -EINVAL;
791
792
793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
794 if (!res) {
795 dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
796 return -ENODEV;
797 }
798 pci_v3_base = devm_ioremap(&pdev->dev, res->start,
799 resource_size(res));
800 if (!pci_v3_base) {
801 dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
802 return -ENODEV;
803 }
804
805
806 irq = platform_get_irq(pdev, 0);
807 if (irq <= 0) {
808 dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
809 return -ENODEV;
810 }
811 ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
812 "PCIv3 error", NULL);
813 if (ret < 0) {
814 dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
815 return ret;
816 }
817
818 for_each_of_pci_range(&parser, &range) {
819 if (!range.flags) {
820 ret = of_pci_range_to_resource(&range, np, &conf_mem);
821 conf_mem.name = "PCIv3 config";
822 }
823 if (range.flags & IORESOURCE_IO) {
824 ret = of_pci_range_to_resource(&range, np, &io_mem);
825 io_mem.name = "PCIv3 I/O";
826 }
827 if ((range.flags & IORESOURCE_MEM) &&
828 !(range.flags & IORESOURCE_PREFETCH)) {
829 non_mem_pci = range.pci_addr;
830 non_mem_pci_sz = range.size;
831 ret = of_pci_range_to_resource(&range, np, &non_mem);
832 non_mem.name = "PCIv3 non-prefetched mem";
833 }
834 if ((range.flags & IORESOURCE_MEM) &&
835 (range.flags & IORESOURCE_PREFETCH)) {
836 pre_mem_pci = range.pci_addr;
837 pre_mem_pci_sz = range.size;
838 ret = of_pci_range_to_resource(&range, np, &pre_mem);
839 pre_mem.name = "PCIv3 prefetched mem";
840 }
841
842 if (ret < 0) {
843 dev_err(&pdev->dev, "missing ranges in device node\n");
844 return ret;
845 }
846 }
847
848 pci_v3.map_irq = of_irq_parse_and_map_pci;
849 pci_common_init_dev(&pdev->dev, &pci_v3);
850
851 return 0;
852}
853
854static const struct of_device_id pci_ids[] = {
855 { .compatible = "v3,v360epc-pci", },
856 {},
857};
858
859static struct platform_driver pci_v3_driver = {
860 .driver = {
861 .name = "pci-v3",
862 .of_match_table = pci_ids,
863 },
864};
865
866static int __init pci_v3_init(void)
867{
868 return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
869}
870
871subsys_initcall(pci_v3_init);
872
873
874
875
876
877
878
879
880static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
881 {
882 .virtual = (unsigned long)PCI_MEMORY_VADDR,
883 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
884 .length = SZ_16M,
885 .type = MT_DEVICE
886 }, {
887 .virtual = (unsigned long)PCI_CONFIG_VADDR,
888 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
889 .length = SZ_16M,
890 .type = MT_DEVICE
891 }
892};
893
894int __init pci_v3_early_init(void)
895{
896 iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
897 vga_base = (unsigned long)PCI_MEMORY_VADDR;
898 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
899 return 0;
900}
901