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38#include <linux/gpio.h>
39#include <linux/init.h>
40#include <linux/module.h>
41#include <linux/sched.h>
42#include <linux/interrupt.h>
43#include <linux/io.h>
44
45#include <asm/irq.h>
46#include <asm/mach/irq.h>
47
48#include "soc.h"
49
50#include <mach/hardware.h>
51
52#include "common.h"
53
54#define IRQ_BANK(irq) ((irq) >> 5)
55#define IRQ_BIT(irq) ((irq) & 0x1f)
56
57struct omap_irq_bank {
58 unsigned long base_reg;
59 unsigned long trigger_map;
60 unsigned long wake_enable;
61};
62
63u32 omap_irq_flags;
64static unsigned int irq_bank_count;
65static struct omap_irq_bank *irq_banks;
66
67static inline void irq_bank_writel(unsigned long value, int bank, int offset)
68{
69 omap_writel(value, irq_banks[bank].base_reg + offset);
70}
71
72static void omap_ack_irq(struct irq_data *d)
73{
74 if (d->irq > 31)
75 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
76
77 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
78}
79
80static void omap_mask_irq(struct irq_data *d)
81{
82 int bank = IRQ_BANK(d->irq);
83 u32 l;
84
85 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
86 l |= 1 << IRQ_BIT(d->irq);
87 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
88}
89
90static void omap_unmask_irq(struct irq_data *d)
91{
92 int bank = IRQ_BANK(d->irq);
93 u32 l;
94
95 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
96 l &= ~(1 << IRQ_BIT(d->irq));
97 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
98}
99
100static void omap_mask_ack_irq(struct irq_data *d)
101{
102 omap_mask_irq(d);
103 omap_ack_irq(d);
104}
105
106static int omap_wake_irq(struct irq_data *d, unsigned int enable)
107{
108 int bank = IRQ_BANK(d->irq);
109
110 if (enable)
111 irq_banks[bank].wake_enable |= IRQ_BIT(d->irq);
112 else
113 irq_banks[bank].wake_enable &= ~IRQ_BIT(d->irq);
114
115 return 0;
116}
117
118
119
120
121
122
123
124
125
126static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
127{
128 signed int bank;
129 unsigned long val, offset;
130
131 bank = IRQ_BANK(irq);
132
133 fiq = bank ? 0 : (fiq & 0x1);
134 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
135 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
136 irq_bank_writel(val, bank, offset);
137}
138
139#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
140static struct omap_irq_bank omap7xx_irq_banks[] = {
141 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
142 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
143 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
144};
145#endif
146
147#ifdef CONFIG_ARCH_OMAP15XX
148static struct omap_irq_bank omap1510_irq_banks[] = {
149 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
150 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
151};
152static struct omap_irq_bank omap310_irq_banks[] = {
153 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
154 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
155};
156#endif
157
158#if defined(CONFIG_ARCH_OMAP16XX)
159
160static struct omap_irq_bank omap1610_irq_banks[] = {
161 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
162 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
163 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
164 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
165};
166#endif
167
168static struct irq_chip omap_irq_chip = {
169 .name = "MPU",
170 .irq_ack = omap_mask_ack_irq,
171 .irq_mask = omap_mask_irq,
172 .irq_unmask = omap_unmask_irq,
173 .irq_set_wake = omap_wake_irq,
174};
175
176void __init omap1_init_irq(void)
177{
178 int i, j;
179
180#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
181 if (cpu_is_omap7xx()) {
182 omap_irq_flags = INT_7XX_IH2_IRQ;
183 irq_banks = omap7xx_irq_banks;
184 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
185 }
186#endif
187#ifdef CONFIG_ARCH_OMAP15XX
188 if (cpu_is_omap1510()) {
189 omap_irq_flags = INT_1510_IH2_IRQ;
190 irq_banks = omap1510_irq_banks;
191 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
192 }
193 if (cpu_is_omap310()) {
194 omap_irq_flags = INT_1510_IH2_IRQ;
195 irq_banks = omap310_irq_banks;
196 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
197 }
198#endif
199#if defined(CONFIG_ARCH_OMAP16XX)
200 if (cpu_is_omap16xx()) {
201 omap_irq_flags = INT_1510_IH2_IRQ;
202 irq_banks = omap1610_irq_banks;
203 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
204 }
205#endif
206 printk("Total of %i interrupts in %i interrupt banks\n",
207 irq_bank_count * 32, irq_bank_count);
208
209
210 for (i = 0; i < irq_bank_count; i++) {
211 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
212 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
213 }
214
215
216 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
217 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
218
219
220 if (cpu_is_omap7xx())
221 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
222
223
224 for (i = 0; i < irq_bank_count; i++) {
225 for (j = i * 32; j < (i + 1) * 32; j++) {
226 int irq_trigger;
227
228 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
229 omap_irq_set_cfg(j, 0, 0, irq_trigger);
230
231 irq_set_chip_and_handler(j, &omap_irq_chip,
232 handle_level_irq);
233 set_irq_flags(j, IRQF_VALID);
234 }
235 }
236
237
238
239 if (cpu_is_omap7xx())
240 omap_unmask_irq(irq_get_irq_data(INT_7XX_IH2_IRQ));
241 else if (cpu_is_omap15xx())
242 omap_unmask_irq(irq_get_irq_data(INT_1510_IH2_IRQ));
243 else if (cpu_is_omap16xx())
244 omap_unmask_irq(irq_get_irq_data(INT_1610_IH2_IRQ));
245}
246
