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12#ifndef _ASM_MB93493_REGS_H
13#define _ASM_MB93493_REGS_H
14
15#include <asm/mb-regs.h>
16#include <asm/mb93493-irqs.h>
17
18#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
19#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
20
21#define __set_MB93493(X,V) \
22do { \
23 *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \
24} while(0)
25
26#define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4)
27#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
28#define MB93493_STSR_EN
29
30#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
31#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
32#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
33
34#define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4)
35#define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V))
36
37#define __get_MB93493_LBSER() __get_MB93493(0x3f0)
38#define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V))
39
40#define MB93493_LBSER_VDC 0x00010000
41#define MB93493_LBSER_VCC 0x00020000
42#define MB93493_LBSER_AUDIO 0x00040000
43#define MB93493_LBSER_I2C_0 0x00080000
44#define MB93493_LBSER_I2C_1 0x00100000
45#define MB93493_LBSER_USB 0x00200000
46#define MB93493_LBSER_GPIO 0x00800000
47#define MB93493_LBSER_PCMCIA 0x01000000
48
49#define __get_MB93493_LBSR() __get_MB93493(0x3fc)
50#define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V))
51
52
53
54
55#define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X)
56#define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V))
57
58#define MB93493_VDC_RCURSOR 0x140
59#define MB93493_VDC_RCT1 0x144
60#define MB93493_VDC_RCT2 0x148
61#define MB93493_VDC_RHDC 0x150
62#define MB93493_VDC_RH_MARGINS 0x154
63#define MB93493_VDC_RVDC 0x158
64#define MB93493_VDC_RV_MARGINS 0x15c
65#define MB93493_VDC_RC 0x170
66#define MB93493_VDC_RCLOCK 0x174
67#define MB93493_VDC_RBLACK 0x178
68#define MB93493_VDC_RS 0x17c
69
70#define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); })
71#define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X))
72
73#define VDC_TPO_WIDTH 32
74
75#define VDC_RC_DSR 0x00000080
76
77#define VDC_RS_IT 0x00060000
78#define VDC_RS_IT_UNDERFLOW 0x00040000
79#define VDC_RS_IT_VSYNC 0x00020000
80#define VDC_RS_DFI 0x00010000
81#define VDC_RS_DFI_TOP 0x00000000
82#define VDC_RS_DFI_BOTTOM 0x00010000
83#define VDC_RS_DCSR 0x00000010
84#define VDC_RS_DCM 0x00000003
85#define VDC_RS_DCM_DISABLED 0x00000000
86#define VDC_RS_DCM_STOPPED 0x00000001
87#define VDC_RS_DCM_FREERUNNING 0x00000002
88#define VDC_RS_DCM_TRANSFERRING 0x00000003
89
90
91
92
93#define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X)
94#define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V))
95
96#define MB93493_VCC_RREDUCT 0x104
97#define MB93493_VCC_RHY 0x108
98#define MB93493_VCC_RHC 0x10c
99#define MB93493_VCC_RHSIZE 0x110
100#define MB93493_VCC_RHBC 0x114
101#define MB93493_VCC_RVCC 0x118
102#define MB93493_VCC_RVBC 0x11c
103#define MB93493_VCC_RV 0x120
104#define MB93493_VCC_RDTS 0x128
105#define MB93493_VCC_RDTS_4B 0x01000000
106#define MB93493_VCC_RDTS_32B 0x03000000
107#define MB93493_VCC_RDTS_SHIFT 24
108#define MB93493_VCC_RCC 0x130
109#define MB93493_VCC_RIS 0x134
110
111#define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X))
112
113#define VCC_RHSIZE_RHCC 0x000007ff
114#define VCC_RHSIZE_RHCC_SHIFT 0
115#define VCC_RHSIZE_RHTCC 0x0fff0000
116#define VCC_RHSIZE_RHTCC_SHIFT 16
117
118#define VCC_RVBC_RVBC 0x00003f00
119#define VCC_RVBC_RVBC_SHIFT 8
120
121#define VCC_RREDUCT_RHR 0x07ff0000
122#define VCC_RREDUCT_RHR_SHIFT 16
123#define VCC_RREDUCT_RVR 0x000007ff
124#define VCC_RREDUCT_RVR_SHIFT 0
125
126#define VCC_RCC_CE 0x00000001
127#define VCC_RCC_CS 0x00000002
128#define VCC_RCC_CPF 0x0000000c
129#define VCC_RCC_CPF_YCBCR_16 0x00000000
130#define VCC_RCC_CPF_RGB 0x00000004
131#define VCC_RCC_CPF_YCBCR_24 0x00000008
132#define VCC_RCC_CPF_BT656 0x0000000c
133#define VCC_RCC_CPF_SHIFT 2
134#define VCC_RCC_CSR 0x00000080
135#define VCC_RCC_HSIP 0x00000100
136#define VCC_RCC_HSIP_LOACT 0x00000000
137#define VCC_RCC_HSIP_HIACT 0x00000100
138#define VCC_RCC_VSIP 0x00000200
139#define VCC_RCC_VSIP_LOACT 0x00000000
140#define VCC_RCC_VSIP_HIACT 0x00000200
141#define VCC_RCC_CIE 0x00000800
142#define VCC_RCC_CFP 0x00001000
143#define VCC_RCC_CFP_4TO3 0x00000000
144#define VCC_RCC_CFP_1TO1 0x00001000
145#define VCC_RCC_CSM 0x00006000
146#define VCC_RCC_CSM_ONEPASS 0x00002000
147#define VCC_RCC_CSM_INTERLACE 0x00004000
148#define VCC_RCC_CSM_SHIFT 13
149#define VCC_RCC_ES 0x00008000
150#define VCC_RCC_ES_NEG 0x00000000
151#define VCC_RCC_ES_POS 0x00008000
152#define VCC_RCC_IFI 0x00080000
153#define VCC_RCC_FDTS 0x00300000
154#define VCC_RCC_FDTS_3_8 0x00000000
155#define VCC_RCC_FDTS_1_4 0x00100000
156#define VCC_RCC_FDTS_7_16 0x00200000
157#define VCC_RCC_FDTS_SHIFT 20
158#define VCC_RCC_MOV 0x00400000
159#define VCC_RCC_STP 0x00800000
160#define VCC_RCC_TO 0x01000000
161
162#define VCC_RIS_VSYNC 0x01000000
163#define VCC_RIS_OV 0x02000000
164#define VCC_RIS_BOTTOM 0x08000000
165#define VCC_RIS_STARTED 0x10000000
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169
170#define MB93493_I2C_BSR 0x340
171#define MB93493_I2C_BCR 0x344
172#define MB93493_I2C_CCR 0x348
173#define MB93493_I2C_ADR 0x34c
174#define MB93493_I2C_DTR 0x350
175#define MB93493_I2C_BC2R 0x35c
176
177#define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20))
178#define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20))
179#define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V))
180
181#define I2C_BSR_BB (1 << 7)
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185
186#define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X)
187#define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V))
188
189#define MB93493_I2S_ALDR 0x300
190#define MB93493_I2S_ARDR 0x304
191#define MB93493_I2S_APDR 0x308
192#define MB93493_I2S_AISTR 0x310
193#define MB93493_I2S_AICR 0x314
194
195#define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X))
196#define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X))
197#define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X))
198#define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X))
199
200#define I2S_AISTR_OTST 0x00000003
201#define I2S_AISTR_OTR 0x00000010
202#define I2S_AISTR_OUR 0x00000020
203#define I2S_AISTR_OOR 0x00000040
204#define I2S_AISTR_ODS 0x00000100
205#define I2S_AISTR_ODE 0x00000400
206#define I2S_AISTR_OTRIE 0x00001000
207#define I2S_AISTR_OURIE 0x00002000
208#define I2S_AISTR_OORIE 0x00004000
209#define I2S_AISTR__OUT_MASK 0x00007570
210#define I2S_AISTR_ITST 0x00030000
211#define I2S_AISTR_ITST_SHIFT 16
212#define I2S_AISTR_ITR 0x00100000
213#define I2S_AISTR_IUR 0x00200000
214#define I2S_AISTR_IOR 0x00400000
215#define I2S_AISTR_IDS 0x01000000
216#define I2S_AISTR_IDE 0x04000000
217#define I2S_AISTR_ITRIE 0x10000000
218#define I2S_AISTR_IURIE 0x20000000
219#define I2S_AISTR_IORIE 0x40000000
220#define I2S_AISTR__IN_MASK 0x75700000
221
222#define I2S_AICR_MI 0x00000001
223#define I2S_AICR_AMI 0x00000002
224#define I2S_AICR_LRI 0x00000004
225#define I2S_AICR_SDMI 0x00000070
226#define I2S_AICR_SDMI_SHIFT 4
227#define I2S_AICR_CLI 0x00000080
228#define I2S_AICR_IM 0x00000300
229#define I2S_AICR_IM_SHIFT 8
230#define I2S_AICR__IN_MASK 0x000003f7
231#define I2S_AICR_MO 0x00001000
232#define I2S_AICR_AMO 0x00002000
233#define I2S_AICR_AMO_SHIFT 13
234#define I2S_AICR_LRO 0x00004000
235#define I2S_AICR_SDMO 0x00070000
236#define I2S_AICR_SDMO_SHIFT 16
237#define I2S_AICR_CLO 0x00080000
238#define I2S_AICR_OM 0x00100000
239#define I2S_AICR__OUT_MASK 0x001f7000
240#define I2S_AICR_DIV 0x03000000
241#define I2S_AICR_DIV_SHIFT 24
242#define I2S_AICR_FL 0x20000000
243#define I2S_AICR_FS 0x40000000
244#define I2S_AICR_ME 0x80000000
245
246
247
248
249#define __addr_MB93493_PCMCIA(X) ((volatile unsigned long *)(__region_CS5 + (X)))
250
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253
254#define __get_MB93493_GPIO_PDR(X) __get_MB93493(0x380 + (X) * 0xc0)
255#define __set_MB93493_GPIO_PDR(X,V) __set_MB93493(0x380 + (X) * 0xc0, (V))
256
257#define __get_MB93493_GPIO_GPDR(X) __get_MB93493(0x384 + (X) * 0xc0)
258#define __set_MB93493_GPIO_GPDR(X,V) __set_MB93493(0x384 + (X) * 0xc0, (V))
259
260#define __get_MB93493_GPIO_SIR(X) __get_MB93493(0x388 + (X) * 0xc0)
261#define __set_MB93493_GPIO_SIR(X,V) __set_MB93493(0x388 + (X) * 0xc0, (V))
262
263#define __get_MB93493_GPIO_SOR(X) __get_MB93493(0x38c + (X) * 0xc0)
264#define __set_MB93493_GPIO_SOR(X,V) __set_MB93493(0x38c + (X) * 0xc0, (V))
265
266#define __get_MB93493_GPIO_PDSR(X) __get_MB93493(0x390 + (X) * 0xc0)
267#define __set_MB93493_GPIO_PDSR(X,V) __set_MB93493(0x390 + (X) * 0xc0, (V))
268
269#define __get_MB93493_GPIO_PDCR(X) __get_MB93493(0x394 + (X) * 0xc0)
270#define __set_MB93493_GPIO_PDCR(X,V) __set_MB93493(0x394 + (X) * 0xc0, (V))
271
272#define __get_MB93493_GPIO_INTST(X) __get_MB93493(0x398 + (X) * 0xc0)
273#define __set_MB93493_GPIO_INTST(X,V) __set_MB93493(0x398 + (X) * 0xc0, (V))
274
275#define __get_MB93493_GPIO_IEHL(X) __get_MB93493(0x39c + (X) * 0xc0)
276#define __set_MB93493_GPIO_IEHL(X,V) __set_MB93493(0x39c + (X) * 0xc0, (V))
277
278#define __get_MB93493_GPIO_IELH(X) __get_MB93493(0x3a0 + (X) * 0xc0)
279#define __set_MB93493_GPIO_IELH(X,V) __set_MB93493(0x3a0 + (X) * 0xc0, (V))
280
281#endif
282