linux/arch/ia64/kernel/mca.c
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   1/*
   2 * File:        mca.c
   3 * Purpose:     Generic MCA handling layer
   4 *
   5 * Copyright (C) 2003 Hewlett-Packard Co
   6 *      David Mosberger-Tang <davidm@hpl.hp.com>
   7 *
   8 * Copyright (C) 2002 Dell Inc.
   9 * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
  10 *
  11 * Copyright (C) 2002 Intel
  12 * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
  13 *
  14 * Copyright (C) 2001 Intel
  15 * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
  16 *
  17 * Copyright (C) 2000 Intel
  18 * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
  19 *
  20 * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
  21 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
  22 *
  23 * Copyright (C) 2006 FUJITSU LIMITED
  24 * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  25 *
  26 * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
  27 *            Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  28 *            added min save state dump, added INIT handler.
  29 *
  30 * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
  31 *            Added setup of CMCI and CPEI IRQs, logging of corrected platform
  32 *            errors, completed code for logging of corrected & uncorrected
  33 *            machine check errors, and updated for conformance with Nov. 2000
  34 *            revision of the SAL 3.0 spec.
  35 *
  36 * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
  37 *            Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
  38 *            set SAL default return values, changed error record structure to
  39 *            linked list, added init call to sal_get_state_info_size().
  40 *
  41 * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
  42 *            GUID cleanups.
  43 *
  44 * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
  45 *            Added INIT backtrace support.
  46 *
  47 * 2003-12-08 Keith Owens <kaos@sgi.com>
  48 *            smp_call_function() must not be called from interrupt context
  49 *            (can deadlock on tasklist_lock).
  50 *            Use keventd to call smp_call_function().
  51 *
  52 * 2004-02-01 Keith Owens <kaos@sgi.com>
  53 *            Avoid deadlock when using printk() for MCA and INIT records.
  54 *            Delete all record printing code, moved to salinfo_decode in user
  55 *            space.  Mark variables and functions static where possible.
  56 *            Delete dead variables and functions.  Reorder to remove the need
  57 *            for forward declarations and to consolidate related code.
  58 *
  59 * 2005-08-12 Keith Owens <kaos@sgi.com>
  60 *            Convert MCA/INIT handlers to use per event stacks and SAL/OS
  61 *            state.
  62 *
  63 * 2005-10-07 Keith Owens <kaos@sgi.com>
  64 *            Add notify_die() hooks.
  65 *
  66 * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  67 *            Add printing support for MCA/INIT.
  68 *
  69 * 2007-04-27 Russ Anderson <rja@sgi.com>
  70 *            Support multiple cpus going through OS_MCA in the same event.
  71 */
  72#include <linux/jiffies.h>
  73#include <linux/types.h>
  74#include <linux/init.h>
  75#include <linux/sched.h>
  76#include <linux/interrupt.h>
  77#include <linux/irq.h>
  78#include <linux/bootmem.h>
  79#include <linux/acpi.h>
  80#include <linux/timer.h>
  81#include <linux/module.h>
  82#include <linux/kernel.h>
  83#include <linux/smp.h>
  84#include <linux/workqueue.h>
  85#include <linux/cpumask.h>
  86#include <linux/kdebug.h>
  87#include <linux/cpu.h>
  88#include <linux/gfp.h>
  89
  90#include <asm/delay.h>
  91#include <asm/machvec.h>
  92#include <asm/meminit.h>
  93#include <asm/page.h>
  94#include <asm/ptrace.h>
  95#include <asm/sal.h>
  96#include <asm/mca.h>
  97#include <asm/kexec.h>
  98
  99#include <asm/irq.h>
 100#include <asm/hw_irq.h>
 101#include <asm/tlb.h>
 102
 103#include "mca_drv.h"
 104#include "entry.h"
 105
 106#if defined(IA64_MCA_DEBUG_INFO)
 107# define IA64_MCA_DEBUG(fmt...) printk(fmt)
 108#else
 109# define IA64_MCA_DEBUG(fmt...)
 110#endif
 111
 112#define NOTIFY_INIT(event, regs, arg, spin)                             \
 113do {                                                                    \
 114        if ((notify_die((event), "INIT", (regs), (arg), 0, 0)           \
 115                        == NOTIFY_STOP) && ((spin) == 1))               \
 116                ia64_mca_spin(__func__);                                \
 117} while (0)
 118
 119#define NOTIFY_MCA(event, regs, arg, spin)                              \
 120do {                                                                    \
 121        if ((notify_die((event), "MCA", (regs), (arg), 0, 0)            \
 122                        == NOTIFY_STOP) && ((spin) == 1))               \
 123                ia64_mca_spin(__func__);                                \
 124} while (0)
 125
 126/* Used by mca_asm.S */
 127DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
 128DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
 129DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
 130DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
 131DEFINE_PER_CPU(u64, ia64_mca_tr_reload);   /* Flag for TR reload */
 132
 133unsigned long __per_cpu_mca[NR_CPUS];
 134
 135/* In mca_asm.S */
 136extern void                     ia64_os_init_dispatch_monarch (void);
 137extern void                     ia64_os_init_dispatch_slave (void);
 138
 139static int monarch_cpu = -1;
 140
 141static ia64_mc_info_t           ia64_mc_info;
 142
 143#define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 144#define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 145#define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 146#define CPE_HISTORY_LENGTH    5
 147#define CMC_HISTORY_LENGTH    5
 148
 149#ifdef CONFIG_ACPI
 150static struct timer_list cpe_poll_timer;
 151#endif
 152static struct timer_list cmc_poll_timer;
 153/*
 154 * This variable tells whether we are currently in polling mode.
 155 * Start with this in the wrong state so we won't play w/ timers
 156 * before the system is ready.
 157 */
 158static int cmc_polling_enabled = 1;
 159
 160/*
 161 * Clearing this variable prevents CPE polling from getting activated
 162 * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 163 * but encounters problems retrieving CPE logs.  This should only be
 164 * necessary for debugging.
 165 */
 166static int cpe_poll_enabled = 1;
 167
 168extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 169
 170static int mca_init __initdata;
 171
 172/*
 173 * limited & delayed printing support for MCA/INIT handler
 174 */
 175
 176#define mprintk(fmt...) ia64_mca_printk(fmt)
 177
 178#define MLOGBUF_SIZE (512+256*NR_CPUS)
 179#define MLOGBUF_MSGMAX 256
 180static char mlogbuf[MLOGBUF_SIZE];
 181static DEFINE_SPINLOCK(mlogbuf_wlock);  /* mca context only */
 182static DEFINE_SPINLOCK(mlogbuf_rlock);  /* normal context only */
 183static unsigned long mlogbuf_start;
 184static unsigned long mlogbuf_end;
 185static unsigned int mlogbuf_finished = 0;
 186static unsigned long mlogbuf_timestamp = 0;
 187
 188static int loglevel_save = -1;
 189#define BREAK_LOGLEVEL(__console_loglevel)              \
 190        oops_in_progress = 1;                           \
 191        if (loglevel_save < 0)                          \
 192                loglevel_save = __console_loglevel;     \
 193        __console_loglevel = 15;
 194
 195#define RESTORE_LOGLEVEL(__console_loglevel)            \
 196        if (loglevel_save >= 0) {                       \
 197                __console_loglevel = loglevel_save;     \
 198                loglevel_save = -1;                     \
 199        }                                               \
 200        mlogbuf_finished = 0;                           \
 201        oops_in_progress = 0;
 202
 203/*
 204 * Push messages into buffer, print them later if not urgent.
 205 */
 206void ia64_mca_printk(const char *fmt, ...)
 207{
 208        va_list args;
 209        int printed_len;
 210        char temp_buf[MLOGBUF_MSGMAX];
 211        char *p;
 212
 213        va_start(args, fmt);
 214        printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
 215        va_end(args);
 216
 217        /* Copy the output into mlogbuf */
 218        if (oops_in_progress) {
 219                /* mlogbuf was abandoned, use printk directly instead. */
 220                printk("%s", temp_buf);
 221        } else {
 222                spin_lock(&mlogbuf_wlock);
 223                for (p = temp_buf; *p; p++) {
 224                        unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
 225                        if (next != mlogbuf_start) {
 226                                mlogbuf[mlogbuf_end] = *p;
 227                                mlogbuf_end = next;
 228                        } else {
 229                                /* buffer full */
 230                                break;
 231                        }
 232                }
 233                mlogbuf[mlogbuf_end] = '\0';
 234                spin_unlock(&mlogbuf_wlock);
 235        }
 236}
 237EXPORT_SYMBOL(ia64_mca_printk);
 238
 239/*
 240 * Print buffered messages.
 241 *  NOTE: call this after returning normal context. (ex. from salinfod)
 242 */
 243void ia64_mlogbuf_dump(void)
 244{
 245        char temp_buf[MLOGBUF_MSGMAX];
 246        char *p;
 247        unsigned long index;
 248        unsigned long flags;
 249        unsigned int printed_len;
 250
 251        /* Get output from mlogbuf */
 252        while (mlogbuf_start != mlogbuf_end) {
 253                temp_buf[0] = '\0';
 254                p = temp_buf;
 255                printed_len = 0;
 256
 257                spin_lock_irqsave(&mlogbuf_rlock, flags);
 258
 259                index = mlogbuf_start;
 260                while (index != mlogbuf_end) {
 261                        *p = mlogbuf[index];
 262                        index = (index + 1) % MLOGBUF_SIZE;
 263                        if (!*p)
 264                                break;
 265                        p++;
 266                        if (++printed_len >= MLOGBUF_MSGMAX - 1)
 267                                break;
 268                }
 269                *p = '\0';
 270                if (temp_buf[0])
 271                        printk("%s", temp_buf);
 272                mlogbuf_start = index;
 273
 274                mlogbuf_timestamp = 0;
 275                spin_unlock_irqrestore(&mlogbuf_rlock, flags);
 276        }
 277}
 278EXPORT_SYMBOL(ia64_mlogbuf_dump);
 279
 280/*
 281 * Call this if system is going to down or if immediate flushing messages to
 282 * console is required. (ex. recovery was failed, crash dump is going to be
 283 * invoked, long-wait rendezvous etc.)
 284 *  NOTE: this should be called from monarch.
 285 */
 286static void ia64_mlogbuf_finish(int wait)
 287{
 288        BREAK_LOGLEVEL(console_loglevel);
 289
 290        spin_lock_init(&mlogbuf_rlock);
 291        ia64_mlogbuf_dump();
 292        printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
 293                "MCA/INIT might be dodgy or fail.\n");
 294
 295        if (!wait)
 296                return;
 297
 298        /* wait for console */
 299        printk("Delaying for 5 seconds...\n");
 300        udelay(5*1000000);
 301
 302        mlogbuf_finished = 1;
 303}
 304
 305/*
 306 * Print buffered messages from INIT context.
 307 */
 308static void ia64_mlogbuf_dump_from_init(void)
 309{
 310        if (mlogbuf_finished)
 311                return;
 312
 313        if (mlogbuf_timestamp &&
 314                        time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
 315                printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
 316                        " and the system seems to be messed up.\n");
 317                ia64_mlogbuf_finish(0);
 318                return;
 319        }
 320
 321        if (!spin_trylock(&mlogbuf_rlock)) {
 322                printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
 323                        "Generated messages other than stack dump will be "
 324                        "buffered to mlogbuf and will be printed later.\n");
 325                printk(KERN_ERR "INIT: If messages would not printed after "
 326                        "this INIT, wait 30sec and assert INIT again.\n");
 327                if (!mlogbuf_timestamp)
 328                        mlogbuf_timestamp = jiffies;
 329                return;
 330        }
 331        spin_unlock(&mlogbuf_rlock);
 332        ia64_mlogbuf_dump();
 333}
 334
 335static void inline
 336ia64_mca_spin(const char *func)
 337{
 338        if (monarch_cpu == smp_processor_id())
 339                ia64_mlogbuf_finish(0);
 340        mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
 341        while (1)
 342                cpu_relax();
 343}
 344/*
 345 * IA64_MCA log support
 346 */
 347#define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 348#define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 349
 350typedef struct ia64_state_log_s
 351{
 352        spinlock_t      isl_lock;
 353        int             isl_index;
 354        unsigned long   isl_count;
 355        ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 356} ia64_state_log_t;
 357
 358static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 359
 360#define IA64_LOG_ALLOCATE(it, size) \
 361        {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 362                (ia64_err_rec_t *)alloc_bootmem(size); \
 363        ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 364                (ia64_err_rec_t *)alloc_bootmem(size);}
 365#define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 366#define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 367#define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 368#define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 369#define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 370#define IA64_LOG_INDEX_INC(it) \
 371    {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 372    ia64_state_log[it].isl_count++;}
 373#define IA64_LOG_INDEX_DEC(it) \
 374    ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 375#define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 376#define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 377#define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 378
 379/*
 380 * ia64_log_init
 381 *      Reset the OS ia64 log buffer
 382 * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 383 * Outputs      :       None
 384 */
 385static void __init
 386ia64_log_init(int sal_info_type)
 387{
 388        u64     max_size = 0;
 389
 390        IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 391        IA64_LOG_LOCK_INIT(sal_info_type);
 392
 393        // SAL will tell us the maximum size of any error record of this type
 394        max_size = ia64_sal_get_state_info_size(sal_info_type);
 395        if (!max_size)
 396                /* alloc_bootmem() doesn't like zero-sized allocations! */
 397                return;
 398
 399        // set up OS data structures to hold error info
 400        IA64_LOG_ALLOCATE(sal_info_type, max_size);
 401        memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 402        memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 403}
 404
 405/*
 406 * ia64_log_get
 407 *
 408 *      Get the current MCA log from SAL and copy it into the OS log buffer.
 409 *
 410 *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 411 *              irq_safe    whether you can use printk at this point
 412 *  Outputs :   size        (total record length)
 413 *              *buffer     (ptr to error record)
 414 *
 415 */
 416static u64
 417ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 418{
 419        sal_log_record_header_t     *log_buffer;
 420        u64                         total_len = 0;
 421        unsigned long               s;
 422
 423        IA64_LOG_LOCK(sal_info_type);
 424
 425        /* Get the process state information */
 426        log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 427
 428        total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 429
 430        if (total_len) {
 431                IA64_LOG_INDEX_INC(sal_info_type);
 432                IA64_LOG_UNLOCK(sal_info_type);
 433                if (irq_safe) {
 434                        IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
 435                                       __func__, sal_info_type, total_len);
 436                }
 437                *buffer = (u8 *) log_buffer;
 438                return total_len;
 439        } else {
 440                IA64_LOG_UNLOCK(sal_info_type);
 441                return 0;
 442        }
 443}
 444
 445/*
 446 *  ia64_mca_log_sal_error_record
 447 *
 448 *  This function retrieves a specified error record type from SAL
 449 *  and wakes up any processes waiting for error records.
 450 *
 451 *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
 452 *              FIXME: remove MCA and irq_safe.
 453 */
 454static void
 455ia64_mca_log_sal_error_record(int sal_info_type)
 456{
 457        u8 *buffer;
 458        sal_log_record_header_t *rh;
 459        u64 size;
 460        int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
 461#ifdef IA64_MCA_DEBUG_INFO
 462        static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 463#endif
 464
 465        size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 466        if (!size)
 467                return;
 468
 469        salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 470
 471        if (irq_safe)
 472                IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 473                        smp_processor_id(),
 474                        sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 475
 476        /* Clear logs from corrected errors in case there's no user-level logger */
 477        rh = (sal_log_record_header_t *)buffer;
 478        if (rh->severity == sal_log_severity_corrected)
 479                ia64_sal_clear_state_info(sal_info_type);
 480}
 481
 482/*
 483 * search_mca_table
 484 *  See if the MCA surfaced in an instruction range
 485 *  that has been tagged as recoverable.
 486 *
 487 *  Inputs
 488 *      first   First address range to check
 489 *      last    Last address range to check
 490 *      ip      Instruction pointer, address we are looking for
 491 *
 492 * Return value:
 493 *      1 on Success (in the table)/ 0 on Failure (not in the  table)
 494 */
 495int
 496search_mca_table (const struct mca_table_entry *first,
 497                const struct mca_table_entry *last,
 498                unsigned long ip)
 499{
 500        const struct mca_table_entry *curr;
 501        u64 curr_start, curr_end;
 502
 503        curr = first;
 504        while (curr <= last) {
 505                curr_start = (u64) &curr->start_addr + curr->start_addr;
 506                curr_end = (u64) &curr->end_addr + curr->end_addr;
 507
 508                if ((ip >= curr_start) && (ip <= curr_end)) {
 509                        return 1;
 510                }
 511                curr++;
 512        }
 513        return 0;
 514}
 515
 516/* Given an address, look for it in the mca tables. */
 517int mca_recover_range(unsigned long addr)
 518{
 519        extern struct mca_table_entry __start___mca_table[];
 520        extern struct mca_table_entry __stop___mca_table[];
 521
 522        return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
 523}
 524EXPORT_SYMBOL_GPL(mca_recover_range);
 525
 526#ifdef CONFIG_ACPI
 527
 528int cpe_vector = -1;
 529int ia64_cpe_irq = -1;
 530
 531static irqreturn_t
 532ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
 533{
 534        static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 535        static int              index;
 536        static DEFINE_SPINLOCK(cpe_history_lock);
 537
 538        IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 539                       __func__, cpe_irq, smp_processor_id());
 540
 541        /* SAL spec states this should run w/ interrupts enabled */
 542        local_irq_enable();
 543
 544        spin_lock(&cpe_history_lock);
 545        if (!cpe_poll_enabled && cpe_vector >= 0) {
 546
 547                int i, count = 1; /* we know 1 happened now */
 548                unsigned long now = jiffies;
 549
 550                for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 551                        if (now - cpe_history[i] <= HZ)
 552                                count++;
 553                }
 554
 555                IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 556                if (count >= CPE_HISTORY_LENGTH) {
 557
 558                        cpe_poll_enabled = 1;
 559                        spin_unlock(&cpe_history_lock);
 560                        disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 561
 562                        /*
 563                         * Corrected errors will still be corrected, but
 564                         * make sure there's a log somewhere that indicates
 565                         * something is generating more than we can handle.
 566                         */
 567                        printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 568
 569                        mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 570
 571                        /* lock already released, get out now */
 572                        goto out;
 573                } else {
 574                        cpe_history[index++] = now;
 575                        if (index == CPE_HISTORY_LENGTH)
 576                                index = 0;
 577                }
 578        }
 579        spin_unlock(&cpe_history_lock);
 580out:
 581        /* Get the CPE error record and log it */
 582        ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 583
 584        local_irq_disable();
 585
 586        return IRQ_HANDLED;
 587}
 588
 589#endif /* CONFIG_ACPI */
 590
 591#ifdef CONFIG_ACPI
 592/*
 593 * ia64_mca_register_cpev
 594 *
 595 *  Register the corrected platform error vector with SAL.
 596 *
 597 *  Inputs
 598 *      cpev        Corrected Platform Error Vector number
 599 *
 600 *  Outputs
 601 *      None
 602 */
 603void
 604ia64_mca_register_cpev (int cpev)
 605{
 606        /* Register the CPE interrupt vector with SAL */
 607        struct ia64_sal_retval isrv;
 608
 609        isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 610        if (isrv.status) {
 611                printk(KERN_ERR "Failed to register Corrected Platform "
 612                       "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 613                return;
 614        }
 615
 616        IA64_MCA_DEBUG("%s: corrected platform error "
 617                       "vector %#x registered\n", __func__, cpev);
 618}
 619#endif /* CONFIG_ACPI */
 620
 621/*
 622 * ia64_mca_cmc_vector_setup
 623 *
 624 *  Setup the corrected machine check vector register in the processor.
 625 *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 626 *  This function is invoked on a per-processor basis.
 627 *
 628 * Inputs
 629 *      None
 630 *
 631 * Outputs
 632 *      None
 633 */
 634void
 635ia64_mca_cmc_vector_setup (void)
 636{
 637        cmcv_reg_t      cmcv;
 638
 639        cmcv.cmcv_regval        = 0;
 640        cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 641        cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 642        ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 643
 644        IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
 645                       __func__, smp_processor_id(), IA64_CMC_VECTOR);
 646
 647        IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 648                       __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 649}
 650
 651/*
 652 * ia64_mca_cmc_vector_disable
 653 *
 654 *  Mask the corrected machine check vector register in the processor.
 655 *  This function is invoked on a per-processor basis.
 656 *
 657 * Inputs
 658 *      dummy(unused)
 659 *
 660 * Outputs
 661 *      None
 662 */
 663static void
 664ia64_mca_cmc_vector_disable (void *dummy)
 665{
 666        cmcv_reg_t      cmcv;
 667
 668        cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 669
 670        cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 671        ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 672
 673        IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
 674                       __func__, smp_processor_id(), cmcv.cmcv_vector);
 675}
 676
 677/*
 678 * ia64_mca_cmc_vector_enable
 679 *
 680 *  Unmask the corrected machine check vector register in the processor.
 681 *  This function is invoked on a per-processor basis.
 682 *
 683 * Inputs
 684 *      dummy(unused)
 685 *
 686 * Outputs
 687 *      None
 688 */
 689static void
 690ia64_mca_cmc_vector_enable (void *dummy)
 691{
 692        cmcv_reg_t      cmcv;
 693
 694        cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 695
 696        cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 697        ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 698
 699        IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
 700                       __func__, smp_processor_id(), cmcv.cmcv_vector);
 701}
 702
 703/*
 704 * ia64_mca_cmc_vector_disable_keventd
 705 *
 706 * Called via keventd (smp_call_function() is not safe in interrupt context) to
 707 * disable the cmc interrupt vector.
 708 */
 709static void
 710ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
 711{
 712        on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 0);
 713}
 714
 715/*
 716 * ia64_mca_cmc_vector_enable_keventd
 717 *
 718 * Called via keventd (smp_call_function() is not safe in interrupt context) to
 719 * enable the cmc interrupt vector.
 720 */
 721static void
 722ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
 723{
 724        on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 0);
 725}
 726
 727/*
 728 * ia64_mca_wakeup
 729 *
 730 *      Send an inter-cpu interrupt to wake-up a particular cpu.
 731 *
 732 *  Inputs  :   cpuid
 733 *  Outputs :   None
 734 */
 735static void
 736ia64_mca_wakeup(int cpu)
 737{
 738        platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 739}
 740
 741/*
 742 * ia64_mca_wakeup_all
 743 *
 744 *      Wakeup all the slave cpus which have rendez'ed previously.
 745 *
 746 *  Inputs  :   None
 747 *  Outputs :   None
 748 */
 749static void
 750ia64_mca_wakeup_all(void)
 751{
 752        int cpu;
 753
 754        /* Clear the Rendez checkin flag for all cpus */
 755        for_each_online_cpu(cpu) {
 756                if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 757                        ia64_mca_wakeup(cpu);
 758        }
 759
 760}
 761
 762/*
 763 * ia64_mca_rendez_interrupt_handler
 764 *
 765 *      This is handler used to put slave processors into spinloop
 766 *      while the monarch processor does the mca handling and later
 767 *      wake each slave up once the monarch is done.  The state
 768 *      IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
 769 *      in SAL.  The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
 770 *      the cpu has come out of OS rendezvous.
 771 *
 772 *  Inputs  :   None
 773 *  Outputs :   None
 774 */
 775static irqreturn_t
 776ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
 777{
 778        unsigned long flags;
 779        int cpu = smp_processor_id();
 780        struct ia64_mca_notify_die nd =
 781                { .sos = NULL, .monarch_cpu = &monarch_cpu };
 782
 783        /* Mask all interrupts */
 784        local_irq_save(flags);
 785
 786        NOTIFY_MCA(DIE_MCA_RENDZVOUS_ENTER, get_irq_regs(), (long)&nd, 1);
 787
 788        ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 789        /* Register with the SAL monarch that the slave has
 790         * reached SAL
 791         */
 792        ia64_sal_mc_rendez();
 793
 794        NOTIFY_MCA(DIE_MCA_RENDZVOUS_PROCESS, get_irq_regs(), (long)&nd, 1);
 795
 796        /* Wait for the monarch cpu to exit. */
 797        while (monarch_cpu != -1)
 798               cpu_relax();     /* spin until monarch leaves */
 799
 800        NOTIFY_MCA(DIE_MCA_RENDZVOUS_LEAVE, get_irq_regs(), (long)&nd, 1);
 801
 802        ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 803        /* Enable all interrupts */
 804        local_irq_restore(flags);
 805        return IRQ_HANDLED;
 806}
 807
 808/*
 809 * ia64_mca_wakeup_int_handler
 810 *
 811 *      The interrupt handler for processing the inter-cpu interrupt to the
 812 *      slave cpu which was spinning in the rendez loop.
 813 *      Since this spinning is done by turning off the interrupts and
 814 *      polling on the wakeup-interrupt bit in the IRR, there is
 815 *      nothing useful to be done in the handler.
 816 *
 817 *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 818 *      arg             (Interrupt handler specific argument)
 819 *  Outputs :   None
 820 *
 821 */
 822static irqreturn_t
 823ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
 824{
 825        return IRQ_HANDLED;
 826}
 827
 828/* Function pointer for extra MCA recovery */
 829int (*ia64_mca_ucmc_extension)
 830        (void*,struct ia64_sal_os_state*)
 831        = NULL;
 832
 833int
 834ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
 835{
 836        if (ia64_mca_ucmc_extension)
 837                return 1;
 838
 839        ia64_mca_ucmc_extension = fn;
 840        return 0;
 841}
 842
 843void
 844ia64_unreg_MCA_extension(void)
 845{
 846        if (ia64_mca_ucmc_extension)
 847                ia64_mca_ucmc_extension = NULL;
 848}
 849
 850EXPORT_SYMBOL(ia64_reg_MCA_extension);
 851EXPORT_SYMBOL(ia64_unreg_MCA_extension);
 852
 853
 854static inline void
 855copy_reg(const u64 *fr, u64 fnat, unsigned long *tr, unsigned long *tnat)
 856{
 857        u64 fslot, tslot, nat;
 858        *tr = *fr;
 859        fslot = ((unsigned long)fr >> 3) & 63;
 860        tslot = ((unsigned long)tr >> 3) & 63;
 861        *tnat &= ~(1UL << tslot);
 862        nat = (fnat >> fslot) & 1;
 863        *tnat |= (nat << tslot);
 864}
 865
 866/* Change the comm field on the MCA/INT task to include the pid that
 867 * was interrupted, it makes for easier debugging.  If that pid was 0
 868 * (swapper or nested MCA/INIT) then use the start of the previous comm
 869 * field suffixed with its cpu.
 870 */
 871
 872static void
 873ia64_mca_modify_comm(const struct task_struct *previous_current)
 874{
 875        char *p, comm[sizeof(current->comm)];
 876        if (previous_current->pid)
 877                snprintf(comm, sizeof(comm), "%s %d",
 878                        current->comm, previous_current->pid);
 879        else {
 880                int l;
 881                if ((p = strchr(previous_current->comm, ' ')))
 882                        l = p - previous_current->comm;
 883                else
 884                        l = strlen(previous_current->comm);
 885                snprintf(comm, sizeof(comm), "%s %*s %d",
 886                        current->comm, l, previous_current->comm,
 887                        task_thread_info(previous_current)->cpu);
 888        }
 889        memcpy(current->comm, comm, sizeof(current->comm));
 890}
 891
 892static void
 893finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos,
 894                unsigned long *nat)
 895{
 896        const pal_min_state_area_t *ms = sos->pal_min_state;
 897        const u64 *bank;
 898
 899        /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
 900         * pmsa_{xip,xpsr,xfs}
 901         */
 902        if (ia64_psr(regs)->ic) {
 903                regs->cr_iip = ms->pmsa_iip;
 904                regs->cr_ipsr = ms->pmsa_ipsr;
 905                regs->cr_ifs = ms->pmsa_ifs;
 906        } else {
 907                regs->cr_iip = ms->pmsa_xip;
 908                regs->cr_ipsr = ms->pmsa_xpsr;
 909                regs->cr_ifs = ms->pmsa_xfs;
 910
 911                sos->iip = ms->pmsa_iip;
 912                sos->ipsr = ms->pmsa_ipsr;
 913                sos->ifs = ms->pmsa_ifs;
 914        }
 915        regs->pr = ms->pmsa_pr;
 916        regs->b0 = ms->pmsa_br0;
 917        regs->ar_rsc = ms->pmsa_rsc;
 918        copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &regs->r1, nat);
 919        copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &regs->r2, nat);
 920        copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &regs->r3, nat);
 921        copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &regs->r8, nat);
 922        copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &regs->r9, nat);
 923        copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &regs->r10, nat);
 924        copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &regs->r11, nat);
 925        copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &regs->r12, nat);
 926        copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &regs->r13, nat);
 927        copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &regs->r14, nat);
 928        copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &regs->r15, nat);
 929        if (ia64_psr(regs)->bn)
 930                bank = ms->pmsa_bank1_gr;
 931        else
 932                bank = ms->pmsa_bank0_gr;
 933        copy_reg(&bank[16-16], ms->pmsa_nat_bits, &regs->r16, nat);
 934        copy_reg(&bank[17-16], ms->pmsa_nat_bits, &regs->r17, nat);
 935        copy_reg(&bank[18-16], ms->pmsa_nat_bits, &regs->r18, nat);
 936        copy_reg(&bank[19-16], ms->pmsa_nat_bits, &regs->r19, nat);
 937        copy_reg(&bank[20-16], ms->pmsa_nat_bits, &regs->r20, nat);
 938        copy_reg(&bank[21-16], ms->pmsa_nat_bits, &regs->r21, nat);
 939        copy_reg(&bank[22-16], ms->pmsa_nat_bits, &regs->r22, nat);
 940        copy_reg(&bank[23-16], ms->pmsa_nat_bits, &regs->r23, nat);
 941        copy_reg(&bank[24-16], ms->pmsa_nat_bits, &regs->r24, nat);
 942        copy_reg(&bank[25-16], ms->pmsa_nat_bits, &regs->r25, nat);
 943        copy_reg(&bank[26-16], ms->pmsa_nat_bits, &regs->r26, nat);
 944        copy_reg(&bank[27-16], ms->pmsa_nat_bits, &regs->r27, nat);
 945        copy_reg(&bank[28-16], ms->pmsa_nat_bits, &regs->r28, nat);
 946        copy_reg(&bank[29-16], ms->pmsa_nat_bits, &regs->r29, nat);
 947        copy_reg(&bank[30-16], ms->pmsa_nat_bits, &regs->r30, nat);
 948        copy_reg(&bank[31-16], ms->pmsa_nat_bits, &regs->r31, nat);
 949}
 950
 951/* On entry to this routine, we are running on the per cpu stack, see
 952 * mca_asm.h.  The original stack has not been touched by this event.  Some of
 953 * the original stack's registers will be in the RBS on this stack.  This stack
 954 * also contains a partial pt_regs and switch_stack, the rest of the data is in
 955 * PAL minstate.
 956 *
 957 * The first thing to do is modify the original stack to look like a blocked
 958 * task so we can run backtrace on the original task.  Also mark the per cpu
 959 * stack as current to ensure that we use the correct task state, it also means
 960 * that we can do backtrace on the MCA/INIT handler code itself.
 961 */
 962
 963static struct task_struct *
 964ia64_mca_modify_original_stack(struct pt_regs *regs,
 965                const struct switch_stack *sw,
 966                struct ia64_sal_os_state *sos,
 967                const char *type)
 968{
 969        char *p;
 970        ia64_va va;
 971        extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
 972        const pal_min_state_area_t *ms = sos->pal_min_state;
 973        struct task_struct *previous_current;
 974        struct pt_regs *old_regs;
 975        struct switch_stack *old_sw;
 976        unsigned size = sizeof(struct pt_regs) +
 977                        sizeof(struct switch_stack) + 16;
 978        unsigned long *old_bspstore, *old_bsp;
 979        unsigned long *new_bspstore, *new_bsp;
 980        unsigned long old_unat, old_rnat, new_rnat, nat;
 981        u64 slots, loadrs = regs->loadrs;
 982        u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
 983        u64 ar_bspstore = regs->ar_bspstore;
 984        u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
 985        const char *msg;
 986        int cpu = smp_processor_id();
 987
 988        previous_current = curr_task(cpu);
 989        set_curr_task(cpu, current);
 990        if ((p = strchr(current->comm, ' ')))
 991                *p = '\0';
 992
 993        /* Best effort attempt to cope with MCA/INIT delivered while in
 994         * physical mode.
 995         */
 996        regs->cr_ipsr = ms->pmsa_ipsr;
 997        if (ia64_psr(regs)->dt == 0) {
 998                va.l = r12;
 999                if (va.f.reg == 0) {
1000                        va.f.reg = 7;
1001                        r12 = va.l;
1002                }
1003                va.l = r13;
1004                if (va.f.reg == 0) {
1005                        va.f.reg = 7;
1006                        r13 = va.l;
1007                }
1008        }
1009        if (ia64_psr(regs)->rt == 0) {
1010                va.l = ar_bspstore;
1011                if (va.f.reg == 0) {
1012                        va.f.reg = 7;
1013                        ar_bspstore = va.l;
1014                }
1015                va.l = ar_bsp;
1016                if (va.f.reg == 0) {
1017                        va.f.reg = 7;
1018                        ar_bsp = va.l;
1019                }
1020        }
1021
1022        /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
1023         * have been copied to the old stack, the old stack may fail the
1024         * validation tests below.  So ia64_old_stack() must restore the dirty
1025         * registers from the new stack.  The old and new bspstore probably
1026         * have different alignments, so loadrs calculated on the old bsp
1027         * cannot be used to restore from the new bsp.  Calculate a suitable
1028         * loadrs for the new stack and save it in the new pt_regs, where
1029         * ia64_old_stack() can get it.
1030         */
1031        old_bspstore = (unsigned long *)ar_bspstore;
1032        old_bsp = (unsigned long *)ar_bsp;
1033        slots = ia64_rse_num_regs(old_bspstore, old_bsp);
1034        new_bspstore = (unsigned long *)((u64)current + IA64_RBS_OFFSET);
1035        new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
1036        regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
1037
1038        /* Verify the previous stack state before we change it */
1039        if (user_mode(regs)) {
1040                msg = "occurred in user space";
1041                /* previous_current is guaranteed to be valid when the task was
1042                 * in user space, so ...
1043                 */
1044                ia64_mca_modify_comm(previous_current);
1045                goto no_mod;
1046        }
1047
1048        if (r13 != sos->prev_IA64_KR_CURRENT) {
1049                msg = "inconsistent previous current and r13";
1050                goto no_mod;
1051        }
1052
1053        if (!mca_recover_range(ms->pmsa_iip)) {
1054                if ((r12 - r13) >= KERNEL_STACK_SIZE) {
1055                        msg = "inconsistent r12 and r13";
1056                        goto no_mod;
1057                }
1058                if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
1059                        msg = "inconsistent ar.bspstore and r13";
1060                        goto no_mod;
1061                }
1062                va.p = old_bspstore;
1063                if (va.f.reg < 5) {
1064                        msg = "old_bspstore is in the wrong region";
1065                        goto no_mod;
1066                }
1067                if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
1068                        msg = "inconsistent ar.bsp and r13";
1069                        goto no_mod;
1070                }
1071                size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1072                if (ar_bspstore + size > r12) {
1073                        msg = "no room for blocked state";
1074                        goto no_mod;
1075                }
1076        }
1077
1078        ia64_mca_modify_comm(previous_current);
1079
1080        /* Make the original task look blocked.  First stack a struct pt_regs,
1081         * describing the state at the time of interrupt.  mca_asm.S built a
1082         * partial pt_regs, copy it and fill in the blanks using minstate.
1083         */
1084        p = (char *)r12 - sizeof(*regs);
1085        old_regs = (struct pt_regs *)p;
1086        memcpy(old_regs, regs, sizeof(*regs));
1087        old_regs->loadrs = loadrs;
1088        old_unat = old_regs->ar_unat;
1089        finish_pt_regs(old_regs, sos, &old_unat);
1090
1091        /* Next stack a struct switch_stack.  mca_asm.S built a partial
1092         * switch_stack, copy it and fill in the blanks using pt_regs and
1093         * minstate.
1094         *
1095         * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1096         * ar.pfs is set to 0.
1097         *
1098         * unwind.c::unw_unwind() does special processing for interrupt frames.
1099         * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1100         * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
1101         * that this is documented, of course.  Set PRED_NON_SYSCALL in the
1102         * switch_stack on the original stack so it will unwind correctly when
1103         * unwind.c reads pt_regs.
1104         *
1105         * thread.ksp is updated to point to the synthesized switch_stack.
1106         */
1107        p -= sizeof(struct switch_stack);
1108        old_sw = (struct switch_stack *)p;
1109        memcpy(old_sw, sw, sizeof(*sw));
1110        old_sw->caller_unat = old_unat;
1111        old_sw->ar_fpsr = old_regs->ar_fpsr;
1112        copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1113        copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1114        copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1115        copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1116        old_sw->b0 = (u64)ia64_leave_kernel;
1117        old_sw->b1 = ms->pmsa_br1;
1118        old_sw->ar_pfs = 0;
1119        old_sw->ar_unat = old_unat;
1120        old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1121        previous_current->thread.ksp = (u64)p - 16;
1122
1123        /* Finally copy the original stack's registers back to its RBS.
1124         * Registers from ar.bspstore through ar.bsp at the time of the event
1125         * are in the current RBS, copy them back to the original stack.  The
1126         * copy must be done register by register because the original bspstore
1127         * and the current one have different alignments, so the saved RNAT
1128         * data occurs at different places.
1129         *
1130         * mca_asm does cover, so the old_bsp already includes all registers at
1131         * the time of MCA/INIT.  It also does flushrs, so all registers before
1132         * this function have been written to backing store on the MCA/INIT
1133         * stack.
1134         */
1135        new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1136        old_rnat = regs->ar_rnat;
1137        while (slots--) {
1138                if (ia64_rse_is_rnat_slot(new_bspstore)) {
1139                        new_rnat = ia64_get_rnat(new_bspstore++);
1140                }
1141                if (ia64_rse_is_rnat_slot(old_bspstore)) {
1142                        *old_bspstore++ = old_rnat;
1143                        old_rnat = 0;
1144                }
1145                nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1146                old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1147                old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1148                *old_bspstore++ = *new_bspstore++;
1149        }
1150        old_sw->ar_bspstore = (unsigned long)old_bspstore;
1151        old_sw->ar_rnat = old_rnat;
1152
1153        sos->prev_task = previous_current;
1154        return previous_current;
1155
1156no_mod:
1157        mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1158                        smp_processor_id(), type, msg);
1159        old_unat = regs->ar_unat;
1160        finish_pt_regs(regs, sos, &old_unat);
1161        return previous_current;
1162}
1163
1164/* The monarch/slave interaction is based on monarch_cpu and requires that all
1165 * slaves have entered rendezvous before the monarch leaves.  If any cpu has
1166 * not entered rendezvous yet then wait a bit.  The assumption is that any
1167 * slave that has not rendezvoused after a reasonable time is never going to do
1168 * so.  In this context, slave includes cpus that respond to the MCA rendezvous
1169 * interrupt, as well as cpus that receive the INIT slave event.
1170 */
1171
1172static void
1173ia64_wait_for_slaves(int monarch, const char *type)
1174{
1175        int c, i , wait;
1176
1177        /*
1178         * wait 5 seconds total for slaves (arbitrary)
1179         */
1180        for (i = 0; i < 5000; i++) {
1181                wait = 0;
1182                for_each_online_cpu(c) {
1183                        if (c == monarch)
1184                                continue;
1185                        if (ia64_mc_info.imi_rendez_checkin[c]
1186                                        == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1187                                udelay(1000);           /* short wait */
1188                                wait = 1;
1189                                break;
1190                        }
1191                }
1192                if (!wait)
1193                        goto all_in;
1194        }
1195
1196        /*
1197         * Maybe slave(s) dead. Print buffered messages immediately.
1198         */
1199        ia64_mlogbuf_finish(0);
1200        mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1201        for_each_online_cpu(c) {
1202                if (c == monarch)
1203                        continue;
1204                if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1205                        mprintk(" %d", c);
1206        }
1207        mprintk("\n");
1208        return;
1209
1210all_in:
1211        mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1212        return;
1213}
1214
1215/*  mca_insert_tr
1216 *
1217 *  Switch rid when TR reload and needed!
1218 *  iord: 1: itr, 2: itr;
1219 *
1220*/
1221static void mca_insert_tr(u64 iord)
1222{
1223
1224        int i;
1225        u64 old_rr;
1226        struct ia64_tr_entry *p;
1227        unsigned long psr;
1228        int cpu = smp_processor_id();
1229
1230        if (!ia64_idtrs[cpu])
1231                return;
1232
1233        psr = ia64_clear_ic();
1234        for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1235                p = ia64_idtrs[cpu] + (iord - 1) * IA64_TR_ALLOC_MAX;
1236                if (p->pte & 0x1) {
1237                        old_rr = ia64_get_rr(p->ifa);
1238                        if (old_rr != p->rr) {
1239                                ia64_set_rr(p->ifa, p->rr);
1240                                ia64_srlz_d();
1241                        }
1242                        ia64_ptr(iord, p->ifa, p->itir >> 2);
1243                        ia64_srlz_i();
1244                        if (iord & 0x1) {
1245                                ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1246                                ia64_srlz_i();
1247                        }
1248                        if (iord & 0x2) {
1249                                ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1250                                ia64_srlz_i();
1251                        }
1252                        if (old_rr != p->rr) {
1253                                ia64_set_rr(p->ifa, old_rr);
1254                                ia64_srlz_d();
1255                        }
1256                }
1257        }
1258        ia64_set_psr(psr);
1259}
1260
1261/*
1262 * ia64_mca_handler
1263 *
1264 *      This is uncorrectable machine check handler called from OS_MCA
1265 *      dispatch code which is in turn called from SAL_CHECK().
1266 *      This is the place where the core of OS MCA handling is done.
1267 *      Right now the logs are extracted and displayed in a well-defined
1268 *      format. This handler code is supposed to be run only on the
1269 *      monarch processor. Once the monarch is done with MCA handling
1270 *      further MCA logging is enabled by clearing logs.
1271 *      Monarch also has the duty of sending wakeup-IPIs to pull the
1272 *      slave processors out of rendezvous spinloop.
1273 *
1274 *      If multiple processors call into OS_MCA, the first will become
1275 *      the monarch.  Subsequent cpus will be recorded in the mca_cpu
1276 *      bitmask.  After the first monarch has processed its MCA, it
1277 *      will wake up the next cpu in the mca_cpu bitmask and then go
1278 *      into the rendezvous loop.  When all processors have serviced
1279 *      their MCA, the last monarch frees up the rest of the processors.
1280 */
1281void
1282ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1283                 struct ia64_sal_os_state *sos)
1284{
1285        int recover, cpu = smp_processor_id();
1286        struct task_struct *previous_current;
1287        struct ia64_mca_notify_die nd =
1288                { .sos = sos, .monarch_cpu = &monarch_cpu, .data = &recover };
1289        static atomic_t mca_count;
1290        static cpumask_t mca_cpu;
1291
1292        if (atomic_add_return(1, &mca_count) == 1) {
1293                monarch_cpu = cpu;
1294                sos->monarch = 1;
1295        } else {
1296                cpumask_set_cpu(cpu, &mca_cpu);
1297                sos->monarch = 0;
1298        }
1299        mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1300                "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1301
1302        previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1303
1304        NOTIFY_MCA(DIE_MCA_MONARCH_ENTER, regs, (long)&nd, 1);
1305
1306        ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1307        if (sos->monarch) {
1308                ia64_wait_for_slaves(cpu, "MCA");
1309
1310                /* Wakeup all the processors which are spinning in the
1311                 * rendezvous loop.  They will leave SAL, then spin in the OS
1312                 * with interrupts disabled until this monarch cpu leaves the
1313                 * MCA handler.  That gets control back to the OS so we can
1314                 * backtrace the other cpus, backtrace when spinning in SAL
1315                 * does not work.
1316                 */
1317                ia64_mca_wakeup_all();
1318        } else {
1319                while (cpumask_test_cpu(cpu, &mca_cpu))
1320                        cpu_relax();    /* spin until monarch wakes us */
1321        }
1322
1323        NOTIFY_MCA(DIE_MCA_MONARCH_PROCESS, regs, (long)&nd, 1);
1324
1325        /* Get the MCA error record and log it */
1326        ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1327
1328        /* MCA error recovery */
1329        recover = (ia64_mca_ucmc_extension
1330                && ia64_mca_ucmc_extension(
1331                        IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1332                        sos));
1333
1334        if (recover) {
1335                sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1336                rh->severity = sal_log_severity_corrected;
1337                ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1338                sos->os_status = IA64_MCA_CORRECTED;
1339        } else {
1340                /* Dump buffered message to console */
1341                ia64_mlogbuf_finish(1);
1342        }
1343
1344        if (__this_cpu_read(ia64_mca_tr_reload)) {
1345                mca_insert_tr(0x1); /*Reload dynamic itrs*/
1346                mca_insert_tr(0x2); /*Reload dynamic itrs*/
1347        }
1348
1349        NOTIFY_MCA(DIE_MCA_MONARCH_LEAVE, regs, (long)&nd, 1);
1350
1351        if (atomic_dec_return(&mca_count) > 0) {
1352                int i;
1353
1354                /* wake up the next monarch cpu,
1355                 * and put this cpu in the rendez loop.
1356                 */
1357                for_each_online_cpu(i) {
1358                        if (cpumask_test_cpu(i, &mca_cpu)) {
1359                                monarch_cpu = i;
1360                                cpumask_clear_cpu(i, &mca_cpu); /* wake next cpu */
1361                                while (monarch_cpu != -1)
1362                                        cpu_relax();    /* spin until last cpu leaves */
1363                                set_curr_task(cpu, previous_current);
1364                                ia64_mc_info.imi_rendez_checkin[cpu]
1365                                                = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1366                                return;
1367                        }
1368                }
1369        }
1370        set_curr_task(cpu, previous_current);
1371        ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1372        monarch_cpu = -1;       /* This frees the slaves and previous monarchs */
1373}
1374
1375static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1376static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1377
1378/*
1379 * ia64_mca_cmc_int_handler
1380 *
1381 *  This is corrected machine check interrupt handler.
1382 *      Right now the logs are extracted and displayed in a well-defined
1383 *      format.
1384 *
1385 * Inputs
1386 *      interrupt number
1387 *      client data arg ptr
1388 *
1389 * Outputs
1390 *      None
1391 */
1392static irqreturn_t
1393ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1394{
1395        static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1396        static int              index;
1397        static DEFINE_SPINLOCK(cmc_history_lock);
1398
1399        IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1400                       __func__, cmc_irq, smp_processor_id());
1401
1402        /* SAL spec states this should run w/ interrupts enabled */
1403        local_irq_enable();
1404
1405        spin_lock(&cmc_history_lock);
1406        if (!cmc_polling_enabled) {
1407                int i, count = 1; /* we know 1 happened now */
1408                unsigned long now = jiffies;
1409
1410                for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1411                        if (now - cmc_history[i] <= HZ)
1412                                count++;
1413                }
1414
1415                IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1416                if (count >= CMC_HISTORY_LENGTH) {
1417
1418                        cmc_polling_enabled = 1;
1419                        spin_unlock(&cmc_history_lock);
1420                        /* If we're being hit with CMC interrupts, we won't
1421                         * ever execute the schedule_work() below.  Need to
1422                         * disable CMC interrupts on this processor now.
1423                         */
1424                        ia64_mca_cmc_vector_disable(NULL);
1425                        schedule_work(&cmc_disable_work);
1426
1427                        /*
1428                         * Corrected errors will still be corrected, but
1429                         * make sure there's a log somewhere that indicates
1430                         * something is generating more than we can handle.
1431                         */
1432                        printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1433
1434                        mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1435
1436                        /* lock already released, get out now */
1437                        goto out;
1438                } else {
1439                        cmc_history[index++] = now;
1440                        if (index == CMC_HISTORY_LENGTH)
1441                                index = 0;
1442                }
1443        }
1444        spin_unlock(&cmc_history_lock);
1445out:
1446        /* Get the CMC error record and log it */
1447        ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1448
1449        local_irq_disable();
1450
1451        return IRQ_HANDLED;
1452}
1453
1454/*
1455 *  ia64_mca_cmc_int_caller
1456 *
1457 *      Triggered by sw interrupt from CMC polling routine.  Calls
1458 *      real interrupt handler and either triggers a sw interrupt
1459 *      on the next cpu or does cleanup at the end.
1460 *
1461 * Inputs
1462 *      interrupt number
1463 *      client data arg ptr
1464 * Outputs
1465 *      handled
1466 */
1467static irqreturn_t
1468ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1469{
1470        static int start_count = -1;
1471        unsigned int cpuid;
1472
1473        cpuid = smp_processor_id();
1474
1475        /* If first cpu, update count */
1476        if (start_count == -1)
1477                start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1478
1479        ia64_mca_cmc_int_handler(cmc_irq, arg);
1480
1481        cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1482
1483        if (cpuid < nr_cpu_ids) {
1484                platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1485        } else {
1486                /* If no log record, switch out of polling mode */
1487                if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1488
1489                        printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1490                        schedule_work(&cmc_enable_work);
1491                        cmc_polling_enabled = 0;
1492
1493                } else {
1494
1495                        mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1496                }
1497
1498                start_count = -1;
1499        }
1500
1501        return IRQ_HANDLED;
1502}
1503
1504/*
1505 *  ia64_mca_cmc_poll
1506 *
1507 *      Poll for Corrected Machine Checks (CMCs)
1508 *
1509 * Inputs   :   dummy(unused)
1510 * Outputs  :   None
1511 *
1512 */
1513static void
1514ia64_mca_cmc_poll (unsigned long dummy)
1515{
1516        /* Trigger a CMC interrupt cascade  */
1517        platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CMCP_VECTOR,
1518                                                        IA64_IPI_DM_INT, 0);
1519}
1520
1521/*
1522 *  ia64_mca_cpe_int_caller
1523 *
1524 *      Triggered by sw interrupt from CPE polling routine.  Calls
1525 *      real interrupt handler and either triggers a sw interrupt
1526 *      on the next cpu or does cleanup at the end.
1527 *
1528 * Inputs
1529 *      interrupt number
1530 *      client data arg ptr
1531 * Outputs
1532 *      handled
1533 */
1534#ifdef CONFIG_ACPI
1535
1536static irqreturn_t
1537ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1538{
1539        static int start_count = -1;
1540        static int poll_time = MIN_CPE_POLL_INTERVAL;
1541        unsigned int cpuid;
1542
1543        cpuid = smp_processor_id();
1544
1545        /* If first cpu, update count */
1546        if (start_count == -1)
1547                start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1548
1549        ia64_mca_cpe_int_handler(cpe_irq, arg);
1550
1551        cpuid = cpumask_next(cpuid+1, cpu_online_mask);
1552
1553        if (cpuid < NR_CPUS) {
1554                platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1555        } else {
1556                /*
1557                 * If a log was recorded, increase our polling frequency,
1558                 * otherwise, backoff or return to interrupt mode.
1559                 */
1560                if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1561                        poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1562                } else if (cpe_vector < 0) {
1563                        poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1564                } else {
1565                        poll_time = MIN_CPE_POLL_INTERVAL;
1566
1567                        printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1568                        enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1569                        cpe_poll_enabled = 0;
1570                }
1571
1572                if (cpe_poll_enabled)
1573                        mod_timer(&cpe_poll_timer, jiffies + poll_time);
1574                start_count = -1;
1575        }
1576
1577        return IRQ_HANDLED;
1578}
1579
1580/*
1581 *  ia64_mca_cpe_poll
1582 *
1583 *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1584 *      on first cpu, from there it will trickle through all the cpus.
1585 *
1586 * Inputs   :   dummy(unused)
1587 * Outputs  :   None
1588 *
1589 */
1590static void
1591ia64_mca_cpe_poll (unsigned long dummy)
1592{
1593        /* Trigger a CPE interrupt cascade  */
1594        platform_send_ipi(cpumask_first(cpu_online_mask), IA64_CPEP_VECTOR,
1595                                                        IA64_IPI_DM_INT, 0);
1596}
1597
1598#endif /* CONFIG_ACPI */
1599
1600static int
1601default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1602{
1603        int c;
1604        struct task_struct *g, *t;
1605        if (val != DIE_INIT_MONARCH_PROCESS)
1606                return NOTIFY_DONE;
1607#ifdef CONFIG_KEXEC
1608        if (atomic_read(&kdump_in_progress))
1609                return NOTIFY_DONE;
1610#endif
1611
1612        /*
1613         * FIXME: mlogbuf will brim over with INIT stack dumps.
1614         * To enable show_stack from INIT, we use oops_in_progress which should
1615         * be used in real oops. This would cause something wrong after INIT.
1616         */
1617        BREAK_LOGLEVEL(console_loglevel);
1618        ia64_mlogbuf_dump_from_init();
1619
1620        printk(KERN_ERR "Processes interrupted by INIT -");
1621        for_each_online_cpu(c) {
1622                struct ia64_sal_os_state *s;
1623                t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1624                s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1625                g = s->prev_task;
1626                if (g) {
1627                        if (g->pid)
1628                                printk(" %d", g->pid);
1629                        else
1630                                printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1631                }
1632        }
1633        printk("\n\n");
1634        if (read_trylock(&tasklist_lock)) {
1635                do_each_thread (g, t) {
1636                        printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1637                        show_stack(t, NULL);
1638                } while_each_thread (g, t);
1639                read_unlock(&tasklist_lock);
1640        }
1641        /* FIXME: This will not restore zapped printk locks. */
1642        RESTORE_LOGLEVEL(console_loglevel);
1643        return NOTIFY_DONE;
1644}
1645
1646/*
1647 * C portion of the OS INIT handler
1648 *
1649 * Called from ia64_os_init_dispatch
1650 *
1651 * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1652 * this event.  This code is used for both monarch and slave INIT events, see
1653 * sos->monarch.
1654 *
1655 * All INIT events switch to the INIT stack and change the previous process to
1656 * blocked status.  If one of the INIT events is the monarch then we are
1657 * probably processing the nmi button/command.  Use the monarch cpu to dump all
1658 * the processes.  The slave INIT events all spin until the monarch cpu
1659 * returns.  We can also get INIT slave events for MCA, in which case the MCA
1660 * process is the monarch.
1661 */
1662
1663void
1664ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1665                  struct ia64_sal_os_state *sos)
1666{
1667        static atomic_t slaves;
1668        static atomic_t monarchs;
1669        struct task_struct *previous_current;
1670        int cpu = smp_processor_id();
1671        struct ia64_mca_notify_die nd =
1672                { .sos = sos, .monarch_cpu = &monarch_cpu };
1673
1674        NOTIFY_INIT(DIE_INIT_ENTER, regs, (long)&nd, 0);
1675
1676        mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1677                sos->proc_state_param, cpu, sos->monarch);
1678        salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1679
1680        previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1681        sos->os_status = IA64_INIT_RESUME;
1682
1683        /* FIXME: Workaround for broken proms that drive all INIT events as
1684         * slaves.  The last slave that enters is promoted to be a monarch.
1685         * Remove this code in September 2006, that gives platforms a year to
1686         * fix their proms and get their customers updated.
1687         */
1688        if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1689                mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1690                        __func__, cpu);
1691                atomic_dec(&slaves);
1692                sos->monarch = 1;
1693        }
1694
1695        /* FIXME: Workaround for broken proms that drive all INIT events as
1696         * monarchs.  Second and subsequent monarchs are demoted to slaves.
1697         * Remove this code in September 2006, that gives platforms a year to
1698         * fix their proms and get their customers updated.
1699         */
1700        if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1701                mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1702                               __func__, cpu);
1703                atomic_dec(&monarchs);
1704                sos->monarch = 0;
1705        }
1706
1707        if (!sos->monarch) {
1708                ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1709
1710#ifdef CONFIG_KEXEC
1711                while (monarch_cpu == -1 && !atomic_read(&kdump_in_progress))
1712                        udelay(1000);
1713#else
1714                while (monarch_cpu == -1)
1715                        cpu_relax();    /* spin until monarch enters */
1716#endif
1717
1718                NOTIFY_INIT(DIE_INIT_SLAVE_ENTER, regs, (long)&nd, 1);
1719                NOTIFY_INIT(DIE_INIT_SLAVE_PROCESS, regs, (long)&nd, 1);
1720
1721#ifdef CONFIG_KEXEC
1722                while (monarch_cpu != -1 && !atomic_read(&kdump_in_progress))
1723                        udelay(1000);
1724#else
1725                while (monarch_cpu != -1)
1726                        cpu_relax();    /* spin until monarch leaves */
1727#endif
1728
1729                NOTIFY_INIT(DIE_INIT_SLAVE_LEAVE, regs, (long)&nd, 1);
1730
1731                mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1732                set_curr_task(cpu, previous_current);
1733                ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1734                atomic_dec(&slaves);
1735                return;
1736        }
1737
1738        monarch_cpu = cpu;
1739        NOTIFY_INIT(DIE_INIT_MONARCH_ENTER, regs, (long)&nd, 1);
1740
1741        /*
1742         * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1743         * generated via the BMC's command-line interface, but since the console is on the
1744         * same serial line, the user will need some time to switch out of the BMC before
1745         * the dump begins.
1746         */
1747        mprintk("Delaying for 5 seconds...\n");
1748        udelay(5*1000000);
1749        ia64_wait_for_slaves(cpu, "INIT");
1750        /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1751         * to default_monarch_init_process() above and just print all the
1752         * tasks.
1753         */
1754        NOTIFY_INIT(DIE_INIT_MONARCH_PROCESS, regs, (long)&nd, 1);
1755        NOTIFY_INIT(DIE_INIT_MONARCH_LEAVE, regs, (long)&nd, 1);
1756
1757        mprintk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1758        atomic_dec(&monarchs);
1759        set_curr_task(cpu, previous_current);
1760        monarch_cpu = -1;
1761        return;
1762}
1763
1764static int __init
1765ia64_mca_disable_cpe_polling(char *str)
1766{
1767        cpe_poll_enabled = 0;
1768        return 1;
1769}
1770
1771__setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1772
1773static struct irqaction cmci_irqaction = {
1774        .handler =      ia64_mca_cmc_int_handler,
1775        .name =         "cmc_hndlr"
1776};
1777
1778static struct irqaction cmcp_irqaction = {
1779        .handler =      ia64_mca_cmc_int_caller,
1780        .name =         "cmc_poll"
1781};
1782
1783static struct irqaction mca_rdzv_irqaction = {
1784        .handler =      ia64_mca_rendez_int_handler,
1785        .name =         "mca_rdzv"
1786};
1787
1788static struct irqaction mca_wkup_irqaction = {
1789        .handler =      ia64_mca_wakeup_int_handler,
1790        .name =         "mca_wkup"
1791};
1792
1793#ifdef CONFIG_ACPI
1794static struct irqaction mca_cpe_irqaction = {
1795        .handler =      ia64_mca_cpe_int_handler,
1796        .name =         "cpe_hndlr"
1797};
1798
1799static struct irqaction mca_cpep_irqaction = {
1800        .handler =      ia64_mca_cpe_int_caller,
1801        .name =         "cpe_poll"
1802};
1803#endif /* CONFIG_ACPI */
1804
1805/* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1806 * these stacks can never sleep, they cannot return from the kernel to user
1807 * space, they do not appear in a normal ps listing.  So there is no need to
1808 * format most of the fields.
1809 */
1810
1811static void
1812format_mca_init_stack(void *mca_data, unsigned long offset,
1813                const char *type, int cpu)
1814{
1815        struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1816        struct thread_info *ti;
1817        memset(p, 0, KERNEL_STACK_SIZE);
1818        ti = task_thread_info(p);
1819        ti->flags = _TIF_MCA_INIT;
1820        ti->preempt_count = 1;
1821        ti->task = p;
1822        ti->cpu = cpu;
1823        p->stack = ti;
1824        p->state = TASK_UNINTERRUPTIBLE;
1825        cpumask_set_cpu(cpu, &p->cpus_allowed);
1826        INIT_LIST_HEAD(&p->tasks);
1827        p->parent = p->real_parent = p->group_leader = p;
1828        INIT_LIST_HEAD(&p->children);
1829        INIT_LIST_HEAD(&p->sibling);
1830        strncpy(p->comm, type, sizeof(p->comm)-1);
1831}
1832
1833/* Caller prevents this from being called after init */
1834static void * __init_refok mca_bootmem(void)
1835{
1836        return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
1837                            KERNEL_STACK_SIZE, 0);
1838}
1839
1840/* Do per-CPU MCA-related initialization.  */
1841void
1842ia64_mca_cpu_init(void *cpu_data)
1843{
1844        void *pal_vaddr;
1845        void *data;
1846        long sz = sizeof(struct ia64_mca_cpu);
1847        int cpu = smp_processor_id();
1848        static int first_time = 1;
1849
1850        /*
1851         * Structure will already be allocated if cpu has been online,
1852         * then offlined.
1853         */
1854        if (__per_cpu_mca[cpu]) {
1855                data = __va(__per_cpu_mca[cpu]);
1856        } else {
1857                if (first_time) {
1858                        data = mca_bootmem();
1859                        first_time = 0;
1860                } else
1861                        data = (void *)__get_free_pages(GFP_KERNEL,
1862                                                        get_order(sz));
1863                if (!data)
1864                        panic("Could not allocate MCA memory for cpu %d\n",
1865                                        cpu);
1866        }
1867        format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1868                "MCA", cpu);
1869        format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1870                "INIT", cpu);
1871        __this_cpu_write(ia64_mca_data, (__per_cpu_mca[cpu] = __pa(data)));
1872
1873        /*
1874         * Stash away a copy of the PTE needed to map the per-CPU page.
1875         * We may need it during MCA recovery.
1876         */
1877        __this_cpu_write(ia64_mca_per_cpu_pte,
1878                pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL)));
1879
1880        /*
1881         * Also, stash away a copy of the PAL address and the PTE
1882         * needed to map it.
1883         */
1884        pal_vaddr = efi_get_pal_addr();
1885        if (!pal_vaddr)
1886                return;
1887        __this_cpu_write(ia64_mca_pal_base,
1888                GRANULEROUNDDOWN((unsigned long) pal_vaddr));
1889        __this_cpu_write(ia64_mca_pal_pte, pte_val(mk_pte_phys(__pa(pal_vaddr),
1890                                                              PAGE_KERNEL)));
1891}
1892
1893static void ia64_mca_cmc_vector_adjust(void *dummy)
1894{
1895        unsigned long flags;
1896
1897        local_irq_save(flags);
1898        if (!cmc_polling_enabled)
1899                ia64_mca_cmc_vector_enable(NULL);
1900        local_irq_restore(flags);
1901}
1902
1903static int mca_cpu_callback(struct notifier_block *nfb,
1904                                      unsigned long action,
1905                                      void *hcpu)
1906{
1907        int hotcpu = (unsigned long) hcpu;
1908
1909        switch (action) {
1910        case CPU_ONLINE:
1911        case CPU_ONLINE_FROZEN:
1912                smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust,
1913                                         NULL, 0);
1914                break;
1915        }
1916        return NOTIFY_OK;
1917}
1918
1919static struct notifier_block mca_cpu_notifier = {
1920        .notifier_call = mca_cpu_callback
1921};
1922
1923/*
1924 * ia64_mca_init
1925 *
1926 *  Do all the system level mca specific initialization.
1927 *
1928 *      1. Register spinloop and wakeup request interrupt vectors
1929 *
1930 *      2. Register OS_MCA handler entry point
1931 *
1932 *      3. Register OS_INIT handler entry point
1933 *
1934 *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1935 *
1936 *  Note that this initialization is done very early before some kernel
1937 *  services are available.
1938 *
1939 *  Inputs  :   None
1940 *
1941 *  Outputs :   None
1942 */
1943void __init
1944ia64_mca_init(void)
1945{
1946        ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1947        ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1948        ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1949        int i;
1950        long rc;
1951        struct ia64_sal_retval isrv;
1952        unsigned long timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1953        static struct notifier_block default_init_monarch_nb = {
1954                .notifier_call = default_monarch_init_process,
1955                .priority = 0/* we need to notified last */
1956        };
1957
1958        IA64_MCA_DEBUG("%s: begin\n", __func__);
1959
1960        /* Clear the Rendez checkin flag for all cpus */
1961        for(i = 0 ; i < NR_CPUS; i++)
1962                ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1963
1964        /*
1965         * Register the rendezvous spinloop and wakeup mechanism with SAL
1966         */
1967
1968        /* Register the rendezvous interrupt vector with SAL */
1969        while (1) {
1970                isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1971                                              SAL_MC_PARAM_MECHANISM_INT,
1972                                              IA64_MCA_RENDEZ_VECTOR,
1973                                              timeout,
1974                                              SAL_MC_PARAM_RZ_ALWAYS);
1975                rc = isrv.status;
1976                if (rc == 0)
1977                        break;
1978                if (rc == -2) {
1979                        printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1980                                "%ld to %ld milliseconds\n", timeout, isrv.v0);
1981                        timeout = isrv.v0;
1982                        NOTIFY_MCA(DIE_MCA_NEW_TIMEOUT, NULL, timeout, 0);
1983                        continue;
1984                }
1985                printk(KERN_ERR "Failed to register rendezvous interrupt "
1986                       "with SAL (status %ld)\n", rc);
1987                return;
1988        }
1989
1990        /* Register the wakeup interrupt vector with SAL */
1991        isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1992                                      SAL_MC_PARAM_MECHANISM_INT,
1993                                      IA64_MCA_WAKEUP_VECTOR,
1994                                      0, 0);
1995        rc = isrv.status;
1996        if (rc) {
1997                printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1998                       "(status %ld)\n", rc);
1999                return;
2000        }
2001
2002        IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
2003
2004        ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
2005        /*
2006         * XXX - disable SAL checksum by setting size to 0; should be
2007         *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
2008         */
2009        ia64_mc_info.imi_mca_handler_size       = 0;
2010
2011        /* Register the os mca handler with SAL */
2012        if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
2013                                       ia64_mc_info.imi_mca_handler,
2014                                       ia64_tpa(mca_hldlr_ptr->gp),
2015                                       ia64_mc_info.imi_mca_handler_size,
2016                                       0, 0, 0)))
2017        {
2018                printk(KERN_ERR "Failed to register OS MCA handler with SAL "
2019                       "(status %ld)\n", rc);
2020                return;
2021        }
2022
2023        IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
2024                       ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
2025
2026        /*
2027         * XXX - disable SAL checksum by setting size to 0, should be
2028         * size of the actual init handler in mca_asm.S.
2029         */
2030        ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
2031        ia64_mc_info.imi_monarch_init_handler_size      = 0;
2032        ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
2033        ia64_mc_info.imi_slave_init_handler_size        = 0;
2034
2035        IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
2036                       ia64_mc_info.imi_monarch_init_handler);
2037
2038        /* Register the os init handler with SAL */
2039        if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
2040                                       ia64_mc_info.imi_monarch_init_handler,
2041                                       ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2042                                       ia64_mc_info.imi_monarch_init_handler_size,
2043                                       ia64_mc_info.imi_slave_init_handler,
2044                                       ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2045                                       ia64_mc_info.imi_slave_init_handler_size)))
2046        {
2047                printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
2048                       "(status %ld)\n", rc);
2049                return;
2050        }
2051        if (register_die_notifier(&default_init_monarch_nb)) {
2052                printk(KERN_ERR "Failed to register default monarch INIT process\n");
2053                return;
2054        }
2055
2056        IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2057
2058        /* Initialize the areas set aside by the OS to buffer the
2059         * platform/processor error states for MCA/INIT/CMC
2060         * handling.
2061         */
2062        ia64_log_init(SAL_INFO_TYPE_MCA);
2063        ia64_log_init(SAL_INFO_TYPE_INIT);
2064        ia64_log_init(SAL_INFO_TYPE_CMC);
2065        ia64_log_init(SAL_INFO_TYPE_CPE);
2066
2067        mca_init = 1;
2068        printk(KERN_INFO "MCA related initialization done\n");
2069}
2070
2071
2072/*
2073 * These pieces cannot be done in ia64_mca_init() because it is called before
2074 * early_irq_init() which would wipe out our percpu irq registrations. But we
2075 * cannot leave them until ia64_mca_late_init() because by then all the other
2076 * processors have been brought online and have set their own CMC vectors to
2077 * point at a non-existant action. Called from arch_early_irq_init().
2078 */
2079void __init ia64_mca_irq_init(void)
2080{
2081        /*
2082         *  Configure the CMCI/P vector and handler. Interrupts for CMC are
2083         *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2084         */
2085        register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
2086        register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
2087        ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
2088
2089        /* Setup the MCA rendezvous interrupt vector */
2090        register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
2091
2092        /* Setup the MCA wakeup interrupt vector */
2093        register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
2094
2095#ifdef CONFIG_ACPI
2096        /* Setup the CPEI/P handler */
2097        register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
2098#endif
2099}
2100
2101/*
2102 * ia64_mca_late_init
2103 *
2104 *      Opportunity to setup things that require initialization later
2105 *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
2106 *      platform doesn't support an interrupt driven mechanism.
2107 *
2108 *  Inputs  :   None
2109 *  Outputs :   Status
2110 */
2111static int __init
2112ia64_mca_late_init(void)
2113{
2114        if (!mca_init)
2115                return 0;
2116
2117        register_hotcpu_notifier(&mca_cpu_notifier);
2118
2119        /* Setup the CMCI/P vector and handler */
2120        init_timer(&cmc_poll_timer);
2121        cmc_poll_timer.function = ia64_mca_cmc_poll;
2122
2123        /* Unmask/enable the vector */
2124        cmc_polling_enabled = 0;
2125        schedule_work(&cmc_enable_work);
2126
2127        IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2128
2129#ifdef CONFIG_ACPI
2130        /* Setup the CPEI/P vector and handler */
2131        cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2132        init_timer(&cpe_poll_timer);
2133        cpe_poll_timer.function = ia64_mca_cpe_poll;
2134
2135        {
2136                unsigned int irq;
2137
2138                if (cpe_vector >= 0) {
2139                        /* If platform supports CPEI, enable the irq. */
2140                        irq = local_vector_to_irq(cpe_vector);
2141                        if (irq > 0) {
2142                                cpe_poll_enabled = 0;
2143                                irq_set_status_flags(irq, IRQ_PER_CPU);
2144                                setup_irq(irq, &mca_cpe_irqaction);
2145                                ia64_cpe_irq = irq;
2146                                ia64_mca_register_cpev(cpe_vector);
2147                                IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2148                                        __func__);
2149                                return 0;
2150                        }
2151                        printk(KERN_ERR "%s: Failed to find irq for CPE "
2152                                        "interrupt handler, vector %d\n",
2153                                        __func__, cpe_vector);
2154                }
2155                /* If platform doesn't support CPEI, get the timer going. */
2156                if (cpe_poll_enabled) {
2157                        ia64_mca_cpe_poll(0UL);
2158                        IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2159                }
2160        }
2161#endif
2162
2163        return 0;
2164}
2165
2166device_initcall(ia64_mca_late_init);
2167