1
2
3
4
5
6
7#include <linux/clk.h>
8#include <linux/dma-mapping.h>
9#include <linux/gpio.h>
10#include <linux/i2c.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/interrupt.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/nand.h>
16#include <linux/mtd/partitions.h>
17#include <linux/platform_device.h>
18#include <linux/pm.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/flash.h>
21#include <asm/bootinfo.h>
22#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-au1x00/au1xxx_eth.h>
24#include <asm/mach-au1x00/au1xxx_dbdma.h>
25#include <asm/mach-au1x00/au1xxx_psc.h>
26#include <asm/mach-au1x00/au1550_spi.h>
27#include <asm/mach-au1x00/au1550nd.h>
28#include <asm/mach-db1x00/bcsr.h>
29#include <prom.h>
30#include "platform.h"
31
32static void __init db1550_hw_setup(void)
33{
34 void __iomem *base;
35 unsigned long v;
36
37
38
39
40 v = alchemy_rdsys(AU1000_SYS_PINFUNC);
41 alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
42
43
44
45
46 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
47 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
48 base + PSC_SEL_OFFSET);
49 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
50 wmb();
51 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
52 wmb();
53}
54
55int __init db1550_board_setup(void)
56{
57 unsigned short whoami;
58
59 bcsr_init(DB1550_BCSR_PHYS_ADDR,
60 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
61
62 whoami = bcsr_read(BCSR_WHOAMI);
63 switch (BCSR_WHOAMI_BOARD(whoami)) {
64 case BCSR_WHOAMI_PB1550_SDR:
65 case BCSR_WHOAMI_PB1550_DDR:
66 bcsr_init(PB1550_BCSR_PHYS_ADDR,
67 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
68 case BCSR_WHOAMI_DB1550:
69 break;
70 default:
71 return -ENODEV;
72 }
73
74 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
75 "Daughtercard ID %d\n", get_system_type(),
76 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
77
78 db1550_hw_setup();
79 return 0;
80}
81
82
83
84static struct mtd_partition db1550_spiflash_parts[] = {
85 {
86 .name = "spi_flash",
87 .offset = 0,
88 .size = MTDPART_SIZ_FULL,
89 },
90};
91
92static struct flash_platform_data db1550_spiflash_data = {
93 .name = "s25fl010",
94 .parts = db1550_spiflash_parts,
95 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
96 .type = "m25p10",
97};
98
99static struct spi_board_info db1550_spi_devs[] __initdata = {
100 {
101
102 .modalias = "tmp121",
103 .max_speed_hz = 2400000,
104 .bus_num = 0,
105 .chip_select = 0,
106 .mode = SPI_MODE_0,
107 },
108 {
109
110 .modalias = "m25p80",
111 .max_speed_hz = 2400000,
112 .bus_num = 0,
113 .chip_select = 1,
114 .mode = SPI_MODE_0,
115 .platform_data = &db1550_spiflash_data,
116 },
117};
118
119static struct i2c_board_info db1550_i2c_devs[] __initdata = {
120 { I2C_BOARD_INFO("24c04", 0x52),},
121 { I2C_BOARD_INFO("ne1619", 0x2d),},
122 { I2C_BOARD_INFO("wm8731", 0x1b),},
123};
124
125
126
127static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
128 unsigned int ctrl)
129{
130 struct nand_chip *this = mtd->priv;
131 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
132
133 ioaddr &= 0xffffff00;
134
135 if (ctrl & NAND_CLE) {
136 ioaddr += MEM_STNAND_CMD;
137 } else if (ctrl & NAND_ALE) {
138 ioaddr += MEM_STNAND_ADDR;
139 } else {
140
141 ioaddr += MEM_STNAND_DATA;
142 }
143 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
144 if (cmd != NAND_CMD_NONE) {
145 __raw_writeb(cmd, this->IO_ADDR_W);
146 wmb();
147 }
148}
149
150static int au1550_nand_device_ready(struct mtd_info *mtd)
151{
152 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
153}
154
155static struct mtd_partition db1550_nand_parts[] = {
156 {
157 .name = "NAND FS 0",
158 .offset = 0,
159 .size = 8 * 1024 * 1024,
160 },
161 {
162 .name = "NAND FS 1",
163 .offset = MTDPART_OFS_APPEND,
164 .size = MTDPART_SIZ_FULL
165 },
166};
167
168struct platform_nand_data db1550_nand_platdata = {
169 .chip = {
170 .nr_chips = 1,
171 .chip_offset = 0,
172 .nr_partitions = ARRAY_SIZE(db1550_nand_parts),
173 .partitions = db1550_nand_parts,
174 .chip_delay = 20,
175 },
176 .ctrl = {
177 .dev_ready = au1550_nand_device_ready,
178 .cmd_ctrl = au1550_nand_cmd_ctrl,
179 },
180};
181
182static struct resource db1550_nand_res[] = {
183 [0] = {
184 .start = 0x20000000,
185 .end = 0x200000ff,
186 .flags = IORESOURCE_MEM,
187 },
188};
189
190static struct platform_device db1550_nand_dev = {
191 .name = "gen_nand",
192 .num_resources = ARRAY_SIZE(db1550_nand_res),
193 .resource = db1550_nand_res,
194 .id = -1,
195 .dev = {
196 .platform_data = &db1550_nand_platdata,
197 }
198};
199
200static struct au1550nd_platdata pb1550_nand_pd = {
201 .parts = db1550_nand_parts,
202 .num_parts = ARRAY_SIZE(db1550_nand_parts),
203 .devwidth = 0,
204};
205
206static struct platform_device pb1550_nand_dev = {
207 .name = "au1550-nand",
208 .id = -1,
209 .resource = db1550_nand_res,
210 .num_resources = ARRAY_SIZE(db1550_nand_res),
211 .dev = {
212 .platform_data = &pb1550_nand_pd,
213 },
214};
215
216static void __init pb1550_nand_setup(void)
217{
218 int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
219 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
220
221 gpio_direction_input(206);
222 switch (boot_swapboot) {
223 case 0: case 2: case 8: case 0xC: case 0xD:
224
225 pb1550_nand_pd.devwidth = 1;
226
227 case 1: case 3: case 9: case 0xE: case 0xF:
228
229 platform_device_register(&pb1550_nand_dev);
230 }
231}
232
233
234
235static struct resource au1550_psc0_res[] = {
236 [0] = {
237 .start = AU1550_PSC0_PHYS_ADDR,
238 .end = AU1550_PSC0_PHYS_ADDR + 0xfff,
239 .flags = IORESOURCE_MEM,
240 },
241 [1] = {
242 .start = AU1550_PSC0_INT,
243 .end = AU1550_PSC0_INT,
244 .flags = IORESOURCE_IRQ,
245 },
246 [2] = {
247 .start = AU1550_DSCR_CMD0_PSC0_TX,
248 .end = AU1550_DSCR_CMD0_PSC0_TX,
249 .flags = IORESOURCE_DMA,
250 },
251 [3] = {
252 .start = AU1550_DSCR_CMD0_PSC0_RX,
253 .end = AU1550_DSCR_CMD0_PSC0_RX,
254 .flags = IORESOURCE_DMA,
255 },
256};
257
258static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
259{
260 if (cs)
261 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
262 else
263 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
264}
265
266static struct au1550_spi_info db1550_spi_platdata = {
267 .mainclk_hz = 48000000,
268 .num_chipselect = 2,
269 .activate_cs = db1550_spi_cs_en,
270};
271
272static u64 spi_dmamask = DMA_BIT_MASK(32);
273
274static struct platform_device db1550_spi_dev = {
275 .dev = {
276 .dma_mask = &spi_dmamask,
277 .coherent_dma_mask = DMA_BIT_MASK(32),
278 .platform_data = &db1550_spi_platdata,
279 },
280 .name = "au1550-spi",
281 .id = 0,
282 .num_resources = ARRAY_SIZE(au1550_psc0_res),
283 .resource = au1550_psc0_res,
284};
285
286
287
288static struct resource au1550_psc1_res[] = {
289 [0] = {
290 .start = AU1550_PSC1_PHYS_ADDR,
291 .end = AU1550_PSC1_PHYS_ADDR + 0xfff,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = AU1550_PSC1_INT,
296 .end = AU1550_PSC1_INT,
297 .flags = IORESOURCE_IRQ,
298 },
299 [2] = {
300 .start = AU1550_DSCR_CMD0_PSC1_TX,
301 .end = AU1550_DSCR_CMD0_PSC1_TX,
302 .flags = IORESOURCE_DMA,
303 },
304 [3] = {
305 .start = AU1550_DSCR_CMD0_PSC1_RX,
306 .end = AU1550_DSCR_CMD0_PSC1_RX,
307 .flags = IORESOURCE_DMA,
308 },
309};
310
311static struct platform_device db1550_ac97_dev = {
312 .name = "au1xpsc_ac97",
313 .id = 1,
314 .num_resources = ARRAY_SIZE(au1550_psc1_res),
315 .resource = au1550_psc1_res,
316};
317
318
319static struct resource au1550_psc2_res[] = {
320 [0] = {
321 .start = AU1550_PSC2_PHYS_ADDR,
322 .end = AU1550_PSC2_PHYS_ADDR + 0xfff,
323 .flags = IORESOURCE_MEM,
324 },
325 [1] = {
326 .start = AU1550_PSC2_INT,
327 .end = AU1550_PSC2_INT,
328 .flags = IORESOURCE_IRQ,
329 },
330 [2] = {
331 .start = AU1550_DSCR_CMD0_PSC2_TX,
332 .end = AU1550_DSCR_CMD0_PSC2_TX,
333 .flags = IORESOURCE_DMA,
334 },
335 [3] = {
336 .start = AU1550_DSCR_CMD0_PSC2_RX,
337 .end = AU1550_DSCR_CMD0_PSC2_RX,
338 .flags = IORESOURCE_DMA,
339 },
340};
341
342static struct platform_device db1550_i2c_dev = {
343 .name = "au1xpsc_smbus",
344 .id = 0,
345 .num_resources = ARRAY_SIZE(au1550_psc2_res),
346 .resource = au1550_psc2_res,
347};
348
349
350
351static struct resource au1550_psc3_res[] = {
352 [0] = {
353 .start = AU1550_PSC3_PHYS_ADDR,
354 .end = AU1550_PSC3_PHYS_ADDR + 0xfff,
355 .flags = IORESOURCE_MEM,
356 },
357 [1] = {
358 .start = AU1550_PSC3_INT,
359 .end = AU1550_PSC3_INT,
360 .flags = IORESOURCE_IRQ,
361 },
362 [2] = {
363 .start = AU1550_DSCR_CMD0_PSC3_TX,
364 .end = AU1550_DSCR_CMD0_PSC3_TX,
365 .flags = IORESOURCE_DMA,
366 },
367 [3] = {
368 .start = AU1550_DSCR_CMD0_PSC3_RX,
369 .end = AU1550_DSCR_CMD0_PSC3_RX,
370 .flags = IORESOURCE_DMA,
371 },
372};
373
374static struct platform_device db1550_i2s_dev = {
375 .name = "au1xpsc_i2s",
376 .id = 3,
377 .num_resources = ARRAY_SIZE(au1550_psc3_res),
378 .resource = au1550_psc3_res,
379};
380
381
382
383static struct platform_device db1550_stac_dev = {
384 .name = "ac97-codec",
385 .id = 1,
386};
387
388static struct platform_device db1550_ac97dma_dev = {
389 .name = "au1xpsc-pcm",
390 .id = 1,
391};
392
393static struct platform_device db1550_i2sdma_dev = {
394 .name = "au1xpsc-pcm",
395 .id = 3,
396};
397
398static struct platform_device db1550_sndac97_dev = {
399 .name = "db1550-ac97",
400};
401
402static struct platform_device db1550_sndi2s_dev = {
403 .name = "db1550-i2s",
404};
405
406
407
408static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
409{
410 if ((slot < 11) || (slot > 13) || pin == 0)
411 return -1;
412 if (slot == 11)
413 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
414 if (slot == 12) {
415 switch (pin) {
416 case 1: return AU1550_PCI_INTB;
417 case 2: return AU1550_PCI_INTC;
418 case 3: return AU1550_PCI_INTD;
419 case 4: return AU1550_PCI_INTA;
420 }
421 }
422 if (slot == 13) {
423 switch (pin) {
424 case 1: return AU1550_PCI_INTA;
425 case 2: return AU1550_PCI_INTB;
426 case 3: return AU1550_PCI_INTC;
427 case 4: return AU1550_PCI_INTD;
428 }
429 }
430 return -1;
431}
432
433static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
434{
435 if ((slot < 12) || (slot > 13) || pin == 0)
436 return -1;
437 if (slot == 12) {
438 switch (pin) {
439 case 1: return AU1500_PCI_INTB;
440 case 2: return AU1500_PCI_INTC;
441 case 3: return AU1500_PCI_INTD;
442 case 4: return AU1500_PCI_INTA;
443 }
444 }
445 if (slot == 13) {
446 switch (pin) {
447 case 1: return AU1500_PCI_INTA;
448 case 2: return AU1500_PCI_INTB;
449 case 3: return AU1500_PCI_INTC;
450 case 4: return AU1500_PCI_INTD;
451 }
452 }
453 return -1;
454}
455
456static struct resource alchemy_pci_host_res[] = {
457 [0] = {
458 .start = AU1500_PCI_PHYS_ADDR,
459 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
460 .flags = IORESOURCE_MEM,
461 },
462};
463
464static struct alchemy_pci_platdata db1550_pci_pd = {
465 .board_map_irq = db1550_map_pci_irq,
466};
467
468static struct platform_device db1550_pci_host_dev = {
469 .dev.platform_data = &db1550_pci_pd,
470 .name = "alchemy-pci",
471 .id = 0,
472 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
473 .resource = alchemy_pci_host_res,
474};
475
476
477
478static struct platform_device *db1550_devs[] __initdata = {
479 &db1550_i2c_dev,
480 &db1550_ac97_dev,
481 &db1550_spi_dev,
482 &db1550_i2s_dev,
483 &db1550_stac_dev,
484 &db1550_ac97dma_dev,
485 &db1550_i2sdma_dev,
486 &db1550_sndac97_dev,
487 &db1550_sndi2s_dev,
488};
489
490
491int __init db1550_pci_setup(int id)
492{
493 if (id)
494 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
495 return platform_device_register(&db1550_pci_host_dev);
496}
497
498static void __init db1550_devices(void)
499{
500 alchemy_gpio_direction_output(203, 0);
501
502 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);
503 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);
504 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);
505 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);
506 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW);
507 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW);
508
509 db1x_register_pcmcia_socket(
510 AU1000_PCMCIA_ATTR_PHYS_ADDR,
511 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
512 AU1000_PCMCIA_MEM_PHYS_ADDR,
513 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
514 AU1000_PCMCIA_IO_PHYS_ADDR,
515 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
516 AU1550_GPIO3_INT, AU1550_GPIO0_INT,
517 0, 0, 0);
518
519 db1x_register_pcmcia_socket(
520 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
521 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
522 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
523 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
524 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
525 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
526 AU1550_GPIO5_INT, AU1550_GPIO1_INT,
527 0, 0, 1);
528
529 platform_device_register(&db1550_nand_dev);
530
531 alchemy_gpio_direction_output(202, 0);
532}
533
534static void __init pb1550_devices(void)
535{
536 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
537 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
538 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
539
540
541 alchemy_gpio2_enable_int(201);
542 alchemy_gpio2_enable_int(202);
543
544
545
546
547
548
549
550
551 db1x_register_pcmcia_socket(
552 AU1000_PCMCIA_ATTR_PHYS_ADDR,
553 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
554 AU1000_PCMCIA_MEM_PHYS_ADDR,
555 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
556 AU1000_PCMCIA_IO_PHYS_ADDR,
557 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
558 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
559
560 db1x_register_pcmcia_socket(
561 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
562 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
563 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
564 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
565 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
566 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
567 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
568
569 pb1550_nand_setup();
570}
571
572int __init db1550_dev_setup(void)
573{
574 int swapped, id;
575 struct clk *c;
576
577 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
578
579 i2c_register_board_info(0, db1550_i2c_devs,
580 ARRAY_SIZE(db1550_i2c_devs));
581 spi_register_board_info(db1550_spi_devs,
582 ARRAY_SIZE(db1550_i2c_devs));
583
584 c = clk_get(NULL, "psc0_intclk");
585 if (!IS_ERR(c)) {
586 clk_set_rate(c, 50000000);
587 clk_prepare_enable(c);
588 clk_put(c);
589 }
590 c = clk_get(NULL, "psc2_intclk");
591 if (!IS_ERR(c)) {
592 clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
593 clk_prepare_enable(c);
594 clk_put(c);
595 }
596
597
598 __raw_writel(PSC_SEL_CLK_SERCLK,
599 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
600 wmb();
601 __raw_writel(PSC_SEL_CLK_SERCLK,
602 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
603 wmb();
604
605 __raw_writel(PSC_SEL_CLK_INTCLK,
606 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
607 wmb();
608 __raw_writel(PSC_SEL_CLK_INTCLK,
609 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
610 wmb();
611
612 id ? pb1550_devices() : db1550_devices();
613
614 swapped = bcsr_read(BCSR_STATUS) &
615 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
616 db1x_register_norflash(128 << 20, 4, swapped);
617
618 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
619}
620
