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12#ifndef _ASM_IO_H
13#define _ASM_IO_H
14
15#include <linux/compiler.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/irqflags.h>
19
20#include <asm/addrspace.h>
21#include <asm/bug.h>
22#include <asm/byteorder.h>
23#include <asm/cpu.h>
24#include <asm/cpu-features.h>
25#include <asm-generic/iomap.h>
26#include <asm/page.h>
27#include <asm/pgtable-bits.h>
28#include <asm/processor.h>
29#include <asm/string.h>
30
31#include <ioremap.h>
32#include <mangle-port.h>
33
34
35
36
37#undef CONF_SLOWDOWN_IO
38
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43
44
45# define __raw_ioswabb(a, x) (x)
46# define __raw_ioswabw(a, x) (x)
47# define __raw_ioswabl(a, x) (x)
48# define __raw_ioswabq(a, x) (x)
49# define ____raw_ioswabq(a, x) (x)
50
51
52
53#define IO_SPACE_LIMIT 0xffff
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62
63extern const unsigned long mips_io_port_base;
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73
74static inline void set_io_port_base(unsigned long base)
75{
76 * (unsigned long *) &mips_io_port_base = base;
77 barrier();
78}
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91
92#define __SLOW_DOWN_IO \
93 __asm__ __volatile__( \
94 "sb\t$0,0x80(%0)" \
95 : : "r" (mips_io_port_base));
96
97#ifdef CONF_SLOWDOWN_IO
98#ifdef REALLY_SLOW_IO
99#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
100#else
101#define SLOW_DOWN_IO __SLOW_DOWN_IO
102#endif
103#else
104#define SLOW_DOWN_IO
105#endif
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118
119static inline unsigned long virt_to_phys(volatile const void *address)
120{
121 return __pa(address);
122}
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135
136static inline void * phys_to_virt(unsigned long address)
137{
138 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
139}
140
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142
143
144static inline unsigned long isa_virt_to_bus(volatile void * address)
145{
146 return (unsigned long)address - PAGE_OFFSET;
147}
148
149static inline void * isa_bus_to_virt(unsigned long address)
150{
151 return (void *)(address + PAGE_OFFSET);
152}
153
154#define isa_page_to_bus page_to_phys
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161
162#define virt_to_bus virt_to_phys
163#define bus_to_virt phys_to_virt
164
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167
168#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
169
170extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
171extern void __iounmap(const volatile void __iomem *addr);
172
173#ifndef CONFIG_PCI
174struct pci_dev;
175static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
176#endif
177
178static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
179 unsigned long flags)
180{
181 void __iomem *addr = plat_ioremap(offset, size, flags);
182
183 if (addr)
184 return addr;
185
186#define __IS_LOW512(addr) (!((phys_addr_t)(addr) & (phys_addr_t) ~0x1fffffffULL))
187
188 if (cpu_has_64bit_addresses) {
189 u64 base = UNCAC_BASE;
190
191
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193
194
195 if (flags == _CACHE_UNCACHED)
196 base = (u64) IO_BASE;
197 return (void __iomem *) (unsigned long) (base + offset);
198 } else if (__builtin_constant_p(offset) &&
199 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
200 phys_addr_t phys_addr, last_addr;
201
202 phys_addr = fixup_bigphys_addr(offset, size);
203
204
205 last_addr = phys_addr + size - 1;
206 if (!size || last_addr < phys_addr)
207 return NULL;
208
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212
213 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
214 flags == _CACHE_UNCACHED)
215 return (void __iomem *)
216 (unsigned long)CKSEG1ADDR(phys_addr);
217 }
218
219 return __ioremap(offset, size, flags);
220
221#undef __IS_LOW512
222}
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234
235#define ioremap(offset, size) \
236 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
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257#define ioremap_nocache(offset, size) \
258 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
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275#define ioremap_cachable(offset, size) \
276 __ioremap_mode((offset), (size), _page_cachable_default)
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283
284#define ioremap_cacheable_cow(offset, size) \
285 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
286#define ioremap_uncached_accelerated(offset, size) \
287 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
288
289static inline void iounmap(const volatile void __iomem *addr)
290{
291 if (plat_iounmap(addr))
292 return;
293
294#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
295
296 if (cpu_has_64bit_addresses ||
297 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
298 return;
299
300 __iounmap(addr);
301
302#undef __IS_KSEG1
303}
304
305#ifdef CONFIG_CPU_CAVIUM_OCTEON
306#define war_octeon_io_reorder_wmb() wmb()
307#else
308#define war_octeon_io_reorder_wmb() do { } while (0)
309#endif
310
311#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
312 \
313static inline void pfx##write##bwlq(type val, \
314 volatile void __iomem *mem) \
315{ \
316 volatile type *__mem; \
317 type __val; \
318 \
319 war_octeon_io_reorder_wmb(); \
320 \
321 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
322 \
323 __val = pfx##ioswab##bwlq(__mem, val); \
324 \
325 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
326 *__mem = __val; \
327 else if (cpu_has_64bits) { \
328 unsigned long __flags; \
329 type __tmp; \
330 \
331 if (irq) \
332 local_irq_save(__flags); \
333 __asm__ __volatile__( \
334 ".set arch=r4000" "\t\t# __writeq""\n\t" \
335 "dsll32 %L0, %L0, 0" "\n\t" \
336 "dsrl32 %L0, %L0, 0" "\n\t" \
337 "dsll32 %M0, %M0, 0" "\n\t" \
338 "or %L0, %L0, %M0" "\n\t" \
339 "sd %L0, %2" "\n\t" \
340 ".set mips0" "\n" \
341 : "=r" (__tmp) \
342 : "0" (__val), "m" (*__mem)); \
343 if (irq) \
344 local_irq_restore(__flags); \
345 } else \
346 BUG(); \
347} \
348 \
349static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
350{ \
351 volatile type *__mem; \
352 type __val; \
353 \
354 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
355 \
356 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
357 __val = *__mem; \
358 else if (cpu_has_64bits) { \
359 unsigned long __flags; \
360 \
361 if (irq) \
362 local_irq_save(__flags); \
363 __asm__ __volatile__( \
364 ".set arch=r4000" "\t\t# __readq" "\n\t" \
365 "ld %L0, %1" "\n\t" \
366 "dsra32 %M0, %L0, 0" "\n\t" \
367 "sll %L0, %L0, 0" "\n\t" \
368 ".set mips0" "\n" \
369 : "=r" (__val) \
370 : "m" (*__mem)); \
371 if (irq) \
372 local_irq_restore(__flags); \
373 } else { \
374 __val = 0; \
375 BUG(); \
376 } \
377 \
378 return pfx##ioswab##bwlq(__mem, __val); \
379}
380
381#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
382 \
383static inline void pfx##out##bwlq##p(type val, unsigned long port) \
384{ \
385 volatile type *__addr; \
386 type __val; \
387 \
388 war_octeon_io_reorder_wmb(); \
389 \
390 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
391 \
392 __val = pfx##ioswab##bwlq(__addr, val); \
393 \
394 \
395 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
396 \
397 *__addr = __val; \
398 slow; \
399} \
400 \
401static inline type pfx##in##bwlq##p(unsigned long port) \
402{ \
403 volatile type *__addr; \
404 type __val; \
405 \
406 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
407 \
408 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
409 \
410 __val = *__addr; \
411 slow; \
412 \
413 return pfx##ioswab##bwlq(__addr, __val); \
414}
415
416#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
417 \
418__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
419
420#define BUILDIO_MEM(bwlq, type) \
421 \
422__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
423__BUILD_MEMORY_PFX(, bwlq, type) \
424__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
425
426BUILDIO_MEM(b, u8)
427BUILDIO_MEM(w, u16)
428BUILDIO_MEM(l, u32)
429BUILDIO_MEM(q, u64)
430
431#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
432 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
433 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
434
435#define BUILDIO_IOPORT(bwlq, type) \
436 __BUILD_IOPORT_PFX(, bwlq, type) \
437 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
438
439BUILDIO_IOPORT(b, u8)
440BUILDIO_IOPORT(w, u16)
441BUILDIO_IOPORT(l, u32)
442#ifdef CONFIG_64BIT
443BUILDIO_IOPORT(q, u64)
444#endif
445
446#define __BUILDIO(bwlq, type) \
447 \
448__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
449
450__BUILDIO(q, u64)
451
452#define readb_relaxed readb
453#define readw_relaxed readw
454#define readl_relaxed readl
455#define readq_relaxed readq
456
457#define writeb_relaxed writeb
458#define writew_relaxed writew
459#define writel_relaxed writel
460#define writeq_relaxed writeq
461
462#define readb_be(addr) \
463 __raw_readb((__force unsigned *)(addr))
464#define readw_be(addr) \
465 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
466#define readl_be(addr) \
467 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
468#define readq_be(addr) \
469 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
470
471#define writeb_be(val, addr) \
472 __raw_writeb((val), (__force unsigned *)(addr))
473#define writew_be(val, addr) \
474 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
475#define writel_be(val, addr) \
476 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
477#define writeq_be(val, addr) \
478 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
479
480
481
482
483#define readq readq
484#define writeq writeq
485
486#define __BUILD_MEMORY_STRING(bwlq, type) \
487 \
488static inline void writes##bwlq(volatile void __iomem *mem, \
489 const void *addr, unsigned int count) \
490{ \
491 const volatile type *__addr = addr; \
492 \
493 while (count--) { \
494 __mem_write##bwlq(*__addr, mem); \
495 __addr++; \
496 } \
497} \
498 \
499static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
500 unsigned int count) \
501{ \
502 volatile type *__addr = addr; \
503 \
504 while (count--) { \
505 *__addr = __mem_read##bwlq(mem); \
506 __addr++; \
507 } \
508}
509
510#define __BUILD_IOPORT_STRING(bwlq, type) \
511 \
512static inline void outs##bwlq(unsigned long port, const void *addr, \
513 unsigned int count) \
514{ \
515 const volatile type *__addr = addr; \
516 \
517 while (count--) { \
518 __mem_out##bwlq(*__addr, port); \
519 __addr++; \
520 } \
521} \
522 \
523static inline void ins##bwlq(unsigned long port, void *addr, \
524 unsigned int count) \
525{ \
526 volatile type *__addr = addr; \
527 \
528 while (count--) { \
529 *__addr = __mem_in##bwlq(port); \
530 __addr++; \
531 } \
532}
533
534#define BUILDSTRING(bwlq, type) \
535 \
536__BUILD_MEMORY_STRING(bwlq, type) \
537__BUILD_IOPORT_STRING(bwlq, type)
538
539BUILDSTRING(b, u8)
540BUILDSTRING(w, u16)
541BUILDSTRING(l, u32)
542#ifdef CONFIG_64BIT
543BUILDSTRING(q, u64)
544#endif
545
546
547#ifdef CONFIG_CPU_CAVIUM_OCTEON
548#define mmiowb() wmb()
549#else
550
551#define mmiowb() asm volatile ("sync" ::: "memory")
552#endif
553
554static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
555{
556 memset((void __force *) addr, val, count);
557}
558static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
559{
560 memcpy(dst, (void __force *) src, count);
561}
562static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
563{
564 memcpy((void __force *) dst, src, count);
565}
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587#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
588
589extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
590extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
591extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
592
593#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
594#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
595#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
596
597#else
598
599#define dma_cache_wback_inv(start,size) \
600 do { (void) (start); (void) (size); } while (0)
601#define dma_cache_wback(start,size) \
602 do { (void) (start); (void) (size); } while (0)
603#define dma_cache_inv(start,size) \
604 do { (void) (start); (void) (size); } while (0)
605
606#endif
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612
613#ifdef __MIPSEB__
614#define __CSR_32_ADJUST 4
615#else
616#define __CSR_32_ADJUST 0
617#endif
618
619#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
620#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
621
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623
624
625
626#define xlate_dev_mem_ptr(p) __va(p)
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631#define xlate_dev_kmem_ptr(p) p
632
633#endif
634