LXR linux/arch/mips/pci/ops-bonito64.c

   1/*
   2 * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
   3 *      All rights reserved.
   4 *      Authors: Carsten Langgaard <carstenl@mips.com>
   5 *               Maciej W. Rozycki <macro@mips.com>
   6 *
   7 *  This program is free software; you can distribute it and/or modify it
   8 *  under the terms of the GNU General Public License (Version 2) as
   9 *  published by the Free Software Foundation.
  10 *
  11 *  This program is distributed in the hope it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 *  for more details.
  15 *
  16 *  You should have received a copy of the GNU General Public License along
  17 *  with this program; if not, write to the Free Software Foundation, Inc.,
  18 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19 *
  20 * MIPS boards specific PCI support.
  21 */
  22#include <linux/types.h>
  23#include <linux/pci.h>
  24#include <linux/kernel.h>
  25
  26#include <asm/mips-boards/bonito64.h>
  27
  28#define PCI_ACCESS_READ  0
  29#define PCI_ACCESS_WRITE 1
  30
  31#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
  32#define ID_SEL_BEGIN 10
  33#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
  34
  35
  36static int bonito64_pcibios_config_access(unsigned char access_type,
  37                                      struct pci_bus *bus,
  38                                      unsigned int devfn, int where,
  39                                      u32 * data)
  40{
  41        u32 busnum = bus->number;
  42        u32 addr, type;
  43        u32 dummy;
  44        void *addrp;
  45        int device = PCI_SLOT(devfn);
  46        int function = PCI_FUNC(devfn);
  47        int reg = where & ~3;
  48
  49        if (busnum == 0) {
  50                /* Type 0 configuration for onboard PCI bus */
  51                if (device > MAX_DEV_NUM)
  52                        return -1;
  53
  54                addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
  55                type = 0;
  56        } else {
  57                /* Type 1 configuration for offboard PCI bus */
  58                addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
  59                type = 0x10000;
  60        }
  61
  62        /* Clear aborts */
  63        BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR;
  64
  65        BONITO_PCIMAP_CFG = (addr >> 16) | type;
  66
  67        /* Flush Bonito register block */
  68        dummy = BONITO_PCIMAP_CFG;
  69        mmiowb();
  70
  71        addrp = CFG_SPACE_REG(addr & 0xffff);
  72        if (access_type == PCI_ACCESS_WRITE) {
  73                writel(cpu_to_le32(*data), addrp);
  74                /* Wait till done */
  75                while (BONITO_PCIMSTAT & 0xF);
  76        } else {
  77                *data = le32_to_cpu(readl(addrp));
  78        }
  79
  80        /* Detect Master/Target abort */
  81        if (BONITO_PCICMD & (BONITO_PCICMD_MABORT_CLR |
  82                             BONITO_PCICMD_MTABORT_CLR)) {
  83                /* Error occurred */
  84
  85                /* Clear bits */
  86                BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
  87                                  BONITO_PCICMD_MTABORT_CLR);
  88
  89                return -1;
  90        }
  91
  92        return 0;
  93
  94}
  95
  96
  97/*
  98 * We can't address 8 and 16 bit words directly.  Instead we have to
  99 * read/write a 32bit word and mask/modify the data we actually want.
 100 */
 101static int bonito64_pcibios_read(struct pci_bus *bus, unsigned int devfn,
 102                             int where, int size, u32 * val)
 103{
 104        u32 data = 0;
 105
 106        if ((size == 2) && (where & 1))
 107                return PCIBIOS_BAD_REGISTER_NUMBER;
 108        else if ((size == 4) && (where & 3))
 109                return PCIBIOS_BAD_REGISTER_NUMBER;
 110
 111        if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
 112                                       &data))
 113                return -1;
 114
 115        if (size == 1)
 116                *val = (data >> ((where & 3) << 3)) & 0xff;
 117        else if (size == 2)
 118                *val = (data >> ((where & 3) << 3)) & 0xffff;
 119        else
 120                *val = data;
 121
 122        return PCIBIOS_SUCCESSFUL;
 123}
 124
 125static int bonito64_pcibios_write(struct pci_bus *bus, unsigned int devfn,
 126                              int where, int size, u32 val)
 127{
 128        u32 data = 0;
 129
 130        if ((size == 2) && (where & 1))
 131                return PCIBIOS_BAD_REGISTER_NUMBER;
 132        else if ((size == 4) && (where & 3))
 133                return PCIBIOS_BAD_REGISTER_NUMBER;
 134
 135        if (size == 4)
 136                data = val;
 137        else {
 138                if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
 139                                               where, &data))
 140                        return -1;
 141
 142                if (size == 1)
 143                        data = (data & ~(0xff << ((where & 3) << 3))) |
 144                                (val << ((where & 3) << 3));
 145                else if (size == 2)
 146                        data = (data & ~(0xffff << ((where & 3) << 3))) |
 147                                (val << ((where & 3) << 3));
 148        }
 149
 150        if (bonito64_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
 151                                       &data))
 152                return -1;
 153
 154        return PCIBIOS_SUCCESSFUL;
 155}
 156
 157struct pci_ops bonito64_pci_ops = {
 158        .read = bonito64_pcibios_read,
 159        .write = bonito64_pcibios_write
 160};
 161