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8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/platform_device.h>
15#include <linux/swiotlb.h>
16
17#include <asm/time.h>
18
19#include <asm/octeon/octeon.h>
20#include <asm/octeon/cvmx-npi-defs.h>
21#include <asm/octeon/cvmx-pci-defs.h>
22#include <asm/octeon/pci-octeon.h>
23
24#include <dma-coherence.h>
25
26#define USE_OCTEON_INTERNAL_ARBITER
27
28
29
30
31
32
33#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
34#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
35
36
37#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
38
39u64 octeon_bar1_pci_phys;
40
41
42
43
44union octeon_pci_address {
45 uint64_t u64;
46 struct {
47 uint64_t upper:2;
48 uint64_t reserved:13;
49 uint64_t io:1;
50 uint64_t did:5;
51 uint64_t subdid:3;
52 uint64_t reserved2:4;
53 uint64_t endian_swap:2;
54 uint64_t reserved3:10;
55 uint64_t bus:8;
56 uint64_t dev:5;
57 uint64_t func:3;
58 uint64_t reg:8;
59 } s;
60};
61
62int __initconst (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
63 u8 slot, u8 pin);
64enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
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76
77int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
78{
79 if (octeon_pcibios_map_irq)
80 return octeon_pcibios_map_irq(dev, slot, pin);
81 else
82 panic("octeon_pcibios_map_irq not set.");
83}
84
85
86
87
88
89int pcibios_plat_dev_init(struct pci_dev *dev)
90{
91 uint16_t config;
92 uint32_t dconfig;
93 int pos;
94
95
96
97
98
99
100
101 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
102
103 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
104
105
106
107 pci_read_config_word(dev, PCI_COMMAND, &config);
108 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
109 pci_write_config_word(dev, PCI_COMMAND, config);
110
111 if (dev->subordinate) {
112
113 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
114
115 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
116 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
117 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
118 }
119
120
121 config = PCI_EXP_DEVCTL_CERE;
122 config |= PCI_EXP_DEVCTL_NFERE;
123 config |= PCI_EXP_DEVCTL_FERE;
124 config |= PCI_EXP_DEVCTL_URRE;
125 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
126
127
128 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
129 if (pos) {
130
131 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
132 &dconfig);
133 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
134 dconfig);
135
136
137 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
138
139
140
141
142
143
144
145 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
146 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
147
148
149 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
150
151 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
152
153 if (config & PCI_ERR_CAP_ECRC_GENC)
154 config |= PCI_ERR_CAP_ECRC_GENE;
155
156 if (config & PCI_ERR_CAP_ECRC_CHKC)
157 config |= PCI_ERR_CAP_ECRC_CHKE;
158 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
159
160
161 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
162 PCI_ERR_ROOT_CMD_COR_EN |
163 PCI_ERR_ROOT_CMD_NONFATAL_EN |
164 PCI_ERR_ROOT_CMD_FATAL_EN);
165
166 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
167 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
168 }
169
170 dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
171
172 return 0;
173}
174
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182
183
184const char *octeon_get_pci_interrupts(void)
185{
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206
207 switch (octeon_bootinfo->board_type) {
208 case CVMX_BOARD_TYPE_NAO38:
209
210 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
211 case CVMX_BOARD_TYPE_EBH3100:
212 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
213 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
214 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
215 case CVMX_BOARD_TYPE_BBGW_REF:
216 return "AABCD";
217 case CVMX_BOARD_TYPE_CUST_DSR1000N:
218 return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
219 case CVMX_BOARD_TYPE_THUNDER:
220 case CVMX_BOARD_TYPE_EBH3000:
221 default:
222 return "";
223 }
224}
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236
237int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
238 u8 slot, u8 pin)
239{
240 int irq_num;
241 const char *interrupts;
242 int dev_num;
243
244
245 interrupts = octeon_get_pci_interrupts();
246
247 dev_num = dev->devfn >> 3;
248 if (dev_num < strlen(interrupts))
249 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
250 OCTEON_IRQ_PCI_INT0;
251 else
252 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
253 return irq_num;
254}
255
256
257
258
259
260static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
261 int reg, int size, u32 *val)
262{
263 union octeon_pci_address pci_addr;
264
265 pci_addr.u64 = 0;
266 pci_addr.s.upper = 2;
267 pci_addr.s.io = 1;
268 pci_addr.s.did = 3;
269 pci_addr.s.subdid = 1;
270 pci_addr.s.endian_swap = 1;
271 pci_addr.s.bus = bus->number;
272 pci_addr.s.dev = devfn >> 3;
273 pci_addr.s.func = devfn & 0x7;
274 pci_addr.s.reg = reg;
275
276 switch (size) {
277 case 4:
278 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
279 return PCIBIOS_SUCCESSFUL;
280 case 2:
281 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
282 return PCIBIOS_SUCCESSFUL;
283 case 1:
284 *val = cvmx_read64_uint8(pci_addr.u64);
285 return PCIBIOS_SUCCESSFUL;
286 }
287 return PCIBIOS_FUNC_NOT_SUPPORTED;
288}
289
290
291
292
293
294static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
295 int reg, int size, u32 val)
296{
297 union octeon_pci_address pci_addr;
298
299 pci_addr.u64 = 0;
300 pci_addr.s.upper = 2;
301 pci_addr.s.io = 1;
302 pci_addr.s.did = 3;
303 pci_addr.s.subdid = 1;
304 pci_addr.s.endian_swap = 1;
305 pci_addr.s.bus = bus->number;
306 pci_addr.s.dev = devfn >> 3;
307 pci_addr.s.func = devfn & 0x7;
308 pci_addr.s.reg = reg;
309
310 switch (size) {
311 case 4:
312 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
313 return PCIBIOS_SUCCESSFUL;
314 case 2:
315 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
316 return PCIBIOS_SUCCESSFUL;
317 case 1:
318 cvmx_write64_uint8(pci_addr.u64, val);
319 return PCIBIOS_SUCCESSFUL;
320 }
321 return PCIBIOS_FUNC_NOT_SUPPORTED;
322}
323
324
325static struct pci_ops octeon_pci_ops = {
326 .read = octeon_read_config,
327 .write = octeon_write_config,
328};
329
330static struct resource octeon_pci_mem_resource = {
331 .start = 0,
332 .end = 0,
333 .name = "Octeon PCI MEM",
334 .flags = IORESOURCE_MEM,
335};
336
337
338
339
340
341static struct resource octeon_pci_io_resource = {
342 .start = 0x4000,
343 .end = OCTEON_PCI_IOSPACE_SIZE - 1,
344 .name = "Octeon PCI IO",
345 .flags = IORESOURCE_IO,
346};
347
348static struct pci_controller octeon_pci_controller = {
349 .pci_ops = &octeon_pci_ops,
350 .mem_resource = &octeon_pci_mem_resource,
351 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
352 .io_resource = &octeon_pci_io_resource,
353 .io_offset = 0,
354 .io_map_base = OCTEON_PCI_IOSPACE_BASE,
355};
356
357
358
359
360
361static void octeon_pci_initialize(void)
362{
363 union cvmx_pci_cfg01 cfg01;
364 union cvmx_npi_ctl_status ctl_status;
365 union cvmx_pci_ctl_status_2 ctl_status_2;
366 union cvmx_pci_cfg19 cfg19;
367 union cvmx_pci_cfg16 cfg16;
368 union cvmx_pci_cfg22 cfg22;
369 union cvmx_pci_cfg56 cfg56;
370
371
372 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
373 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
374
375 udelay(2000);
376
377 ctl_status.u64 = 0;
378 ctl_status.s.max_word = 1;
379 ctl_status.s.timer = 1;
380 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
381
382
383
384 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
385 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
386
387 udelay(2000);
388
389 ctl_status_2.u32 = 0;
390 ctl_status_2.s.tsr_hwm = 1;
391
392 ctl_status_2.s.bar2pres = 1;
393 ctl_status_2.s.bar2_enb = 1;
394 ctl_status_2.s.bar2_cax = 1;
395 ctl_status_2.s.bar2_esx = 1;
396 ctl_status_2.s.pmo_amod = 1;
397 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
398
399 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
400 ctl_status_2.s.bb1_siz = 1;
401 ctl_status_2.s.bb_ca = 1;
402 ctl_status_2.s.bb_es = 1;
403 ctl_status_2.s.bb1 = 1;
404 ctl_status_2.s.bb0 = 1;
405 }
406
407 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
408 udelay(2000);
409
410 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
411 pr_notice("PCI Status: %s %s-bit\n",
412 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
413 ctl_status_2.s.ap_64ad ? "64" : "32");
414
415 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
416 union cvmx_pci_cnt_reg cnt_reg_start;
417 union cvmx_pci_cnt_reg cnt_reg_end;
418 unsigned long cycles, pci_clock;
419
420 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
421 cycles = read_c0_cvmcount();
422 udelay(1000);
423 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
424 cycles = read_c0_cvmcount() - cycles;
425 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
426 (cycles / (mips_hpt_frequency / 1000000));
427 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
428 }
429
430
431
432
433
434
435
436
437
438 if (ctl_status_2.s.ap_pcix) {
439 cfg19.u32 = 0;
440
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449
450
451
452 cfg19.s.tdomc = 4;
453
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463
464 cfg19.s.mdrrmc = 2;
465
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467
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473
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475
476 cfg19.s.mrbcm = 1;
477 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
478 }
479
480
481 cfg01.u32 = 0;
482 cfg01.s.msae = 1;
483 cfg01.s.me = 1;
484 cfg01.s.pee = 1;
485 cfg01.s.see = 1;
486 cfg01.s.fbbe = 1;
487
488 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
489
490#ifdef USE_OCTEON_INTERNAL_ARBITER
491
492
493
494
495
496 {
497 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
498
499 pci_int_arb_cfg.u64 = 0;
500 pci_int_arb_cfg.s.en = 1;
501 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
502 }
503#endif
504
505
506
507
508
509
510 cfg16.u32 = 0;
511 cfg16.s.mltd = 1;
512 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
513
514
515
516
517
518 cfg22.u32 = 0;
519
520 cfg22.s.mrv = 0xff;
521
522
523
524
525 cfg22.s.flush = 1;
526 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
527
528
529
530
531
532
533
534
535 cfg56.u32 = 0;
536 cfg56.s.pxcid = 7;
537 cfg56.s.ncp = 0xe8;
538 cfg56.s.dpere = 1;
539 cfg56.s.roe = 1;
540 cfg56.s.mmbc = 1;
541
542 cfg56.s.most = 3;
543
544
545 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
546
547
548
549
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552
553
554
555
556 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
557 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
558 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
559}
560
561
562
563
564
565static int __init octeon_pci_setup(void)
566{
567 union cvmx_npi_mem_access_subidx mem_access;
568 int index;
569
570
571 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
572 return 0;
573
574
575 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
576
577
578 if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
579 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
580 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
581 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
582 else
583 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
584
585 if (!octeon_is_pci_host()) {
586 pr_notice("Not in host mode, PCI Controller not initialized\n");
587 return 0;
588 }
589
590
591 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
592 ioport_resource.start = 0;
593 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
594
595 pr_notice("%s Octeon big bar support\n",
596 (octeon_dma_bar_type ==
597 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
598
599 octeon_pci_initialize();
600
601 mem_access.u64 = 0;
602 mem_access.s.esr = 1;
603 mem_access.s.esw = 1;
604 mem_access.s.nsr = 0;
605 mem_access.s.nsw = 0;
606 mem_access.s.ror = 0;
607 mem_access.s.row = 0;
608 mem_access.s.ba = 0;
609 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
610
611
612
613
614
615
616
617 octeon_npi_write32(CVMX_NPI_PCI_CFG08,
618 (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
619 octeon_npi_write32(CVMX_NPI_PCI_CFG09,
620 (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
621
622 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
623
624 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
625 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
626
627
628
629
630
631 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
632 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
633
634
635 octeon_bar1_pci_phys = 0x80000000ull;
636 for (index = 0; index < 32; index++) {
637 union cvmx_pci_bar1_indexx bar1_index;
638
639 bar1_index.u32 = 0;
640
641 bar1_index.s.addr_idx =
642 (octeon_bar1_pci_phys >> 22) + index;
643
644 bar1_index.s.ca = 1;
645
646 bar1_index.s.end_swp = 1;
647
648 bar1_index.s.addr_v = 1;
649 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
650 bar1_index.u32);
651 }
652
653
654 octeon_pci_mem_resource.start =
655 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
656 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
657 octeon_pci_mem_resource.end =
658 octeon_pci_mem_resource.start + (1ul << 30);
659 } else {
660
661 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
662 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
663
664
665 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
666 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
667
668
669 octeon_bar1_pci_phys =
670 virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
671
672 for (index = 0; index < 32; index++) {
673 union cvmx_pci_bar1_indexx bar1_index;
674
675 bar1_index.u32 = 0;
676
677 bar1_index.s.addr_idx =
678 (octeon_bar1_pci_phys >> 22) + index;
679
680 bar1_index.s.ca = 1;
681
682 bar1_index.s.end_swp = 1;
683
684 bar1_index.s.addr_v = 1;
685 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
686 bar1_index.u32);
687 }
688
689
690 octeon_pci_mem_resource.start =
691 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
692 (4ul << 10);
693 octeon_pci_mem_resource.end =
694 octeon_pci_mem_resource.start + (1ul << 30);
695 }
696
697 register_pci_controller(&octeon_pci_controller);
698
699
700
701
702
703 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
704
705 if (IS_ERR(platform_device_register_simple("octeon_pci_edac",
706 -1, NULL, 0)))
707 pr_err("Registration of co_pci_edac failed!\n");
708
709 octeon_pci_dma_init();
710
711 return 0;
712}
713
714arch_initcall(octeon_pci_setup);
715