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11#include <linux/interrupt.h>
12#include <linux/clockchips.h>
13#include <linux/clocksource.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/io.h>
19#include <linux/slab.h>
20
21#define ALTERA_TIMER_STATUS_REG 0
22#define ALTERA_TIMER_CONTROL_REG 4
23#define ALTERA_TIMER_PERIODL_REG 8
24#define ALTERA_TIMER_PERIODH_REG 12
25#define ALTERA_TIMER_SNAPL_REG 16
26#define ALTERA_TIMER_SNAPH_REG 20
27
28#define ALTERA_TIMER_CONTROL_ITO_MSK (0x1)
29#define ALTERA_TIMER_CONTROL_CONT_MSK (0x2)
30#define ALTERA_TIMER_CONTROL_START_MSK (0x4)
31#define ALTERA_TIMER_CONTROL_STOP_MSK (0x8)
32
33struct nios2_timer {
34 void __iomem *base;
35 unsigned long freq;
36};
37
38struct nios2_clockevent_dev {
39 struct nios2_timer timer;
40 struct clock_event_device ced;
41};
42
43struct nios2_clocksource {
44 struct nios2_timer timer;
45 struct clocksource cs;
46};
47
48static inline struct nios2_clockevent_dev *
49 to_nios2_clkevent(struct clock_event_device *evt)
50{
51 return container_of(evt, struct nios2_clockevent_dev, ced);
52}
53
54static inline struct nios2_clocksource *
55 to_nios2_clksource(struct clocksource *cs)
56{
57 return container_of(cs, struct nios2_clocksource, cs);
58}
59
60static u16 timer_readw(struct nios2_timer *timer, u32 offs)
61{
62 return readw(timer->base + offs);
63}
64
65static void timer_writew(struct nios2_timer *timer, u16 val, u32 offs)
66{
67 writew(val, timer->base + offs);
68}
69
70static inline unsigned long read_timersnapshot(struct nios2_timer *timer)
71{
72 unsigned long count;
73
74 timer_writew(timer, 0, ALTERA_TIMER_SNAPL_REG);
75 count = timer_readw(timer, ALTERA_TIMER_SNAPH_REG) << 16 |
76 timer_readw(timer, ALTERA_TIMER_SNAPL_REG);
77
78 return count;
79}
80
81static cycle_t nios2_timer_read(struct clocksource *cs)
82{
83 struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs);
84 unsigned long flags;
85 u32 count;
86
87 local_irq_save(flags);
88 count = read_timersnapshot(&nios2_cs->timer);
89 local_irq_restore(flags);
90
91
92 return ~count;
93}
94
95static struct nios2_clocksource nios2_cs = {
96 .cs = {
97 .name = "nios2-clksrc",
98 .rating = 250,
99 .read = nios2_timer_read,
100 .mask = CLOCKSOURCE_MASK(32),
101 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
102 },
103};
104
105cycles_t get_cycles(void)
106{
107 return nios2_timer_read(&nios2_cs.cs);
108}
109
110static void nios2_timer_start(struct nios2_timer *timer)
111{
112 u16 ctrl;
113
114 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
115 ctrl |= ALTERA_TIMER_CONTROL_START_MSK;
116 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
117}
118
119static void nios2_timer_stop(struct nios2_timer *timer)
120{
121 u16 ctrl;
122
123 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
124 ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK;
125 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
126}
127
128static void nios2_timer_config(struct nios2_timer *timer, unsigned long period,
129 enum clock_event_mode mode)
130{
131 u16 ctrl;
132
133
134
135 period--;
136
137 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG);
138
139 timer_writew(timer, ctrl | ALTERA_TIMER_CONTROL_STOP_MSK,
140 ALTERA_TIMER_CONTROL_REG);
141
142
143 timer_writew(timer, period, ALTERA_TIMER_PERIODL_REG);
144 timer_writew(timer, period >> 16, ALTERA_TIMER_PERIODH_REG);
145
146 ctrl |= ALTERA_TIMER_CONTROL_START_MSK | ALTERA_TIMER_CONTROL_ITO_MSK;
147 if (mode == CLOCK_EVT_MODE_PERIODIC)
148 ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK;
149 else
150 ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK;
151 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG);
152}
153
154static int nios2_timer_set_next_event(unsigned long delta,
155 struct clock_event_device *evt)
156{
157 struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
158
159 nios2_timer_config(&nios2_ced->timer, delta, evt->mode);
160
161 return 0;
162}
163
164static void nios2_timer_set_mode(enum clock_event_mode mode,
165 struct clock_event_device *evt)
166{
167 unsigned long period;
168 struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
169 struct nios2_timer *timer = &nios2_ced->timer;
170
171 switch (mode) {
172 case CLOCK_EVT_MODE_PERIODIC:
173 period = DIV_ROUND_UP(timer->freq, HZ);
174 nios2_timer_config(timer, period, CLOCK_EVT_MODE_PERIODIC);
175 break;
176 case CLOCK_EVT_MODE_ONESHOT:
177 case CLOCK_EVT_MODE_UNUSED:
178 case CLOCK_EVT_MODE_SHUTDOWN:
179 nios2_timer_stop(timer);
180 break;
181 case CLOCK_EVT_MODE_RESUME:
182 nios2_timer_start(timer);
183 break;
184 }
185}
186
187irqreturn_t timer_interrupt(int irq, void *dev_id)
188{
189 struct clock_event_device *evt = (struct clock_event_device *) dev_id;
190 struct nios2_clockevent_dev *nios2_ced = to_nios2_clkevent(evt);
191
192
193 timer_writew(&nios2_ced->timer, 0, ALTERA_TIMER_STATUS_REG);
194 evt->event_handler(evt);
195
196 return IRQ_HANDLED;
197}
198
199static void __init nios2_timer_get_base_and_freq(struct device_node *np,
200 void __iomem **base, u32 *freq)
201{
202 *base = of_iomap(np, 0);
203 if (!*base)
204 panic("Unable to map reg for %s\n", np->name);
205
206 if (of_property_read_u32(np, "clock-frequency", freq))
207 panic("Unable to get %s clock frequency\n", np->name);
208}
209
210static struct nios2_clockevent_dev nios2_ce = {
211 .ced = {
212 .name = "nios2-clkevent",
213 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
214 .rating = 250,
215 .shift = 32,
216 .set_next_event = nios2_timer_set_next_event,
217 .set_mode = nios2_timer_set_mode,
218 },
219};
220
221static __init void nios2_clockevent_init(struct device_node *timer)
222{
223 void __iomem *iobase;
224 u32 freq;
225 int irq;
226
227 nios2_timer_get_base_and_freq(timer, &iobase, &freq);
228
229 irq = irq_of_parse_and_map(timer, 0);
230 if (!irq)
231 panic("Unable to parse timer irq\n");
232
233 nios2_ce.timer.base = iobase;
234 nios2_ce.timer.freq = freq;
235
236 nios2_ce.ced.cpumask = cpumask_of(0);
237 nios2_ce.ced.irq = irq;
238
239 nios2_timer_stop(&nios2_ce.timer);
240
241 timer_writew(&nios2_ce.timer, 0, ALTERA_TIMER_STATUS_REG);
242
243 if (request_irq(irq, timer_interrupt, IRQF_TIMER, timer->name,
244 &nios2_ce.ced))
245 panic("Unable to setup timer irq\n");
246
247 clockevents_config_and_register(&nios2_ce.ced, freq, 1, ULONG_MAX);
248}
249
250static __init void nios2_clocksource_init(struct device_node *timer)
251{
252 unsigned int ctrl;
253 void __iomem *iobase;
254 u32 freq;
255
256 nios2_timer_get_base_and_freq(timer, &iobase, &freq);
257
258 nios2_cs.timer.base = iobase;
259 nios2_cs.timer.freq = freq;
260
261 clocksource_register_hz(&nios2_cs.cs, freq);
262
263 timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODL_REG);
264 timer_writew(&nios2_cs.timer, USHRT_MAX, ALTERA_TIMER_PERIODH_REG);
265
266
267 ctrl = ALTERA_TIMER_CONTROL_CONT_MSK | ALTERA_TIMER_CONTROL_START_MSK;
268 timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG);
269
270
271 lpj_fine = freq / HZ;
272}
273
274
275
276
277
278
279static void __init nios2_time_init(struct device_node *timer)
280{
281 static int num_called;
282
283 switch (num_called) {
284 case 0:
285 nios2_clockevent_init(timer);
286 break;
287 case 1:
288 nios2_clocksource_init(timer);
289 break;
290 default:
291 break;
292 }
293
294 num_called++;
295}
296
297void read_persistent_clock(struct timespec *ts)
298{
299 ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0);
300 ts->tv_nsec = 0;
301}
302
303void __init time_init(void)
304{
305 clocksource_of_init();
306}
307
308CLOCKSOURCE_OF_DECLARE(nios2_timer, "altr,timer-1.0", nios2_time_init);
309
