1
2
3
4#ifndef _ASM_POWERPC_MUTEX_H
5#define _ASM_POWERPC_MUTEX_H
6
7static inline int __mutex_cmpxchg_lock(atomic_t *v, int old, int new)
8{
9 int t;
10
11 __asm__ __volatile__ (
12"1: lwarx %0,0,%1 # mutex trylock\n\
13 cmpw 0,%0,%2\n\
14 bne- 2f\n"
15 PPC405_ERR77(0,%1)
16" stwcx. %3,0,%1\n\
17 bne- 1b"
18 PPC_ACQUIRE_BARRIER
19 "\n\
202:"
21 : "=&r" (t)
22 : "r" (&v->counter), "r" (old), "r" (new)
23 : "cc", "memory");
24
25 return t;
26}
27
28static inline int __mutex_dec_return_lock(atomic_t *v)
29{
30 int t;
31
32 __asm__ __volatile__(
33"1: lwarx %0,0,%1 # mutex lock\n\
34 addic %0,%0,-1\n"
35 PPC405_ERR77(0,%1)
36" stwcx. %0,0,%1\n\
37 bne- 1b"
38 PPC_ACQUIRE_BARRIER
39 : "=&r" (t)
40 : "r" (&v->counter)
41 : "cc", "memory");
42
43 return t;
44}
45
46static inline int __mutex_inc_return_unlock(atomic_t *v)
47{
48 int t;
49
50 __asm__ __volatile__(
51 PPC_RELEASE_BARRIER
52"1: lwarx %0,0,%1 # mutex unlock\n\
53 addic %0,%0,1\n"
54 PPC405_ERR77(0,%1)
55" stwcx. %0,0,%1 \n\
56 bne- 1b"
57 : "=&r" (t)
58 : "r" (&v->counter)
59 : "cc", "memory");
60
61 return t;
62}
63
64
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66
67
68
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70
71
72
73
74static inline void
75__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
76{
77 if (unlikely(__mutex_dec_return_lock(count) < 0))
78 fail_fn(count);
79}
80
81
82
83
84
85
86
87
88
89static inline int
90__mutex_fastpath_lock_retval(atomic_t *count)
91{
92 if (unlikely(__mutex_dec_return_lock(count) < 0))
93 return -1;
94 return 0;
95}
96
97
98
99
100
101
102
103
104
105
106static inline void
107__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
108{
109 if (unlikely(__mutex_inc_return_unlock(count) <= 0))
110 fail_fn(count);
111}
112
113#define __mutex_slowpath_needs_to_unlock() 1
114
115
116
117
118
119
120
121
122
123
124static inline int
125__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
126{
127 if (likely(__mutex_cmpxchg_lock(count, 1, 0) == 1))
128 return 1;
129 return 0;
130}
131
132#endif
133