1#ifndef _ASM_POWERPC_PAGE_64_H
2#define _ASM_POWERPC_PAGE_64_H
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17
18#define HW_PAGE_SHIFT 12
19#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
20#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
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24
25
26#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
27
28
29#define SID_SHIFT 28
30#define SID_MASK ASM_CONST(0xfffffffff)
31#define ESID_MASK 0xfffffffff0000000UL
32#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
33
34
35#define SID_SHIFT_1T 40
36#define SID_MASK_1T 0xffffffUL
37#define ESID_MASK_1T 0xffffff0000000000UL
38#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
39
40#ifndef __ASSEMBLY__
41#include <asm/cache.h>
42
43typedef unsigned long pte_basic_t;
44
45static inline void clear_page(void *addr)
46{
47 unsigned long iterations;
48 unsigned long onex, twox, fourx, eightx;
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50 iterations = ppc64_caches.dlines_per_page / 8;
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57 onex = ppc64_caches.dline_size;
58 twox = onex << 1;
59 fourx = onex << 2;
60 eightx = onex << 3;
61
62 asm volatile(
63 "mtctr %1 # clear_page\n\
64 .balign 16\n\
651: dcbz 0,%0\n\
66 dcbz %3,%0\n\
67 dcbz %4,%0\n\
68 dcbz %5,%0\n\
69 dcbz %6,%0\n\
70 dcbz %7,%0\n\
71 dcbz %8,%0\n\
72 dcbz %9,%0\n\
73 add %0,%0,%10\n\
74 bdnz+ 1b"
75 : "=&r" (addr)
76 : "r" (iterations), "0" (addr), "b" (onex), "b" (twox),
77 "b" (twox+onex), "b" (fourx), "b" (fourx+onex),
78 "b" (twox+fourx), "b" (eightx-onex), "r" (eightx)
79 : "ctr", "memory");
80}
81
82extern void copy_page(void *to, void *from);
83
84
85extern u64 ppc64_pft_size;
86
87#endif
88
89#ifdef CONFIG_PPC_MM_SLICES
90
91#define SLICE_LOW_SHIFT 28
92#define SLICE_HIGH_SHIFT 40
93
94#define SLICE_LOW_TOP (0x100000000ul)
95#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
96#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
97
98#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
99#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
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105
106
107#define SLICE_MASK_SIZE 8
108
109#ifndef __ASSEMBLY__
110
111struct slice_mask {
112 u16 low_slices;
113 u64 high_slices;
114};
115
116struct mm_struct;
117
118extern unsigned long slice_get_unmapped_area(unsigned long addr,
119 unsigned long len,
120 unsigned long flags,
121 unsigned int psize,
122 int topdown);
123
124extern unsigned int get_slice_psize(struct mm_struct *mm,
125 unsigned long addr);
126
127extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
128extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
129 unsigned long len, unsigned int psize);
130
131#define slice_mm_new_context(mm) ((mm)->context.id == MMU_NO_CONTEXT)
132
133#endif
134#else
135#define slice_init()
136#ifdef CONFIG_PPC_STD_MMU_64
137#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
138#define slice_set_user_psize(mm, psize) \
139do { \
140 (mm)->context.user_psize = (psize); \
141 (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
142} while (0)
143#else
144#ifdef CONFIG_PPC_64K_PAGES
145#define get_slice_psize(mm, addr) MMU_PAGE_64K
146#else
147#define get_slice_psize(mm, addr) MMU_PAGE_4K
148#endif
149#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
150#endif
151
152#define slice_set_range_psize(mm, start, len, psize) \
153 slice_set_user_psize((mm), (psize))
154#define slice_mm_new_context(mm) 1
155#endif
156
157#ifdef CONFIG_HUGETLB_PAGE
158
159#ifdef CONFIG_PPC_MM_SLICES
160#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
161#endif
162
163#endif
164
165#define VM_DATA_DEFAULT_FLAGS \
166 (is_32bit_task() ? \
167 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
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174
175#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
176 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
177
178#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
179 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
180
181#define VM_STACK_DEFAULT_FLAGS \
182 (is_32bit_task() ? \
183 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
184
185#include <asm-generic/getorder.h>
186
187#endif
188