1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/types.h>
4#include <asm/byteorder.h>
5
6#define add_ssaaaa(sh, sl, ah, al, bh, bl) ({ \
7 unsigned int __sh = (ah); \
8 unsigned int __sl = (al); \
9 asm volatile( \
10 " alr %1,%3\n" \
11 " brc 12,0f\n" \
12 " ahi %0,1\n" \
13 "0: alr %0,%2" \
14 : "+&d" (__sh), "+d" (__sl) \
15 : "d" (bh), "d" (bl) : "cc"); \
16 (sh) = __sh; \
17 (sl) = __sl; \
18})
19
20#define sub_ddmmss(sh, sl, ah, al, bh, bl) ({ \
21 unsigned int __sh = (ah); \
22 unsigned int __sl = (al); \
23 asm volatile( \
24 " slr %1,%3\n" \
25 " brc 3,0f\n" \
26 " ahi %0,-1\n" \
27 "0: slr %0,%2" \
28 : "+&d" (__sh), "+d" (__sl) \
29 : "d" (bh), "d" (bl) : "cc"); \
30 (sh) = __sh; \
31 (sl) = __sl; \
32})
33
34
35#define umul_ppmm(wh, wl, u, v) ({ \
36 unsigned int __wh = u; \
37 unsigned int __wl = v; \
38 asm volatile( \
39 " ltr 1,%0\n" \
40 " mr 0,%1\n" \
41 " jnm 0f\n" \
42 " alr 0,%1\n" \
43 "0: ltr %1,%1\n" \
44 " jnm 1f\n" \
45 " alr 0,%0\n" \
46 "1: lr %0,0\n" \
47 " lr %1,1\n" \
48 : "+d" (__wh), "+d" (__wl) \
49 : : "0", "1", "cc"); \
50 wh = __wh; \
51 wl = __wl; \
52})
53
54#define udiv_qrnnd(q, r, n1, n0, d) \
55 do { unsigned long __n; \
56 unsigned int __r, __d; \
57 __n = ((unsigned long)(n1) << 32) + n0; \
58 __d = (d); \
59 (q) = __n / __d; \
60 (r) = __n % __d; \
61 } while (0)
62
63#define UDIV_NEEDS_NORMALIZATION 0
64
65#define abort() BUG()
66
67#define __BYTE_ORDER __BIG_ENDIAN
68
