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21#include <linux/kvm_host.h>
22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/math64.h>
30#include <linux/slab.h>
31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
36#include <asm/delay.h>
37#include <linux/atomic.h>
38#include <linux/jump_label.h>
39#include "kvm_cache_regs.h"
40#include "irq.h"
41#include "trace.h"
42#include "x86.h"
43#include "cpuid.h"
44
45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
70#define APIC_VECTORS_PER_REG 32
71
72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
77
78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
116struct static_key_deferred apic_hw_disabled __read_mostly;
117struct static_key_deferred apic_sw_disabled __read_mostly;
118
119static inline int apic_enabled(struct kvm_lapic *apic)
120{
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
122}
123
124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
134}
135
136
137
138
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
174 u32 ldr, aid;
175
176 if (!kvm_apic_present(vcpu))
177 continue;
178
179 aid = kvm_apic_id(apic);
180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
181
182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
184
185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
196 continue;
197
198 apic_logical_id(new, ldr, &cid, &lid);
199
200 if (lid && cid < ARRAY_SIZE(new->logical_map))
201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
211
212 kvm_vcpu_request_scan_ioapic(kvm);
213}
214
215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
218
219 apic_set_reg(apic, APIC_SPIV, val);
220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
243static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
244{
245 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
246}
247
248static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
249{
250 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
251}
252
253static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
254{
255 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
256}
257
258static inline int apic_lvtt_period(struct kvm_lapic *apic)
259{
260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
261}
262
263static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
264{
265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
266}
267
268static inline int apic_lvt_nmi_mode(u32 lvt_val)
269{
270 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
271}
272
273void kvm_apic_set_version(struct kvm_vcpu *vcpu)
274{
275 struct kvm_lapic *apic = vcpu->arch.apic;
276 struct kvm_cpuid_entry2 *feat;
277 u32 v = APIC_VERSION;
278
279 if (!kvm_vcpu_has_lapic(vcpu))
280 return;
281
282 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
283 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
284 v |= APIC_LVR_DIRECTED_EOI;
285 apic_set_reg(apic, APIC_LVR, v);
286}
287
288static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
289 LVT_MASK ,
290 LVT_MASK | APIC_MODE_MASK,
291 LVT_MASK | APIC_MODE_MASK,
292 LINT_MASK, LINT_MASK,
293 LVT_MASK
294};
295
296static int find_highest_vector(void *bitmap)
297{
298 int vec;
299 u32 *reg;
300
301 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
302 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
303 reg = bitmap + REG_POS(vec);
304 if (*reg)
305 return fls(*reg) - 1 + vec;
306 }
307
308 return -1;
309}
310
311static u8 count_vectors(void *bitmap)
312{
313 int vec;
314 u32 *reg;
315 u8 count = 0;
316
317 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 count += hweight32(*reg);
320 }
321
322 return count;
323}
324
325void __kvm_apic_update_irr(u32 *pir, void *regs)
326{
327 u32 i, pir_val;
328
329 for (i = 0; i <= 7; i++) {
330 pir_val = xchg(&pir[i], 0);
331 if (pir_val)
332 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
333 }
334}
335EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
336
337void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
338{
339 struct kvm_lapic *apic = vcpu->arch.apic;
340
341 __kvm_apic_update_irr(pir, apic->regs);
342}
343EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
344
345static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
346{
347 apic_set_vector(vec, apic->regs + APIC_IRR);
348
349
350
351
352 apic->irr_pending = true;
353}
354
355static inline int apic_search_irr(struct kvm_lapic *apic)
356{
357 return find_highest_vector(apic->regs + APIC_IRR);
358}
359
360static inline int apic_find_highest_irr(struct kvm_lapic *apic)
361{
362 int result;
363
364
365
366
367
368 if (!apic->irr_pending)
369 return -1;
370
371 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
372 result = apic_search_irr(apic);
373 ASSERT(result == -1 || result >= 16);
374
375 return result;
376}
377
378static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
379{
380 struct kvm_vcpu *vcpu;
381
382 vcpu = apic->vcpu;
383
384 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
385
386 apic_clear_vector(vec, apic->regs + APIC_IRR);
387 kvm_make_request(KVM_REQ_EVENT, vcpu);
388 } else {
389 apic->irr_pending = false;
390 apic_clear_vector(vec, apic->regs + APIC_IRR);
391 if (apic_search_irr(apic) != -1)
392 apic->irr_pending = true;
393 }
394}
395
396static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
397{
398 struct kvm_vcpu *vcpu;
399
400 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
401 return;
402
403 vcpu = apic->vcpu;
404
405
406
407
408
409
410 if (unlikely(kvm_x86_ops->hwapic_isr_update))
411 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
412 else {
413 ++apic->isr_count;
414 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
415
416
417
418
419
420 apic->highest_isr_cache = vec;
421 }
422}
423
424static inline int apic_find_highest_isr(struct kvm_lapic *apic)
425{
426 int result;
427
428
429
430
431
432 if (!apic->isr_count)
433 return -1;
434 if (likely(apic->highest_isr_cache != -1))
435 return apic->highest_isr_cache;
436
437 result = find_highest_vector(apic->regs + APIC_ISR);
438 ASSERT(result == -1 || result >= 16);
439
440 return result;
441}
442
443static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
444{
445 struct kvm_vcpu *vcpu;
446 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
447 return;
448
449 vcpu = apic->vcpu;
450
451
452
453
454
455
456
457
458 if (unlikely(kvm_x86_ops->hwapic_isr_update))
459 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
460 apic_find_highest_isr(apic));
461 else {
462 --apic->isr_count;
463 BUG_ON(apic->isr_count < 0);
464 apic->highest_isr_cache = -1;
465 }
466}
467
468int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
469{
470 int highest_irr;
471
472
473
474
475
476
477 if (!kvm_vcpu_has_lapic(vcpu))
478 return 0;
479 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
480
481 return highest_irr;
482}
483
484static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
485 int vector, int level, int trig_mode,
486 unsigned long *dest_map);
487
488int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
489 unsigned long *dest_map)
490{
491 struct kvm_lapic *apic = vcpu->arch.apic;
492
493 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
494 irq->level, irq->trig_mode, dest_map);
495}
496
497static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
498{
499
500 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
501 sizeof(val));
502}
503
504static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
505{
506
507 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
508 sizeof(*val));
509}
510
511static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
512{
513 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
514}
515
516static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
517{
518 u8 val;
519 if (pv_eoi_get_user(vcpu, &val) < 0)
520 apic_debug("Can't read EOI MSR value: 0x%llx\n",
521 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
522 return val & 0x1;
523}
524
525static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
526{
527 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
528 apic_debug("Can't set EOI MSR value: 0x%llx\n",
529 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
530 return;
531 }
532 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
533}
534
535static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
536{
537 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
538 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
539 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
540 return;
541 }
542 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
543}
544
545void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
546{
547 struct kvm_lapic *apic = vcpu->arch.apic;
548 int i;
549
550 for (i = 0; i < 8; i++)
551 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
552}
553
554static void apic_update_ppr(struct kvm_lapic *apic)
555{
556 u32 tpr, isrv, ppr, old_ppr;
557 int isr;
558
559 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
560 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
561 isr = apic_find_highest_isr(apic);
562 isrv = (isr != -1) ? isr : 0;
563
564 if ((tpr & 0xf0) >= (isrv & 0xf0))
565 ppr = tpr & 0xff;
566 else
567 ppr = isrv & 0xf0;
568
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic, ppr, isr, isrv);
571
572 if (old_ppr != ppr) {
573 apic_set_reg(apic, APIC_PROCPRI, ppr);
574 if (ppr < old_ppr)
575 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
576 }
577}
578
579static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
580{
581 apic_set_reg(apic, APIC_TASKPRI, tpr);
582 apic_update_ppr(apic);
583}
584
585static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
586{
587 if (apic_x2apic_mode(apic))
588 return mda == X2APIC_BROADCAST;
589
590 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
591}
592
593static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
594{
595 if (kvm_apic_broadcast(apic, mda))
596 return true;
597
598 if (apic_x2apic_mode(apic))
599 return mda == kvm_apic_id(apic);
600
601 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
602}
603
604static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
605{
606 u32 logical_id;
607
608 if (kvm_apic_broadcast(apic, mda))
609 return true;
610
611 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
612
613 if (apic_x2apic_mode(apic))
614 return ((logical_id >> 16) == (mda >> 16))
615 && (logical_id & mda & 0xffff) != 0;
616
617 logical_id = GET_APIC_LOGICAL_ID(logical_id);
618 mda = GET_APIC_DEST_FIELD(mda);
619
620 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
621 case APIC_DFR_FLAT:
622 return (logical_id & mda) != 0;
623 case APIC_DFR_CLUSTER:
624 return ((logical_id >> 4) == (mda >> 4))
625 && (logical_id & mda & 0xf) != 0;
626 default:
627 apic_debug("Bad DFR vcpu %d: %08x\n",
628 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
629 return false;
630 }
631}
632
633
634
635
636
637static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
638 struct kvm_lapic *target)
639{
640 bool ipi = source != NULL;
641 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
642
643 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
644 return X2APIC_BROADCAST;
645
646 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
647}
648
649bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
650 int short_hand, unsigned int dest, int dest_mode)
651{
652 struct kvm_lapic *target = vcpu->arch.apic;
653 u32 mda = kvm_apic_mda(dest, source, target);
654
655 apic_debug("target %p, source %p, dest 0x%x, "
656 "dest_mode 0x%x, short_hand 0x%x\n",
657 target, source, dest, dest_mode, short_hand);
658
659 ASSERT(target);
660 switch (short_hand) {
661 case APIC_DEST_NOSHORT:
662 if (dest_mode == APIC_DEST_PHYSICAL)
663 return kvm_apic_match_physical_addr(target, mda);
664 else
665 return kvm_apic_match_logical_addr(target, mda);
666 case APIC_DEST_SELF:
667 return target == source;
668 case APIC_DEST_ALLINC:
669 return true;
670 case APIC_DEST_ALLBUT:
671 return target != source;
672 default:
673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
674 short_hand);
675 return false;
676 }
677}
678
679bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
680 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
681{
682 struct kvm_apic_map *map;
683 unsigned long bitmap = 1;
684 struct kvm_lapic **dst;
685 int i;
686 bool ret, x2apic_ipi;
687
688 *r = -1;
689
690 if (irq->shorthand == APIC_DEST_SELF) {
691 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
692 return true;
693 }
694
695 if (irq->shorthand)
696 return false;
697
698 x2apic_ipi = src && apic_x2apic_mode(src);
699 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
700 return false;
701
702 ret = true;
703 rcu_read_lock();
704 map = rcu_dereference(kvm->arch.apic_map);
705
706 if (!map) {
707 ret = false;
708 goto out;
709 }
710
711 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
712 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
713 goto out;
714
715 dst = &map->phys_map[irq->dest_id];
716 } else {
717 u16 cid;
718
719 if (!kvm_apic_logical_map_valid(map)) {
720 ret = false;
721 goto out;
722 }
723
724 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
725
726 if (cid >= ARRAY_SIZE(map->logical_map))
727 goto out;
728
729 dst = map->logical_map[cid];
730
731 if (irq->delivery_mode == APIC_DM_LOWEST) {
732 int l = -1;
733 for_each_set_bit(i, &bitmap, 16) {
734 if (!dst[i])
735 continue;
736 if (l < 0)
737 l = i;
738 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
739 l = i;
740 }
741
742 bitmap = (l >= 0) ? 1 << l : 0;
743 }
744 }
745
746 for_each_set_bit(i, &bitmap, 16) {
747 if (!dst[i])
748 continue;
749 if (*r < 0)
750 *r = 0;
751 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
752 }
753out:
754 rcu_read_unlock();
755 return ret;
756}
757
758
759
760
761
762static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
763 int vector, int level, int trig_mode,
764 unsigned long *dest_map)
765{
766 int result = 0;
767 struct kvm_vcpu *vcpu = apic->vcpu;
768
769 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
770 trig_mode, vector);
771 switch (delivery_mode) {
772 case APIC_DM_LOWEST:
773 vcpu->arch.apic_arb_prio++;
774 case APIC_DM_FIXED:
775
776 if (unlikely(!apic_enabled(apic)))
777 break;
778
779 result = 1;
780
781 if (dest_map)
782 __set_bit(vcpu->vcpu_id, dest_map);
783
784 if (kvm_x86_ops->deliver_posted_interrupt)
785 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
786 else {
787 apic_set_irr(vector, apic);
788
789 kvm_make_request(KVM_REQ_EVENT, vcpu);
790 kvm_vcpu_kick(vcpu);
791 }
792 break;
793
794 case APIC_DM_REMRD:
795 result = 1;
796 vcpu->arch.pv.pv_unhalted = 1;
797 kvm_make_request(KVM_REQ_EVENT, vcpu);
798 kvm_vcpu_kick(vcpu);
799 break;
800
801 case APIC_DM_SMI:
802 apic_debug("Ignoring guest SMI\n");
803 break;
804
805 case APIC_DM_NMI:
806 result = 1;
807 kvm_inject_nmi(vcpu);
808 kvm_vcpu_kick(vcpu);
809 break;
810
811 case APIC_DM_INIT:
812 if (!trig_mode || level) {
813 result = 1;
814
815 apic->pending_events = (1UL << KVM_APIC_INIT);
816
817
818 smp_wmb();
819 kvm_make_request(KVM_REQ_EVENT, vcpu);
820 kvm_vcpu_kick(vcpu);
821 } else {
822 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
823 vcpu->vcpu_id);
824 }
825 break;
826
827 case APIC_DM_STARTUP:
828 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
829 vcpu->vcpu_id, vector);
830 result = 1;
831 apic->sipi_vector = vector;
832
833 smp_wmb();
834 set_bit(KVM_APIC_SIPI, &apic->pending_events);
835 kvm_make_request(KVM_REQ_EVENT, vcpu);
836 kvm_vcpu_kick(vcpu);
837 break;
838
839 case APIC_DM_EXTINT:
840
841
842
843
844
845 break;
846
847 default:
848 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
849 delivery_mode);
850 break;
851 }
852 return result;
853}
854
855int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
856{
857 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
858}
859
860static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
861{
862 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
863 int trigger_mode;
864 if (apic_test_vector(vector, apic->regs + APIC_TMR))
865 trigger_mode = IOAPIC_LEVEL_TRIG;
866 else
867 trigger_mode = IOAPIC_EDGE_TRIG;
868 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
869 }
870}
871
872static int apic_set_eoi(struct kvm_lapic *apic)
873{
874 int vector = apic_find_highest_isr(apic);
875
876 trace_kvm_eoi(apic, vector);
877
878
879
880
881
882 if (vector == -1)
883 return vector;
884
885 apic_clear_isr(vector, apic);
886 apic_update_ppr(apic);
887
888 kvm_ioapic_send_eoi(apic, vector);
889 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
890 return vector;
891}
892
893
894
895
896
897void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
898{
899 struct kvm_lapic *apic = vcpu->arch.apic;
900
901 trace_kvm_eoi(apic, vector);
902
903 kvm_ioapic_send_eoi(apic, vector);
904 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
905}
906EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
907
908static void apic_send_ipi(struct kvm_lapic *apic)
909{
910 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
911 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
912 struct kvm_lapic_irq irq;
913
914 irq.vector = icr_low & APIC_VECTOR_MASK;
915 irq.delivery_mode = icr_low & APIC_MODE_MASK;
916 irq.dest_mode = icr_low & APIC_DEST_MASK;
917 irq.level = icr_low & APIC_INT_ASSERT;
918 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
919 irq.shorthand = icr_low & APIC_SHORT_MASK;
920 if (apic_x2apic_mode(apic))
921 irq.dest_id = icr_high;
922 else
923 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
924
925 trace_kvm_apic_ipi(icr_low, irq.dest_id);
926
927 apic_debug("icr_high 0x%x, icr_low 0x%x, "
928 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
929 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
930 icr_high, icr_low, irq.shorthand, irq.dest_id,
931 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
932 irq.vector);
933
934 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
935}
936
937static u32 apic_get_tmcct(struct kvm_lapic *apic)
938{
939 ktime_t remaining;
940 s64 ns;
941 u32 tmcct;
942
943 ASSERT(apic != NULL);
944
945
946 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
947 apic->lapic_timer.period == 0)
948 return 0;
949
950 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
951 if (ktime_to_ns(remaining) < 0)
952 remaining = ktime_set(0, 0);
953
954 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
955 tmcct = div64_u64(ns,
956 (APIC_BUS_CYCLE_NS * apic->divide_count));
957
958 return tmcct;
959}
960
961static void __report_tpr_access(struct kvm_lapic *apic, bool write)
962{
963 struct kvm_vcpu *vcpu = apic->vcpu;
964 struct kvm_run *run = vcpu->run;
965
966 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
967 run->tpr_access.rip = kvm_rip_read(vcpu);
968 run->tpr_access.is_write = write;
969}
970
971static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
972{
973 if (apic->vcpu->arch.tpr_access_reporting)
974 __report_tpr_access(apic, write);
975}
976
977static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
978{
979 u32 val = 0;
980
981 if (offset >= LAPIC_MMIO_LENGTH)
982 return 0;
983
984 switch (offset) {
985 case APIC_ID:
986 if (apic_x2apic_mode(apic))
987 val = kvm_apic_id(apic);
988 else
989 val = kvm_apic_id(apic) << 24;
990 break;
991 case APIC_ARBPRI:
992 apic_debug("Access APIC ARBPRI register which is for P6\n");
993 break;
994
995 case APIC_TMCCT:
996 if (apic_lvtt_tscdeadline(apic))
997 return 0;
998
999 val = apic_get_tmcct(apic);
1000 break;
1001 case APIC_PROCPRI:
1002 apic_update_ppr(apic);
1003 val = kvm_apic_get_reg(apic, offset);
1004 break;
1005 case APIC_TASKPRI:
1006 report_tpr_access(apic, false);
1007
1008 default:
1009 val = kvm_apic_get_reg(apic, offset);
1010 break;
1011 }
1012
1013 return val;
1014}
1015
1016static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1017{
1018 return container_of(dev, struct kvm_lapic, dev);
1019}
1020
1021static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1022 void *data)
1023{
1024 unsigned char alignment = offset & 0xf;
1025 u32 result;
1026
1027 static const u64 rmask = 0x43ff01ffffffe70cULL;
1028
1029 if ((alignment + len) > 4) {
1030 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1031 offset, len);
1032 return 1;
1033 }
1034
1035 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1036 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1037 offset);
1038 return 1;
1039 }
1040
1041 result = __apic_read(apic, offset & ~0xf);
1042
1043 trace_kvm_apic_read(offset, result);
1044
1045 switch (len) {
1046 case 1:
1047 case 2:
1048 case 4:
1049 memcpy(data, (char *)&result + alignment, len);
1050 break;
1051 default:
1052 printk(KERN_ERR "Local APIC read with len = %x, "
1053 "should be 1,2, or 4 instead\n", len);
1054 break;
1055 }
1056 return 0;
1057}
1058
1059static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1060{
1061 return kvm_apic_hw_enabled(apic) &&
1062 addr >= apic->base_address &&
1063 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1064}
1065
1066static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1067 gpa_t address, int len, void *data)
1068{
1069 struct kvm_lapic *apic = to_lapic(this);
1070 u32 offset = address - apic->base_address;
1071
1072 if (!apic_mmio_in_range(apic, address))
1073 return -EOPNOTSUPP;
1074
1075 apic_reg_read(apic, offset, len, data);
1076
1077 return 0;
1078}
1079
1080static void update_divide_count(struct kvm_lapic *apic)
1081{
1082 u32 tmp1, tmp2, tdcr;
1083
1084 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1085 tmp1 = tdcr & 0xf;
1086 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1087 apic->divide_count = 0x1 << (tmp2 & 0x7);
1088
1089 apic_debug("timer divide count is 0x%x\n",
1090 apic->divide_count);
1091}
1092
1093static void apic_update_lvtt(struct kvm_lapic *apic)
1094{
1095 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1096 apic->lapic_timer.timer_mode_mask;
1097
1098 if (apic->lapic_timer.timer_mode != timer_mode) {
1099 apic->lapic_timer.timer_mode = timer_mode;
1100 hrtimer_cancel(&apic->lapic_timer.timer);
1101 }
1102}
1103
1104static void apic_timer_expired(struct kvm_lapic *apic)
1105{
1106 struct kvm_vcpu *vcpu = apic->vcpu;
1107 wait_queue_head_t *q = &vcpu->wq;
1108 struct kvm_timer *ktimer = &apic->lapic_timer;
1109
1110 if (atomic_read(&apic->lapic_timer.pending))
1111 return;
1112
1113 atomic_inc(&apic->lapic_timer.pending);
1114 kvm_set_pending_timer(vcpu);
1115
1116 if (waitqueue_active(q))
1117 wake_up_interruptible(q);
1118
1119 if (apic_lvtt_tscdeadline(apic))
1120 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1121}
1122
1123
1124
1125
1126
1127
1128static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1129{
1130 struct kvm_lapic *apic = vcpu->arch.apic;
1131 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1132
1133 if (kvm_apic_hw_enabled(apic)) {
1134 int vec = reg & APIC_VECTOR_MASK;
1135 void *bitmap = apic->regs + APIC_ISR;
1136
1137 if (kvm_x86_ops->deliver_posted_interrupt)
1138 bitmap = apic->regs + APIC_IRR;
1139
1140 if (apic_test_vector(vec, bitmap))
1141 return true;
1142 }
1143 return false;
1144}
1145
1146void wait_lapic_expire(struct kvm_vcpu *vcpu)
1147{
1148 struct kvm_lapic *apic = vcpu->arch.apic;
1149 u64 guest_tsc, tsc_deadline;
1150
1151 if (!kvm_vcpu_has_lapic(vcpu))
1152 return;
1153
1154 if (apic->lapic_timer.expired_tscdeadline == 0)
1155 return;
1156
1157 if (!lapic_timer_int_injected(vcpu))
1158 return;
1159
1160 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1161 apic->lapic_timer.expired_tscdeadline = 0;
1162 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1163 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1164
1165
1166 if (guest_tsc < tsc_deadline)
1167 __delay(tsc_deadline - guest_tsc);
1168}
1169
1170static void start_apic_timer(struct kvm_lapic *apic)
1171{
1172 ktime_t now;
1173
1174 atomic_set(&apic->lapic_timer.pending, 0);
1175
1176 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1177
1178 now = apic->lapic_timer.timer.base->get_time();
1179 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1180 * APIC_BUS_CYCLE_NS * apic->divide_count;
1181
1182 if (!apic->lapic_timer.period)
1183 return;
1184
1185
1186
1187
1188
1189 if (apic_lvtt_period(apic)) {
1190 s64 min_period = min_timer_period_us * 1000LL;
1191
1192 if (apic->lapic_timer.period < min_period) {
1193 pr_info_ratelimited(
1194 "kvm: vcpu %i: requested %lld ns "
1195 "lapic timer period limited to %lld ns\n",
1196 apic->vcpu->vcpu_id,
1197 apic->lapic_timer.period, min_period);
1198 apic->lapic_timer.period = min_period;
1199 }
1200 }
1201
1202 hrtimer_start(&apic->lapic_timer.timer,
1203 ktime_add_ns(now, apic->lapic_timer.period),
1204 HRTIMER_MODE_ABS);
1205
1206 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1207 PRIx64 ", "
1208 "timer initial count 0x%x, period %lldns, "
1209 "expire @ 0x%016" PRIx64 ".\n", __func__,
1210 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1211 kvm_apic_get_reg(apic, APIC_TMICT),
1212 apic->lapic_timer.period,
1213 ktime_to_ns(ktime_add_ns(now,
1214 apic->lapic_timer.period)));
1215 } else if (apic_lvtt_tscdeadline(apic)) {
1216
1217 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1218 u64 ns = 0;
1219 ktime_t expire;
1220 struct kvm_vcpu *vcpu = apic->vcpu;
1221 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1222 unsigned long flags;
1223
1224 if (unlikely(!tscdeadline || !this_tsc_khz))
1225 return;
1226
1227 local_irq_save(flags);
1228
1229 now = apic->lapic_timer.timer.base->get_time();
1230 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1231 if (likely(tscdeadline > guest_tsc)) {
1232 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1233 do_div(ns, this_tsc_khz);
1234 expire = ktime_add_ns(now, ns);
1235 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1236 hrtimer_start(&apic->lapic_timer.timer,
1237 expire, HRTIMER_MODE_ABS);
1238 } else
1239 apic_timer_expired(apic);
1240
1241 local_irq_restore(flags);
1242 }
1243}
1244
1245static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1246{
1247 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1248
1249 if (apic_lvt_nmi_mode(lvt0_val)) {
1250 if (!nmi_wd_enabled) {
1251 apic_debug("Receive NMI setting on APIC_LVT0 "
1252 "for cpu %d\n", apic->vcpu->vcpu_id);
1253 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1254 }
1255 } else if (nmi_wd_enabled)
1256 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1257}
1258
1259static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1260{
1261 int ret = 0;
1262
1263 trace_kvm_apic_write(reg, val);
1264
1265 switch (reg) {
1266 case APIC_ID:
1267 if (!apic_x2apic_mode(apic))
1268 kvm_apic_set_id(apic, val >> 24);
1269 else
1270 ret = 1;
1271 break;
1272
1273 case APIC_TASKPRI:
1274 report_tpr_access(apic, true);
1275 apic_set_tpr(apic, val & 0xff);
1276 break;
1277
1278 case APIC_EOI:
1279 apic_set_eoi(apic);
1280 break;
1281
1282 case APIC_LDR:
1283 if (!apic_x2apic_mode(apic))
1284 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1285 else
1286 ret = 1;
1287 break;
1288
1289 case APIC_DFR:
1290 if (!apic_x2apic_mode(apic)) {
1291 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1292 recalculate_apic_map(apic->vcpu->kvm);
1293 } else
1294 ret = 1;
1295 break;
1296
1297 case APIC_SPIV: {
1298 u32 mask = 0x3ff;
1299 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1300 mask |= APIC_SPIV_DIRECTED_EOI;
1301 apic_set_spiv(apic, val & mask);
1302 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1303 int i;
1304 u32 lvt_val;
1305
1306 for (i = 0; i < APIC_LVT_NUM; i++) {
1307 lvt_val = kvm_apic_get_reg(apic,
1308 APIC_LVTT + 0x10 * i);
1309 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1310 lvt_val | APIC_LVT_MASKED);
1311 }
1312 apic_update_lvtt(apic);
1313 atomic_set(&apic->lapic_timer.pending, 0);
1314
1315 }
1316 break;
1317 }
1318 case APIC_ICR:
1319
1320 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1321 apic_send_ipi(apic);
1322 break;
1323
1324 case APIC_ICR2:
1325 if (!apic_x2apic_mode(apic))
1326 val &= 0xff000000;
1327 apic_set_reg(apic, APIC_ICR2, val);
1328 break;
1329
1330 case APIC_LVT0:
1331 apic_manage_nmi_watchdog(apic, val);
1332 case APIC_LVTTHMR:
1333 case APIC_LVTPC:
1334 case APIC_LVT1:
1335 case APIC_LVTERR:
1336
1337 if (!kvm_apic_sw_enabled(apic))
1338 val |= APIC_LVT_MASKED;
1339
1340 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1341 apic_set_reg(apic, reg, val);
1342
1343 break;
1344
1345 case APIC_LVTT:
1346 if (!kvm_apic_sw_enabled(apic))
1347 val |= APIC_LVT_MASKED;
1348 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1349 apic_set_reg(apic, APIC_LVTT, val);
1350 apic_update_lvtt(apic);
1351 break;
1352
1353 case APIC_TMICT:
1354 if (apic_lvtt_tscdeadline(apic))
1355 break;
1356
1357 hrtimer_cancel(&apic->lapic_timer.timer);
1358 apic_set_reg(apic, APIC_TMICT, val);
1359 start_apic_timer(apic);
1360 break;
1361
1362 case APIC_TDCR:
1363 if (val & 4)
1364 apic_debug("KVM_WRITE:TDCR %x\n", val);
1365 apic_set_reg(apic, APIC_TDCR, val);
1366 update_divide_count(apic);
1367 break;
1368
1369 case APIC_ESR:
1370 if (apic_x2apic_mode(apic) && val != 0) {
1371 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1372 ret = 1;
1373 }
1374 break;
1375
1376 case APIC_SELF_IPI:
1377 if (apic_x2apic_mode(apic)) {
1378 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1379 } else
1380 ret = 1;
1381 break;
1382 default:
1383 ret = 1;
1384 break;
1385 }
1386 if (ret)
1387 apic_debug("Local APIC Write to read-only register %x\n", reg);
1388 return ret;
1389}
1390
1391static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1392 gpa_t address, int len, const void *data)
1393{
1394 struct kvm_lapic *apic = to_lapic(this);
1395 unsigned int offset = address - apic->base_address;
1396 u32 val;
1397
1398 if (!apic_mmio_in_range(apic, address))
1399 return -EOPNOTSUPP;
1400
1401
1402
1403
1404
1405
1406 if (len != 4 || (offset & 0xf)) {
1407
1408 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1409 return 0;
1410 }
1411
1412 val = *(u32*)data;
1413
1414
1415 if (offset != APIC_EOI)
1416 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1417 "0x%x\n", __func__, offset, len, val);
1418
1419 apic_reg_write(apic, offset & 0xff0, val);
1420
1421 return 0;
1422}
1423
1424void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1425{
1426 if (kvm_vcpu_has_lapic(vcpu))
1427 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1428}
1429EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1430
1431
1432void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1433{
1434 u32 val = 0;
1435
1436
1437 offset &= 0xff0;
1438
1439 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1440
1441
1442 apic_reg_write(vcpu->arch.apic, offset, val);
1443}
1444EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1445
1446void kvm_free_lapic(struct kvm_vcpu *vcpu)
1447{
1448 struct kvm_lapic *apic = vcpu->arch.apic;
1449
1450 if (!vcpu->arch.apic)
1451 return;
1452
1453 hrtimer_cancel(&apic->lapic_timer.timer);
1454
1455 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1456 static_key_slow_dec_deferred(&apic_hw_disabled);
1457
1458 if (!apic->sw_enabled)
1459 static_key_slow_dec_deferred(&apic_sw_disabled);
1460
1461 if (apic->regs)
1462 free_page((unsigned long)apic->regs);
1463
1464 kfree(apic);
1465}
1466
1467
1468
1469
1470
1471
1472
1473u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1474{
1475 struct kvm_lapic *apic = vcpu->arch.apic;
1476
1477 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1478 apic_lvtt_period(apic))
1479 return 0;
1480
1481 return apic->lapic_timer.tscdeadline;
1482}
1483
1484void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1485{
1486 struct kvm_lapic *apic = vcpu->arch.apic;
1487
1488 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1489 apic_lvtt_period(apic))
1490 return;
1491
1492 hrtimer_cancel(&apic->lapic_timer.timer);
1493 apic->lapic_timer.tscdeadline = data;
1494 start_apic_timer(apic);
1495}
1496
1497void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1498{
1499 struct kvm_lapic *apic = vcpu->arch.apic;
1500
1501 if (!kvm_vcpu_has_lapic(vcpu))
1502 return;
1503
1504 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1505 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1506}
1507
1508u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1509{
1510 u64 tpr;
1511
1512 if (!kvm_vcpu_has_lapic(vcpu))
1513 return 0;
1514
1515 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1516
1517 return (tpr & 0xf0) >> 4;
1518}
1519
1520void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1521{
1522 u64 old_value = vcpu->arch.apic_base;
1523 struct kvm_lapic *apic = vcpu->arch.apic;
1524
1525 if (!apic) {
1526 value |= MSR_IA32_APICBASE_BSP;
1527 vcpu->arch.apic_base = value;
1528 return;
1529 }
1530
1531 vcpu->arch.apic_base = value;
1532
1533
1534 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1535 if (value & MSR_IA32_APICBASE_ENABLE)
1536 static_key_slow_dec_deferred(&apic_hw_disabled);
1537 else
1538 static_key_slow_inc(&apic_hw_disabled.key);
1539 recalculate_apic_map(vcpu->kvm);
1540 }
1541
1542 if ((old_value ^ value) & X2APIC_ENABLE) {
1543 if (value & X2APIC_ENABLE) {
1544 u32 id = kvm_apic_id(apic);
1545 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1546 kvm_apic_set_ldr(apic, ldr);
1547 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1548 } else
1549 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1550 }
1551
1552 apic->base_address = apic->vcpu->arch.apic_base &
1553 MSR_IA32_APICBASE_BASE;
1554
1555 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1556 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1557 pr_warn_once("APIC base relocation is unsupported by KVM");
1558
1559
1560 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1561 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1562
1563}
1564
1565void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1566{
1567 struct kvm_lapic *apic;
1568 int i;
1569
1570 apic_debug("%s\n", __func__);
1571
1572 ASSERT(vcpu);
1573 apic = vcpu->arch.apic;
1574 ASSERT(apic != NULL);
1575
1576
1577 hrtimer_cancel(&apic->lapic_timer.timer);
1578
1579 kvm_apic_set_id(apic, vcpu->vcpu_id);
1580 kvm_apic_set_version(apic->vcpu);
1581
1582 for (i = 0; i < APIC_LVT_NUM; i++)
1583 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1584 apic_update_lvtt(apic);
1585 apic_set_reg(apic, APIC_LVT0,
1586 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1587
1588 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1589 apic_set_spiv(apic, 0xff);
1590 apic_set_reg(apic, APIC_TASKPRI, 0);
1591 kvm_apic_set_ldr(apic, 0);
1592 apic_set_reg(apic, APIC_ESR, 0);
1593 apic_set_reg(apic, APIC_ICR, 0);
1594 apic_set_reg(apic, APIC_ICR2, 0);
1595 apic_set_reg(apic, APIC_TDCR, 0);
1596 apic_set_reg(apic, APIC_TMICT, 0);
1597 for (i = 0; i < 8; i++) {
1598 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1599 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1600 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1601 }
1602 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1603 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1604 apic->highest_isr_cache = -1;
1605 update_divide_count(apic);
1606 atomic_set(&apic->lapic_timer.pending, 0);
1607 if (kvm_vcpu_is_bsp(vcpu))
1608 kvm_lapic_set_base(vcpu,
1609 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1610 vcpu->arch.pv_eoi.msr_val = 0;
1611 apic_update_ppr(apic);
1612
1613 vcpu->arch.apic_arb_prio = 0;
1614 vcpu->arch.apic_attention = 0;
1615
1616 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1617 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1618 vcpu, kvm_apic_id(apic),
1619 vcpu->arch.apic_base, apic->base_address);
1620}
1621
1622
1623
1624
1625
1626
1627
1628static bool lapic_is_periodic(struct kvm_lapic *apic)
1629{
1630 return apic_lvtt_period(apic);
1631}
1632
1633int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1634{
1635 struct kvm_lapic *apic = vcpu->arch.apic;
1636
1637 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1638 apic_lvt_enabled(apic, APIC_LVTT))
1639 return atomic_read(&apic->lapic_timer.pending);
1640
1641 return 0;
1642}
1643
1644int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1645{
1646 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1647 int vector, mode, trig_mode;
1648
1649 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1650 vector = reg & APIC_VECTOR_MASK;
1651 mode = reg & APIC_MODE_MASK;
1652 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1653 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1654 NULL);
1655 }
1656 return 0;
1657}
1658
1659void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1660{
1661 struct kvm_lapic *apic = vcpu->arch.apic;
1662
1663 if (apic)
1664 kvm_apic_local_deliver(apic, APIC_LVT0);
1665}
1666
1667static const struct kvm_io_device_ops apic_mmio_ops = {
1668 .read = apic_mmio_read,
1669 .write = apic_mmio_write,
1670};
1671
1672static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1673{
1674 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1675 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1676
1677 apic_timer_expired(apic);
1678
1679 if (lapic_is_periodic(apic)) {
1680 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1681 return HRTIMER_RESTART;
1682 } else
1683 return HRTIMER_NORESTART;
1684}
1685
1686int kvm_create_lapic(struct kvm_vcpu *vcpu)
1687{
1688 struct kvm_lapic *apic;
1689
1690 ASSERT(vcpu != NULL);
1691 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1692
1693 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1694 if (!apic)
1695 goto nomem;
1696
1697 vcpu->arch.apic = apic;
1698
1699 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1700 if (!apic->regs) {
1701 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1702 vcpu->vcpu_id);
1703 goto nomem_free_apic;
1704 }
1705 apic->vcpu = vcpu;
1706
1707 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1708 HRTIMER_MODE_ABS);
1709 apic->lapic_timer.timer.function = apic_timer_fn;
1710
1711
1712
1713
1714
1715 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1716 kvm_lapic_set_base(vcpu,
1717 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1718
1719 static_key_slow_inc(&apic_sw_disabled.key);
1720 kvm_lapic_reset(vcpu);
1721 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1722
1723 return 0;
1724nomem_free_apic:
1725 kfree(apic);
1726nomem:
1727 return -ENOMEM;
1728}
1729
1730int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1731{
1732 struct kvm_lapic *apic = vcpu->arch.apic;
1733 int highest_irr;
1734
1735 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1736 return -1;
1737
1738 apic_update_ppr(apic);
1739 highest_irr = apic_find_highest_irr(apic);
1740 if ((highest_irr == -1) ||
1741 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1742 return -1;
1743 return highest_irr;
1744}
1745
1746int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1747{
1748 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1749 int r = 0;
1750
1751 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1752 r = 1;
1753 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1754 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1755 r = 1;
1756 return r;
1757}
1758
1759void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1760{
1761 struct kvm_lapic *apic = vcpu->arch.apic;
1762
1763 if (!kvm_vcpu_has_lapic(vcpu))
1764 return;
1765
1766 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1767 kvm_apic_local_deliver(apic, APIC_LVTT);
1768 if (apic_lvtt_tscdeadline(apic))
1769 apic->lapic_timer.tscdeadline = 0;
1770 atomic_set(&apic->lapic_timer.pending, 0);
1771 }
1772}
1773
1774int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1775{
1776 int vector = kvm_apic_has_interrupt(vcpu);
1777 struct kvm_lapic *apic = vcpu->arch.apic;
1778
1779 if (vector == -1)
1780 return -1;
1781
1782
1783
1784
1785
1786
1787
1788
1789 apic_set_isr(vector, apic);
1790 apic_update_ppr(apic);
1791 apic_clear_irr(vector, apic);
1792 return vector;
1793}
1794
1795void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1796 struct kvm_lapic_state *s)
1797{
1798 struct kvm_lapic *apic = vcpu->arch.apic;
1799
1800 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1801
1802 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1803 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1804
1805 kvm_apic_set_id(apic, kvm_apic_id(apic));
1806 kvm_apic_set_version(vcpu);
1807
1808 apic_update_ppr(apic);
1809 hrtimer_cancel(&apic->lapic_timer.timer);
1810 apic_update_lvtt(apic);
1811 update_divide_count(apic);
1812 start_apic_timer(apic);
1813 apic->irr_pending = true;
1814 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1815 1 : count_vectors(apic->regs + APIC_ISR);
1816 apic->highest_isr_cache = -1;
1817 if (kvm_x86_ops->hwapic_irr_update)
1818 kvm_x86_ops->hwapic_irr_update(vcpu,
1819 apic_find_highest_irr(apic));
1820 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1821 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1822 apic_find_highest_isr(apic));
1823 kvm_make_request(KVM_REQ_EVENT, vcpu);
1824 kvm_rtc_eoi_tracking_restore_one(vcpu);
1825}
1826
1827void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1828{
1829 struct hrtimer *timer;
1830
1831 if (!kvm_vcpu_has_lapic(vcpu))
1832 return;
1833
1834 timer = &vcpu->arch.apic->lapic_timer.timer;
1835 if (hrtimer_cancel(timer))
1836 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1837}
1838
1839
1840
1841
1842
1843
1844
1845
1846static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1847 struct kvm_lapic *apic)
1848{
1849 bool pending;
1850 int vector;
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862 BUG_ON(!pv_eoi_enabled(vcpu));
1863 pending = pv_eoi_get_pending(vcpu);
1864
1865
1866
1867
1868
1869 pv_eoi_clr_pending(vcpu);
1870 if (pending)
1871 return;
1872 vector = apic_set_eoi(apic);
1873 trace_kvm_pv_eoi(apic, vector);
1874}
1875
1876void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1877{
1878 u32 data;
1879
1880 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1881 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1882
1883 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1884 return;
1885
1886 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1887 sizeof(u32));
1888
1889 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1890}
1891
1892
1893
1894
1895
1896
1897
1898static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1899 struct kvm_lapic *apic)
1900{
1901 if (!pv_eoi_enabled(vcpu) ||
1902
1903 apic->irr_pending ||
1904
1905 apic->highest_isr_cache == -1 ||
1906
1907 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1908
1909
1910
1911
1912 return;
1913 }
1914
1915 pv_eoi_set_pending(apic->vcpu);
1916}
1917
1918void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1919{
1920 u32 data, tpr;
1921 int max_irr, max_isr;
1922 struct kvm_lapic *apic = vcpu->arch.apic;
1923
1924 apic_sync_pv_eoi_to_guest(vcpu, apic);
1925
1926 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1927 return;
1928
1929 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1930 max_irr = apic_find_highest_irr(apic);
1931 if (max_irr < 0)
1932 max_irr = 0;
1933 max_isr = apic_find_highest_isr(apic);
1934 if (max_isr < 0)
1935 max_isr = 0;
1936 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1937
1938 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1939 sizeof(u32));
1940}
1941
1942int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1943{
1944 if (vapic_addr) {
1945 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1946 &vcpu->arch.apic->vapic_cache,
1947 vapic_addr, sizeof(u32)))
1948 return -EINVAL;
1949 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1950 } else {
1951 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1952 }
1953
1954 vcpu->arch.apic->vapic_addr = vapic_addr;
1955 return 0;
1956}
1957
1958int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1959{
1960 struct kvm_lapic *apic = vcpu->arch.apic;
1961 u32 reg = (msr - APIC_BASE_MSR) << 4;
1962
1963 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1964 return 1;
1965
1966 if (reg == APIC_ICR2)
1967 return 1;
1968
1969
1970 if (reg == APIC_ICR)
1971 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1972 return apic_reg_write(apic, reg, (u32)data);
1973}
1974
1975int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1976{
1977 struct kvm_lapic *apic = vcpu->arch.apic;
1978 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1979
1980 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1981 return 1;
1982
1983 if (reg == APIC_DFR || reg == APIC_ICR2) {
1984 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1985 reg);
1986 return 1;
1987 }
1988
1989 if (apic_reg_read(apic, reg, 4, &low))
1990 return 1;
1991 if (reg == APIC_ICR)
1992 apic_reg_read(apic, APIC_ICR2, 4, &high);
1993
1994 *data = (((u64)high) << 32) | low;
1995
1996 return 0;
1997}
1998
1999int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2000{
2001 struct kvm_lapic *apic = vcpu->arch.apic;
2002
2003 if (!kvm_vcpu_has_lapic(vcpu))
2004 return 1;
2005
2006
2007 if (reg == APIC_ICR)
2008 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2009 return apic_reg_write(apic, reg, (u32)data);
2010}
2011
2012int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2013{
2014 struct kvm_lapic *apic = vcpu->arch.apic;
2015 u32 low, high = 0;
2016
2017 if (!kvm_vcpu_has_lapic(vcpu))
2018 return 1;
2019
2020 if (apic_reg_read(apic, reg, 4, &low))
2021 return 1;
2022 if (reg == APIC_ICR)
2023 apic_reg_read(apic, APIC_ICR2, 4, &high);
2024
2025 *data = (((u64)high) << 32) | low;
2026
2027 return 0;
2028}
2029
2030int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2031{
2032 u64 addr = data & ~KVM_MSR_ENABLED;
2033 if (!IS_ALIGNED(addr, 4))
2034 return 1;
2035
2036 vcpu->arch.pv_eoi.msr_val = data;
2037 if (!pv_eoi_enabled(vcpu))
2038 return 0;
2039 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2040 addr, sizeof(u8));
2041}
2042
2043void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2044{
2045 struct kvm_lapic *apic = vcpu->arch.apic;
2046 u8 sipi_vector;
2047 unsigned long pe;
2048
2049 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2050 return;
2051
2052 pe = xchg(&apic->pending_events, 0);
2053
2054 if (test_bit(KVM_APIC_INIT, &pe)) {
2055 kvm_lapic_reset(vcpu);
2056 kvm_vcpu_reset(vcpu);
2057 if (kvm_vcpu_is_bsp(apic->vcpu))
2058 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2059 else
2060 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2061 }
2062 if (test_bit(KVM_APIC_SIPI, &pe) &&
2063 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2064
2065 smp_rmb();
2066 sipi_vector = apic->sipi_vector;
2067 apic_debug("vcpu %d received sipi with vector # %x\n",
2068 vcpu->vcpu_id, sipi_vector);
2069 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2070 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2071 }
2072}
2073
2074void kvm_lapic_init(void)
2075{
2076
2077 jump_label_rate_limit(&apic_hw_disabled, HZ);
2078 jump_label_rate_limit(&apic_sw_disabled, HZ);
2079}
2080