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12#include <dt-bindings/clock/exynos5440.h>
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/notifier.h>
19#include <linux/reboot.h>
20
21#include "clk.h"
22#include "clk-pll.h"
23
24#define CLKEN_OV_VAL 0xf8
25#define CPU_CLK_STATUS 0xfc
26#define MISC_DOUT1 0x558
27
28static void __iomem *reg_base;
29
30
31PNAME(mout_armclk_p) = { "cplla", "cpllb" };
32PNAME(mout_spi_p) = { "div125", "div200" };
33
34
35static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
36 FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0),
37};
38
39
40static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
41 FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000),
42 FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
43 FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
44 FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
45 FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
46};
47
48
49static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
50 FFACTOR(0, "div250", "ppll", 1, 4, 0),
51 FFACTOR(0, "div200", "ppll", 1, 5, 0),
52 FFACTOR(0, "div125", "div250", 1, 2, 0),
53};
54
55
56static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
57 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
58 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p,
59 CPU_CLK_STATUS, 0, 1, "armclk"),
60};
61
62
63static struct samsung_div_clock exynos5440_div_clks[] __initdata = {
64 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
65};
66
67
68static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
69 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
70 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
71 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
72 GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
73 GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
74 GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
75 GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
76 GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
77 GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
78 GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
79 GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
80 GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
81 GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
82 GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
83 GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
84 GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
85 GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
86 GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
87 GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
88 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
89};
90
91static const struct of_device_id ext_clk_match[] __initconst = {
92 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
93 {},
94};
95
96static int exynos5440_clk_restart_notify(struct notifier_block *this,
97 unsigned long code, void *unused)
98{
99 u32 val, status;
100
101 status = readl_relaxed(reg_base + 0xbc);
102 val = readl_relaxed(reg_base + 0xcc);
103 val = (val & 0xffff0000) | (status & 0xffff);
104 writel_relaxed(val, reg_base + 0xcc);
105
106 return NOTIFY_DONE;
107}
108
109
110
111
112static struct notifier_block exynos5440_clk_restart_handler = {
113 .notifier_call = exynos5440_clk_restart_notify,
114 .priority = 128,
115};
116
117
118static void __init exynos5440_clk_init(struct device_node *np)
119{
120 struct samsung_clk_provider *ctx;
121
122 reg_base = of_iomap(np, 0);
123 if (!reg_base) {
124 pr_err("%s: failed to map clock controller registers,"
125 " aborting clock initialization\n", __func__);
126 return;
127 }
128
129 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
130 if (!ctx)
131 panic("%s: unable to allocate context.\n", __func__);
132
133 samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
134 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
135
136 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
137 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
138
139 samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
140 ARRAY_SIZE(exynos5440_fixed_rate_clks));
141 samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
142 ARRAY_SIZE(exynos5440_fixed_factor_clks));
143 samsung_clk_register_mux(ctx, exynos5440_mux_clks,
144 ARRAY_SIZE(exynos5440_mux_clks));
145 samsung_clk_register_div(ctx, exynos5440_div_clks,
146 ARRAY_SIZE(exynos5440_div_clks));
147 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
148 ARRAY_SIZE(exynos5440_gate_clks));
149
150 samsung_clk_of_add_provider(np, ctx);
151
152 if (register_restart_handler(&exynos5440_clk_restart_handler))
153 pr_warn("exynos5440 clock can't register restart handler\n");
154
155 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
156 pr_info("exynos5440 clock initialization complete\n");
157}
158CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
159
