linux/drivers/clk/socfpga/clk.h
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   1/*
   2 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
   3 *
   4 * based on drivers/clk/tegra/clk.h
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 */
  16
  17#ifndef __SOCFPGA_CLK_H
  18#define __SOCFPGA_CLK_H
  19
  20#include <linux/clk-provider.h>
  21#include <linux/clkdev.h>
  22
  23/* Clock Manager offsets */
  24#define CLKMGR_CTRL             0x0
  25#define CLKMGR_BYPASS           0x4
  26#define CLKMGR_L4SRC            0x70
  27#define CLKMGR_PERPLL_SRC       0xAC
  28
  29#define SOCFPGA_MAX_PARENTS             3
  30#define div_mask(width) ((1 << (width)) - 1)
  31
  32extern void __iomem *clk_mgr_base_addr;
  33
  34void __init socfpga_pll_init(struct device_node *node);
  35void __init socfpga_periph_init(struct device_node *node);
  36void __init socfpga_gate_init(struct device_node *node);
  37
  38struct socfpga_pll {
  39        struct clk_gate hw;
  40};
  41
  42struct socfpga_gate_clk {
  43        struct clk_gate hw;
  44        char *parent_name;
  45        u32 fixed_div;
  46        void __iomem *div_reg;
  47        u32 width;      /* only valid if div_reg != 0 */
  48        u32 shift;      /* only valid if div_reg != 0 */
  49        u32 clk_phase[2];
  50};
  51
  52struct socfpga_periph_clk {
  53        struct clk_gate hw;
  54        char *parent_name;
  55        u32 fixed_div;
  56        void __iomem *div_reg;
  57        u32 width;      /* only valid if div_reg != 0 */
  58        u32 shift;      /* only valid if div_reg != 0 */
  59};
  60
  61#endif /* SOCFPGA_CLK_H */
  62