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18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/time.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clockchips.h>
24#include <linux/clocksource.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/sched_clock.h>
30#include <linux/delay.h>
31
32#include <asm/mach/time.h>
33#include <asm/smp_twd.h>
34
35#define RTC_SECONDS 0x08
36#define RTC_SHADOW_SECONDS 0x0c
37#define RTC_MILLISECONDS 0x10
38
39#define TIMERUS_CNTR_1US 0x10
40#define TIMERUS_USEC_CFG 0x14
41#define TIMERUS_CNTR_FREEZE 0x4c
42
43#define TIMER1_BASE 0x0
44#define TIMER2_BASE 0x8
45#define TIMER3_BASE 0x50
46#define TIMER4_BASE 0x58
47
48#define TIMER_PTV 0x0
49#define TIMER_PCR 0x4
50
51static void __iomem *timer_reg_base;
52static void __iomem *rtc_base;
53
54static struct timespec64 persistent_ts;
55static u64 persistent_ms, last_persistent_ms;
56
57static struct delay_timer tegra_delay_timer;
58
59#define timer_writel(value, reg) \
60 writel_relaxed(value, timer_reg_base + (reg))
61#define timer_readl(reg) \
62 readl_relaxed(timer_reg_base + (reg))
63
64static int tegra_timer_set_next_event(unsigned long cycles,
65 struct clock_event_device *evt)
66{
67 u32 reg;
68
69 reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
70 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
71
72 return 0;
73}
74
75static void tegra_timer_set_mode(enum clock_event_mode mode,
76 struct clock_event_device *evt)
77{
78 u32 reg;
79
80 timer_writel(0, TIMER3_BASE + TIMER_PTV);
81
82 switch (mode) {
83 case CLOCK_EVT_MODE_PERIODIC:
84 reg = 0xC0000000 | ((1000000/HZ)-1);
85 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
86 break;
87 case CLOCK_EVT_MODE_ONESHOT:
88 break;
89 case CLOCK_EVT_MODE_UNUSED:
90 case CLOCK_EVT_MODE_SHUTDOWN:
91 case CLOCK_EVT_MODE_RESUME:
92 break;
93 }
94}
95
96static struct clock_event_device tegra_clockevent = {
97 .name = "timer0",
98 .rating = 300,
99 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
100 .set_next_event = tegra_timer_set_next_event,
101 .set_mode = tegra_timer_set_mode,
102};
103
104static u64 notrace tegra_read_sched_clock(void)
105{
106 return timer_readl(TIMERUS_CNTR_1US);
107}
108
109
110
111
112
113
114
115static u64 tegra_rtc_read_ms(void)
116{
117 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
118 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
119 return (u64)s * MSEC_PER_SEC + ms;
120}
121
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123
124
125
126
127
128
129
130
131
132static void tegra_read_persistent_clock64(struct timespec64 *ts)
133{
134 u64 delta;
135
136 last_persistent_ms = persistent_ms;
137 persistent_ms = tegra_rtc_read_ms();
138 delta = persistent_ms - last_persistent_ms;
139
140 timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
141 *ts = persistent_ts;
142}
143
144static unsigned long tegra_delay_timer_read_counter_long(void)
145{
146 return readl(timer_reg_base + TIMERUS_CNTR_1US);
147}
148
149static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
150{
151 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
152 timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
153 evt->event_handler(evt);
154 return IRQ_HANDLED;
155}
156
157static struct irqaction tegra_timer_irq = {
158 .name = "timer0",
159 .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
160 .handler = tegra_timer_interrupt,
161 .dev_id = &tegra_clockevent,
162};
163
164static void __init tegra20_init_timer(struct device_node *np)
165{
166 struct clk *clk;
167 unsigned long rate;
168 int ret;
169
170 timer_reg_base = of_iomap(np, 0);
171 if (!timer_reg_base) {
172 pr_err("Can't map timer registers\n");
173 BUG();
174 }
175
176 tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
177 if (tegra_timer_irq.irq <= 0) {
178 pr_err("Failed to map timer IRQ\n");
179 BUG();
180 }
181
182 clk = of_clk_get(np, 0);
183 if (IS_ERR(clk)) {
184 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
185 rate = 12000000;
186 } else {
187 clk_prepare_enable(clk);
188 rate = clk_get_rate(clk);
189 }
190
191 switch (rate) {
192 case 12000000:
193 timer_writel(0x000b, TIMERUS_USEC_CFG);
194 break;
195 case 13000000:
196 timer_writel(0x000c, TIMERUS_USEC_CFG);
197 break;
198 case 19200000:
199 timer_writel(0x045f, TIMERUS_USEC_CFG);
200 break;
201 case 26000000:
202 timer_writel(0x0019, TIMERUS_USEC_CFG);
203 break;
204 default:
205 WARN(1, "Unknown clock rate");
206 }
207
208 sched_clock_register(tegra_read_sched_clock, 32, 1000000);
209
210 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
211 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
212 pr_err("Failed to register clocksource\n");
213 BUG();
214 }
215
216 tegra_delay_timer.read_current_timer =
217 tegra_delay_timer_read_counter_long;
218 tegra_delay_timer.freq = 1000000;
219 register_current_timer_delay(&tegra_delay_timer);
220
221 ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
222 if (ret) {
223 pr_err("Failed to register timer IRQ: %d\n", ret);
224 BUG();
225 }
226
227 tegra_clockevent.cpumask = cpu_all_mask;
228 tegra_clockevent.irq = tegra_timer_irq.irq;
229 clockevents_config_and_register(&tegra_clockevent, 1000000,
230 0x1, 0x1fffffff);
231}
232CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
233
234static void __init tegra20_init_rtc(struct device_node *np)
235{
236 struct clk *clk;
237
238 rtc_base = of_iomap(np, 0);
239 if (!rtc_base) {
240 pr_err("Can't map RTC registers");
241 BUG();
242 }
243
244
245
246
247
248 clk = of_clk_get(np, 0);
249 if (IS_ERR(clk))
250 pr_warn("Unable to get rtc-tegra clock\n");
251 else
252 clk_prepare_enable(clk);
253
254 register_persistent_clock(NULL, tegra_read_persistent_clock64);
255}
256CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
257
258#ifdef CONFIG_PM
259static u32 usec_config;
260
261void tegra_timer_suspend(void)
262{
263 usec_config = timer_readl(TIMERUS_USEC_CFG);
264}
265
266void tegra_timer_resume(void)
267{
268 timer_writel(usec_config, TIMERUS_USEC_CFG);
269}
270#endif
271