1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47#ifndef __ICP_QAT_HAL_H
48#define __ICP_QAT_HAL_H
49#include "icp_qat_fw_loader_handle.h"
50
51enum hal_global_csr {
52 MISC_CONTROL = 0x04,
53 ICP_RESET = 0x0c,
54 ICP_GLOBAL_CLK_ENABLE = 0x50
55};
56
57enum hal_ae_csr {
58 USTORE_ADDRESS = 0x000,
59 USTORE_DATA_LOWER = 0x004,
60 USTORE_DATA_UPPER = 0x008,
61 ALU_OUT = 0x010,
62 CTX_ARB_CNTL = 0x014,
63 CTX_ENABLES = 0x018,
64 CC_ENABLE = 0x01c,
65 CSR_CTX_POINTER = 0x020,
66 CTX_STS_INDIRECT = 0x040,
67 ACTIVE_CTX_STATUS = 0x044,
68 CTX_SIG_EVENTS_INDIRECT = 0x048,
69 CTX_SIG_EVENTS_ACTIVE = 0x04c,
70 CTX_WAKEUP_EVENTS_INDIRECT = 0x050,
71 LM_ADDR_0_INDIRECT = 0x060,
72 LM_ADDR_1_INDIRECT = 0x068,
73 INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0,
74 INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8,
75 FUTURE_COUNT_SIGNAL_INDIRECT = 0x078,
76 TIMESTAMP_LOW = 0x0c0,
77 TIMESTAMP_HIGH = 0x0c4,
78 PROFILE_COUNT = 0x144,
79 SIGNATURE_ENABLE = 0x150,
80 AE_MISC_CONTROL = 0x160,
81 LOCAL_CSR_STATUS = 0x180,
82};
83
84#define UA_ECS (0x1 << 31)
85#define ACS_ABO_BITPOS 31
86#define ACS_ACNO 0x7
87#define CE_ENABLE_BITPOS 0x8
88#define CE_LMADDR_0_GLOBAL_BITPOS 16
89#define CE_LMADDR_1_GLOBAL_BITPOS 17
90#define CE_NN_MODE_BITPOS 20
91#define CE_REG_PAR_ERR_BITPOS 25
92#define CE_BREAKPOINT_BITPOS 27
93#define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29
94#define CE_INUSE_CONTEXTS_BITPOS 31
95#define CE_NN_MODE (0x1 << CE_NN_MODE_BITPOS)
96#define CE_INUSE_CONTEXTS (0x1 << CE_INUSE_CONTEXTS_BITPOS)
97#define XCWE_VOLUNTARY (0x1)
98#define LCS_STATUS (0x1)
99#define MMC_SHARE_CS_BITPOS 2
100#define GLOBAL_CSR 0xA00
101
102#define SET_CAP_CSR(handle, csr, val) \
103 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
104#define GET_CAP_CSR(handle, csr) \
105 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
106#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
107#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
108#define AE_CSR(handle, ae) \
109 (handle->hal_cap_ae_local_csr_addr_v + \
110 ((ae & handle->hal_handle->ae_mask) << 12))
111#define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
112#define SET_AE_CSR(handle, ae, csr, val) \
113 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
114#define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
115#define AE_XFER(handle, ae) \
116 (handle->hal_cap_ae_xfer_csr_addr_v + \
117 ((ae & handle->hal_handle->ae_mask) << 12))
118#define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
119 ((reg & 0xff) << 2))
120#define SET_AE_XFER(handle, ae, reg, val) \
121 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
122#define SRAM_WRITE(handle, addr, val) \
123 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
124#define SRAM_READ(handle, addr) ADF_CSR_RD(handle->hal_sram_addr_v, addr)
125#endif
126