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36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/edac.h>
41
42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43#include "edac_core.h"
44
45#define IE31200_REVISION "1.0"
46#define EDAC_MOD_STR "ie31200_edac"
47
48#define ie31200_printk(level, fmt, arg...) \
49 edac_printk(level, "ie31200", fmt, ##arg)
50
51#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
52#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
53#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
54#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
55#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
56#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
57#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
58
59#define IE31200_DIMMS 4
60#define IE31200_RANKS 8
61#define IE31200_RANKS_PER_CHANNEL 4
62#define IE31200_DIMMS_PER_CHANNEL 2
63#define IE31200_CHANNELS 2
64
65
66#define IE31200_MCHBAR_LOW 0x48
67#define IE31200_MCHBAR_HIGH 0x4c
68#define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
69#define IE31200_MMR_WINDOW_SIZE BIT(15)
70
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89
90#define IE31200_ERRSTS 0xc8
91#define IE31200_ERRSTS_UE BIT(1)
92#define IE31200_ERRSTS_CE BIT(0)
93#define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
94
95
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106
107
108#define IE31200_C0ECCERRLOG 0x40c8
109#define IE31200_C1ECCERRLOG 0x44c8
110#define IE31200_ECCERRLOG_CE BIT(0)
111#define IE31200_ECCERRLOG_UE BIT(1)
112#define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
113#define IE31200_ECCERRLOG_RANK_SHIFT 27
114#define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
115#define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
116
117#define IE31200_ECCERRLOG_SYNDROME(log) \
118 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
119 IE31200_ECCERRLOG_SYNDROME_SHIFT)
120
121#define IE31200_CAPID0 0xe4
122#define IE31200_CAPID0_PDCD BIT(4)
123#define IE31200_CAPID0_DDPCD BIT(6)
124#define IE31200_CAPID0_ECC BIT(1)
125
126#define IE31200_MAD_DIMM_0_OFFSET 0x5004
127#define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
128#define IE31200_MAD_DIMM_A_RANK BIT(17)
129#define IE31200_MAD_DIMM_A_WIDTH BIT(19)
130
131#define IE31200_PAGES(n) (n << (28 - PAGE_SHIFT))
132
133static int nr_channels;
134
135struct ie31200_priv {
136 void __iomem *window;
137};
138
139enum ie31200_chips {
140 IE31200 = 0,
141};
142
143struct ie31200_dev_info {
144 const char *ctl_name;
145};
146
147struct ie31200_error_info {
148 u16 errsts;
149 u16 errsts2;
150 u64 eccerrlog[IE31200_CHANNELS];
151};
152
153static const struct ie31200_dev_info ie31200_devs[] = {
154 [IE31200] = {
155 .ctl_name = "IE31200"
156 },
157};
158
159struct dimm_data {
160 u8 size;
161 u8 dual_rank : 1,
162 x16_width : 1;
163};
164
165static int how_many_channels(struct pci_dev *pdev)
166{
167 int n_channels;
168 unsigned char capid0_2b;
169
170 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
171
172
173 if (capid0_2b & IE31200_CAPID0_PDCD) {
174 edac_dbg(0, "In single channel mode\n");
175 n_channels = 1;
176 } else {
177 edac_dbg(0, "In dual channel mode\n");
178 n_channels = 2;
179 }
180
181
182 if (capid0_2b & IE31200_CAPID0_DDPCD)
183 edac_dbg(0, "2 DIMMS per channel disabled\n");
184 else
185 edac_dbg(0, "2 DIMMS per channel enabled\n");
186
187 return n_channels;
188}
189
190static bool ecc_capable(struct pci_dev *pdev)
191{
192 unsigned char capid0_4b;
193
194 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
195 if (capid0_4b & IE31200_CAPID0_ECC)
196 return false;
197 return true;
198}
199
200static int eccerrlog_row(int channel, u64 log)
201{
202 int rank = ((log & IE31200_ECCERRLOG_RANK_BITS) >>
203 IE31200_ECCERRLOG_RANK_SHIFT);
204 return rank | (channel * IE31200_RANKS_PER_CHANNEL);
205}
206
207static void ie31200_clear_error_info(struct mem_ctl_info *mci)
208{
209
210
211
212
213 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
214 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
215}
216
217static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
218 struct ie31200_error_info *info)
219{
220 struct pci_dev *pdev;
221 struct ie31200_priv *priv = mci->pvt_info;
222 void __iomem *window = priv->window;
223
224 pdev = to_pci_dev(mci->pdev);
225
226
227
228
229
230
231 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
232 if (!(info->errsts & IE31200_ERRSTS_BITS))
233 return;
234
235 info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
236 if (nr_channels == 2)
237 info->eccerrlog[1] = lo_hi_readq(window + IE31200_C1ECCERRLOG);
238
239 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
240
241
242
243
244
245
246
247 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
248 info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
249 if (nr_channels == 2)
250 info->eccerrlog[1] =
251 lo_hi_readq(window + IE31200_C1ECCERRLOG);
252 }
253
254 ie31200_clear_error_info(mci);
255}
256
257static void ie31200_process_error_info(struct mem_ctl_info *mci,
258 struct ie31200_error_info *info)
259{
260 int channel;
261 u64 log;
262
263 if (!(info->errsts & IE31200_ERRSTS_BITS))
264 return;
265
266 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
267 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
268 -1, -1, -1, "UE overwrote CE", "");
269 info->errsts = info->errsts2;
270 }
271
272 for (channel = 0; channel < nr_channels; channel++) {
273 log = info->eccerrlog[channel];
274 if (log & IE31200_ECCERRLOG_UE) {
275 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
276 0, 0, 0,
277 eccerrlog_row(channel, log),
278 channel, -1,
279 "ie31200 UE", "");
280 } else if (log & IE31200_ECCERRLOG_CE) {
281 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
282 0, 0,
283 IE31200_ECCERRLOG_SYNDROME(log),
284 eccerrlog_row(channel, log),
285 channel, -1,
286 "ie31200 CE", "");
287 }
288 }
289}
290
291static void ie31200_check(struct mem_ctl_info *mci)
292{
293 struct ie31200_error_info info;
294
295 edac_dbg(1, "MC%d\n", mci->mc_idx);
296 ie31200_get_and_clear_error_info(mci, &info);
297 ie31200_process_error_info(mci, &info);
298}
299
300static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
301{
302 union {
303 u64 mchbar;
304 struct {
305 u32 mchbar_low;
306 u32 mchbar_high;
307 };
308 } u;
309 void __iomem *window;
310
311 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
312 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
313 u.mchbar &= IE31200_MCHBAR_MASK;
314
315 if (u.mchbar != (resource_size_t)u.mchbar) {
316 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
317 (unsigned long long)u.mchbar);
318 return NULL;
319 }
320
321 window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
322 if (!window)
323 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
324 (unsigned long long)u.mchbar);
325
326 return window;
327}
328
329static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
330{
331 int i, j, ret;
332 struct mem_ctl_info *mci = NULL;
333 struct edac_mc_layer layers[2];
334 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
335 void __iomem *window;
336 struct ie31200_priv *priv;
337 u32 addr_decode;
338
339 edac_dbg(0, "MC:\n");
340
341 if (!ecc_capable(pdev)) {
342 ie31200_printk(KERN_INFO, "No ECC support\n");
343 return -ENODEV;
344 }
345
346 nr_channels = how_many_channels(pdev);
347 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
348 layers[0].size = IE31200_DIMMS;
349 layers[0].is_virt_csrow = true;
350 layers[1].type = EDAC_MC_LAYER_CHANNEL;
351 layers[1].size = nr_channels;
352 layers[1].is_virt_csrow = false;
353 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
354 sizeof(struct ie31200_priv));
355 if (!mci)
356 return -ENOMEM;
357
358 window = ie31200_map_mchbar(pdev);
359 if (!window) {
360 ret = -ENODEV;
361 goto fail_free;
362 }
363
364 edac_dbg(3, "MC: init mci\n");
365 mci->pdev = &pdev->dev;
366 mci->mtype_cap = MEM_FLAG_DDR3;
367 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
368 mci->edac_cap = EDAC_FLAG_SECDED;
369 mci->mod_name = EDAC_MOD_STR;
370 mci->mod_ver = IE31200_REVISION;
371 mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
372 mci->dev_name = pci_name(pdev);
373 mci->edac_check = ie31200_check;
374 mci->ctl_page_to_phys = NULL;
375 priv = mci->pvt_info;
376 priv->window = window;
377
378
379 for (i = 0; i < IE31200_CHANNELS; i++) {
380 addr_decode = readl(window + IE31200_MAD_DIMM_0_OFFSET +
381 (i * 4));
382 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
383 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
384 dimm_info[i][j].size = (addr_decode >> (j * 8)) &
385 IE31200_MAD_DIMM_SIZE;
386 dimm_info[i][j].dual_rank = (addr_decode &
387 (IE31200_MAD_DIMM_A_RANK << j)) ? 1 : 0;
388 dimm_info[i][j].x16_width = (addr_decode &
389 (IE31200_MAD_DIMM_A_WIDTH << j)) ? 1 : 0;
390 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
391 dimm_info[i][j].size,
392 dimm_info[i][j].dual_rank,
393 dimm_info[i][j].x16_width);
394 }
395 }
396
397
398
399
400
401
402
403 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
404 for (j = 0; j < IE31200_CHANNELS; j++) {
405 struct dimm_info *dimm;
406 unsigned long nr_pages;
407
408 nr_pages = IE31200_PAGES(dimm_info[j][i].size);
409 if (nr_pages == 0)
410 continue;
411
412 if (dimm_info[j][i].dual_rank) {
413 nr_pages = nr_pages / 2;
414 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
415 mci->n_layers, (i * 2) + 1,
416 j, 0);
417 dimm->nr_pages = nr_pages;
418 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
419 dimm->grain = 8;
420 dimm->mtype = MEM_DDR3;
421 dimm->dtype = DEV_UNKNOWN;
422 dimm->edac_mode = EDAC_UNKNOWN;
423 }
424 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
425 mci->n_layers, i * 2, j, 0);
426 dimm->nr_pages = nr_pages;
427 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
428 dimm->grain = 8;
429 dimm->mtype = MEM_DDR3;
430 dimm->dtype = DEV_UNKNOWN;
431 dimm->edac_mode = EDAC_UNKNOWN;
432 }
433 }
434
435 ie31200_clear_error_info(mci);
436
437 if (edac_mc_add_mc(mci)) {
438 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
439 ret = -ENODEV;
440 goto fail_unmap;
441 }
442
443
444 edac_dbg(3, "MC: success\n");
445 return 0;
446
447fail_unmap:
448 iounmap(window);
449
450fail_free:
451 edac_mc_free(mci);
452
453 return ret;
454}
455
456static int ie31200_init_one(struct pci_dev *pdev,
457 const struct pci_device_id *ent)
458{
459 edac_dbg(0, "MC:\n");
460
461 if (pci_enable_device(pdev) < 0)
462 return -EIO;
463
464 return ie31200_probe1(pdev, ent->driver_data);
465}
466
467static void ie31200_remove_one(struct pci_dev *pdev)
468{
469 struct mem_ctl_info *mci;
470 struct ie31200_priv *priv;
471
472 edac_dbg(0, "\n");
473 mci = edac_mc_del_mc(&pdev->dev);
474 if (!mci)
475 return;
476 priv = mci->pvt_info;
477 iounmap(priv->window);
478 edac_mc_free(mci);
479}
480
481static const struct pci_device_id ie31200_pci_tbl[] = {
482 {
483 PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
484 IE31200},
485 {
486 PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
487 IE31200},
488 {
489 PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
490 IE31200},
491 {
492 PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
493 IE31200},
494 {
495 PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
496 IE31200},
497 {
498 PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
499 IE31200},
500 {
501 PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
502 IE31200},
503 {
504 0,
505 }
506};
507MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
508
509static struct pci_driver ie31200_driver = {
510 .name = EDAC_MOD_STR,
511 .probe = ie31200_init_one,
512 .remove = ie31200_remove_one,
513 .id_table = ie31200_pci_tbl,
514};
515
516static int __init ie31200_init(void)
517{
518 edac_dbg(3, "MC:\n");
519
520 opstate_init();
521
522 return pci_register_driver(&ie31200_driver);
523}
524
525static void __exit ie31200_exit(void)
526{
527 edac_dbg(3, "MC:\n");
528 pci_unregister_driver(&ie31200_driver);
529}
530
531module_init(ie31200_init);
532module_exit(ie31200_exit);
533
534MODULE_LICENSE("GPL");
535MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
536MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
537
