1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/interrupt.h>
19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/seq_file.h>
22#include <linux/bitops.h>
23#include <linux/regmap.h>
24#include <linux/mfd/intel_soc_pmic.h>
25
26#define CRYSTALCOVE_GPIO_NUM 16
27#define CRYSTALCOVE_VGPIO_NUM 95
28
29#define UPDATE_IRQ_TYPE BIT(0)
30#define UPDATE_IRQ_MASK BIT(1)
31
32#define GPIO0IRQ 0x0b
33#define GPIO1IRQ 0x0c
34#define MGPIO0IRQS0 0x19
35#define MGPIO1IRQS0 0x1a
36#define MGPIO0IRQSX 0x1b
37#define MGPIO1IRQSX 0x1c
38#define GPIO0P0CTLO 0x2b
39#define GPIO0P0CTLI 0x33
40#define GPIO1P0CTLO 0x3b
41#define GPIO1P0CTLI 0x43
42#define GPIOPANELCTL 0x52
43
44#define CTLI_INTCNT_DIS (0)
45#define CTLI_INTCNT_NE (1 << 1)
46#define CTLI_INTCNT_PE (2 << 1)
47#define CTLI_INTCNT_BE (3 << 1)
48
49#define CTLO_DIR_IN (0)
50#define CTLO_DIR_OUT (1 << 5)
51
52#define CTLO_DRV_CMOS (0)
53#define CTLO_DRV_OD (1 << 4)
54
55#define CTLO_DRV_REN (1 << 3)
56
57#define CTLO_RVAL_2KDW (0)
58#define CTLO_RVAL_2KUP (1 << 1)
59#define CTLO_RVAL_50KDW (2 << 1)
60#define CTLO_RVAL_50KUP (3 << 1)
61
62#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
63#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
64
65enum ctrl_register {
66 CTRL_IN,
67 CTRL_OUT,
68};
69
70
71
72
73
74
75
76
77
78
79struct crystalcove_gpio {
80 struct mutex buslock;
81 struct gpio_chip chip;
82 struct regmap *regmap;
83 int update;
84 int intcnt_value;
85 bool set_irq_mask;
86};
87
88static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
89{
90 return container_of(gc, struct crystalcove_gpio, chip);
91}
92
93static inline int to_reg(int gpio, enum ctrl_register reg_type)
94{
95 int reg;
96
97 if (gpio == 94) {
98 return GPIOPANELCTL;
99 }
100
101 if (reg_type == CTRL_IN) {
102 if (gpio < 8)
103 reg = GPIO0P0CTLI;
104 else
105 reg = GPIO1P0CTLI;
106 } else {
107 if (gpio < 8)
108 reg = GPIO0P0CTLO;
109 else
110 reg = GPIO1P0CTLO;
111 }
112
113 return reg + gpio % 8;
114}
115
116static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
117 int gpio)
118{
119 u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
120 int mask = BIT(gpio % 8);
121
122 if (cg->set_irq_mask)
123 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
124 else
125 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
126}
127
128static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
129{
130 int reg = to_reg(gpio, CTRL_IN);
131
132 regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
133}
134
135static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
136{
137 struct crystalcove_gpio *cg = to_cg(chip);
138
139 if (gpio > CRYSTALCOVE_VGPIO_NUM)
140 return 0;
141
142 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
143 CTLO_INPUT_SET);
144}
145
146static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
147 int value)
148{
149 struct crystalcove_gpio *cg = to_cg(chip);
150
151 if (gpio > CRYSTALCOVE_VGPIO_NUM)
152 return 0;
153
154 return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
155 CTLO_OUTPUT_SET | value);
156}
157
158static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
159{
160 struct crystalcove_gpio *cg = to_cg(chip);
161 int ret;
162 unsigned int val;
163
164 if (gpio > CRYSTALCOVE_VGPIO_NUM)
165 return 0;
166
167 ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
168 if (ret)
169 return ret;
170
171 return val & 0x1;
172}
173
174static void crystalcove_gpio_set(struct gpio_chip *chip,
175 unsigned gpio, int value)
176{
177 struct crystalcove_gpio *cg = to_cg(chip);
178
179 if (gpio > CRYSTALCOVE_VGPIO_NUM)
180 return;
181
182 if (value)
183 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
184 else
185 regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
186}
187
188static int crystalcove_irq_type(struct irq_data *data, unsigned type)
189{
190 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
191
192 switch (type) {
193 case IRQ_TYPE_NONE:
194 cg->intcnt_value = CTLI_INTCNT_DIS;
195 break;
196 case IRQ_TYPE_EDGE_BOTH:
197 cg->intcnt_value = CTLI_INTCNT_BE;
198 break;
199 case IRQ_TYPE_EDGE_RISING:
200 cg->intcnt_value = CTLI_INTCNT_PE;
201 break;
202 case IRQ_TYPE_EDGE_FALLING:
203 cg->intcnt_value = CTLI_INTCNT_NE;
204 break;
205 default:
206 return -EINVAL;
207 }
208
209 cg->update |= UPDATE_IRQ_TYPE;
210
211 return 0;
212}
213
214static void crystalcove_bus_lock(struct irq_data *data)
215{
216 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
217
218 mutex_lock(&cg->buslock);
219}
220
221static void crystalcove_bus_sync_unlock(struct irq_data *data)
222{
223 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
224 int gpio = data->hwirq;
225
226 if (cg->update & UPDATE_IRQ_TYPE)
227 crystalcove_update_irq_ctrl(cg, gpio);
228 if (cg->update & UPDATE_IRQ_MASK)
229 crystalcove_update_irq_mask(cg, gpio);
230 cg->update = 0;
231
232 mutex_unlock(&cg->buslock);
233}
234
235static void crystalcove_irq_unmask(struct irq_data *data)
236{
237 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
238
239 cg->set_irq_mask = false;
240 cg->update |= UPDATE_IRQ_MASK;
241}
242
243static void crystalcove_irq_mask(struct irq_data *data)
244{
245 struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
246
247 cg->set_irq_mask = true;
248 cg->update |= UPDATE_IRQ_MASK;
249}
250
251static struct irq_chip crystalcove_irqchip = {
252 .name = "Crystal Cove",
253 .irq_mask = crystalcove_irq_mask,
254 .irq_unmask = crystalcove_irq_unmask,
255 .irq_set_type = crystalcove_irq_type,
256 .irq_bus_lock = crystalcove_bus_lock,
257 .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
258};
259
260static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
261{
262 struct crystalcove_gpio *cg = data;
263 unsigned int p0, p1;
264 int pending;
265 int gpio;
266 unsigned int virq;
267
268 if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
269 regmap_read(cg->regmap, GPIO1IRQ, &p1))
270 return IRQ_NONE;
271
272 regmap_write(cg->regmap, GPIO0IRQ, p0);
273 regmap_write(cg->regmap, GPIO1IRQ, p1);
274
275 pending = p0 | p1 << 8;
276
277 for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
278 if (pending & BIT(gpio)) {
279 virq = irq_find_mapping(cg->chip.irqdomain, gpio);
280 handle_nested_irq(virq);
281 }
282 }
283
284 return IRQ_HANDLED;
285}
286
287static void crystalcove_gpio_dbg_show(struct seq_file *s,
288 struct gpio_chip *chip)
289{
290 struct crystalcove_gpio *cg = to_cg(chip);
291 int gpio, offset;
292 unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
293
294 for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
295 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
296 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
297 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
298 &mirqs0);
299 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
300 &mirqsx);
301 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
302 &irq);
303
304 offset = gpio % 8;
305 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
306 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
307 ctli & 0x1 ? "hi" : "lo",
308 ctli & CTLI_INTCNT_NE ? "fall" : " ",
309 ctli & CTLI_INTCNT_PE ? "rise" : " ",
310 ctlo,
311 mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
312 mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
313 irq & BIT(offset) ? "pending" : " ");
314 }
315}
316
317static int crystalcove_gpio_probe(struct platform_device *pdev)
318{
319 int irq = platform_get_irq(pdev, 0);
320 struct crystalcove_gpio *cg;
321 int retval;
322 struct device *dev = pdev->dev.parent;
323 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
324
325 if (irq < 0)
326 return irq;
327
328 cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
329 if (!cg)
330 return -ENOMEM;
331
332 platform_set_drvdata(pdev, cg);
333
334 mutex_init(&cg->buslock);
335 cg->chip.label = KBUILD_MODNAME;
336 cg->chip.direction_input = crystalcove_gpio_dir_in;
337 cg->chip.direction_output = crystalcove_gpio_dir_out;
338 cg->chip.get = crystalcove_gpio_get;
339 cg->chip.set = crystalcove_gpio_set;
340 cg->chip.base = -1;
341 cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
342 cg->chip.can_sleep = true;
343 cg->chip.dev = dev;
344 cg->chip.dbg_show = crystalcove_gpio_dbg_show;
345 cg->regmap = pmic->regmap;
346
347 retval = gpiochip_add(&cg->chip);
348 if (retval) {
349 dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
350 return retval;
351 }
352
353 gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
354 handle_simple_irq, IRQ_TYPE_NONE);
355
356 retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
357 IRQF_ONESHOT, KBUILD_MODNAME, cg);
358
359 if (retval) {
360 dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
361 goto out_remove_gpio;
362 }
363
364 return 0;
365
366out_remove_gpio:
367 gpiochip_remove(&cg->chip);
368 return retval;
369}
370
371static int crystalcove_gpio_remove(struct platform_device *pdev)
372{
373 struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
374 int irq = platform_get_irq(pdev, 0);
375
376 gpiochip_remove(&cg->chip);
377 if (irq >= 0)
378 free_irq(irq, cg);
379 return 0;
380}
381
382static struct platform_driver crystalcove_gpio_driver = {
383 .probe = crystalcove_gpio_probe,
384 .remove = crystalcove_gpio_remove,
385 .driver = {
386 .name = "crystal_cove_gpio",
387 },
388};
389
390module_platform_driver(crystalcove_gpio_driver);
391
392MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
393MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
394MODULE_LICENSE("GPL v2");
395
