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11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/types.h>
15#include <linux/irqdomain.h>
16#include <linux/irq.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/gpio.h>
19#include <linux/gpio/driver.h>
20#include <linux/platform_device.h>
21#include <linux/mfd/dln2.h>
22
23#define DLN2_GPIO_ID 0x01
24
25#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
26#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
27#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
28#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
29#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
30#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
31#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
32#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
33#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
34#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
35#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
36#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
37#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
38#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
39
40#define DLN2_GPIO_EVENT_NONE 0
41#define DLN2_GPIO_EVENT_CHANGE 1
42#define DLN2_GPIO_EVENT_LVL_HIGH 2
43#define DLN2_GPIO_EVENT_LVL_LOW 3
44#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
45#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
46#define DLN2_GPIO_EVENT_MASK 0x0F
47
48#define DLN2_GPIO_MAX_PINS 32
49
50struct dln2_gpio {
51 struct platform_device *pdev;
52 struct gpio_chip gpio;
53
54
55
56
57
58 DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
59
60
61 DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
62
63 DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
64 int irq_type[DLN2_GPIO_MAX_PINS];
65 struct mutex irq_lock;
66};
67
68struct dln2_gpio_pin {
69 __le16 pin;
70};
71
72struct dln2_gpio_pin_val {
73 __le16 pin __packed;
74 u8 value;
75};
76
77static int dln2_gpio_get_pin_count(struct platform_device *pdev)
78{
79 int ret;
80 __le16 count;
81 int len = sizeof(count);
82
83 ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
84 if (ret < 0)
85 return ret;
86 if (len < sizeof(count))
87 return -EPROTO;
88
89 return le16_to_cpu(count);
90}
91
92static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
93{
94 struct dln2_gpio_pin req = {
95 .pin = cpu_to_le16(pin),
96 };
97
98 return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
99}
100
101static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
102{
103 int ret;
104 struct dln2_gpio_pin req = {
105 .pin = cpu_to_le16(pin),
106 };
107 struct dln2_gpio_pin_val rsp;
108 int len = sizeof(rsp);
109
110 ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
111 if (ret < 0)
112 return ret;
113 if (len < sizeof(rsp) || req.pin != rsp.pin)
114 return -EPROTO;
115
116 return rsp.value;
117}
118
119static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
120{
121 int ret;
122
123 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
124 if (ret < 0)
125 return ret;
126 return !!ret;
127}
128
129static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
130{
131 int ret;
132
133 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
134 if (ret < 0)
135 return ret;
136 return !!ret;
137}
138
139static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
140 unsigned int pin, int value)
141{
142 struct dln2_gpio_pin_val req = {
143 .pin = cpu_to_le16(pin),
144 .value = value,
145 };
146
147 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
148 sizeof(req));
149}
150
151#define DLN2_GPIO_DIRECTION_IN 0
152#define DLN2_GPIO_DIRECTION_OUT 1
153
154static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
155{
156 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
157 struct dln2_gpio_pin req = {
158 .pin = cpu_to_le16(offset),
159 };
160 struct dln2_gpio_pin_val rsp;
161 int len = sizeof(rsp);
162 int ret;
163
164 ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
165 if (ret < 0)
166 return ret;
167
168
169 ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
170 &req, sizeof(req), &rsp, &len);
171 if (ret < 0)
172 return ret;
173 if (len < sizeof(rsp) || req.pin != rsp.pin) {
174 ret = -EPROTO;
175 goto out_disable;
176 }
177
178 switch (rsp.value) {
179 case DLN2_GPIO_DIRECTION_IN:
180 clear_bit(offset, dln2->output_enabled);
181 return 0;
182 case DLN2_GPIO_DIRECTION_OUT:
183 set_bit(offset, dln2->output_enabled);
184 return 0;
185 default:
186 ret = -EPROTO;
187 goto out_disable;
188 }
189
190out_disable:
191 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
192 return ret;
193}
194
195static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
196{
197 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
198
199 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
200}
201
202static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
203{
204 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
205
206 if (test_bit(offset, dln2->output_enabled))
207 return GPIOF_DIR_OUT;
208
209 return GPIOF_DIR_IN;
210}
211
212static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
213{
214 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
215 int dir;
216
217 dir = dln2_gpio_get_direction(chip, offset);
218 if (dir < 0)
219 return dir;
220
221 if (dir == GPIOF_DIR_IN)
222 return dln2_gpio_pin_get_in_val(dln2, offset);
223
224 return dln2_gpio_pin_get_out_val(dln2, offset);
225}
226
227static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
228{
229 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
230
231 dln2_gpio_pin_set_out_val(dln2, offset, value);
232}
233
234static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
235 unsigned dir)
236{
237 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
238 struct dln2_gpio_pin_val req = {
239 .pin = cpu_to_le16(offset),
240 .value = dir,
241 };
242 int ret;
243
244 ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
245 &req, sizeof(req));
246 if (ret < 0)
247 return ret;
248
249 if (dir == DLN2_GPIO_DIRECTION_OUT)
250 set_bit(offset, dln2->output_enabled);
251 else
252 clear_bit(offset, dln2->output_enabled);
253
254 return ret;
255}
256
257static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
258{
259 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
260}
261
262static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
263 int value)
264{
265 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
266 int ret;
267
268 ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
269 if (ret < 0)
270 return ret;
271
272 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
273}
274
275static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
276 unsigned debounce)
277{
278 struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
279 __le32 duration = cpu_to_le32(debounce);
280
281 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
282 &duration, sizeof(duration));
283}
284
285static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
286 unsigned type, unsigned period)
287{
288 struct {
289 __le16 pin;
290 u8 type;
291 __le16 period;
292 } __packed req = {
293 .pin = cpu_to_le16(pin),
294 .type = type,
295 .period = cpu_to_le16(period),
296 };
297
298 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
299 &req, sizeof(req));
300}
301
302static void dln2_irq_unmask(struct irq_data *irqd)
303{
304 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
305 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
306 int pin = irqd_to_hwirq(irqd);
307
308 set_bit(pin, dln2->unmasked_irqs);
309}
310
311static void dln2_irq_mask(struct irq_data *irqd)
312{
313 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
314 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
315 int pin = irqd_to_hwirq(irqd);
316
317 clear_bit(pin, dln2->unmasked_irqs);
318}
319
320static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
321{
322 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
323 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
324 int pin = irqd_to_hwirq(irqd);
325
326 switch (type) {
327 case IRQ_TYPE_LEVEL_HIGH:
328 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
329 break;
330 case IRQ_TYPE_LEVEL_LOW:
331 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
332 break;
333 case IRQ_TYPE_EDGE_BOTH:
334 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
335 break;
336 case IRQ_TYPE_EDGE_RISING:
337 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
338 break;
339 case IRQ_TYPE_EDGE_FALLING:
340 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
341 break;
342 default:
343 return -EINVAL;
344 }
345
346 return 0;
347}
348
349static void dln2_irq_bus_lock(struct irq_data *irqd)
350{
351 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
352 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
353
354 mutex_lock(&dln2->irq_lock);
355}
356
357static void dln2_irq_bus_unlock(struct irq_data *irqd)
358{
359 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
360 struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
361 int pin = irqd_to_hwirq(irqd);
362 int enabled, unmasked;
363 unsigned type;
364 int ret;
365
366 enabled = test_bit(pin, dln2->enabled_irqs);
367 unmasked = test_bit(pin, dln2->unmasked_irqs);
368
369 if (enabled != unmasked) {
370 if (unmasked) {
371 type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
372 set_bit(pin, dln2->enabled_irqs);
373 } else {
374 type = DLN2_GPIO_EVENT_NONE;
375 clear_bit(pin, dln2->enabled_irqs);
376 }
377
378 ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
379 if (ret)
380 dev_err(dln2->gpio.dev, "failed to set event\n");
381 }
382
383 mutex_unlock(&dln2->irq_lock);
384}
385
386static struct irq_chip dln2_gpio_irqchip = {
387 .name = "dln2-irq",
388 .irq_mask = dln2_irq_mask,
389 .irq_unmask = dln2_irq_unmask,
390 .irq_set_type = dln2_irq_set_type,
391 .irq_bus_lock = dln2_irq_bus_lock,
392 .irq_bus_sync_unlock = dln2_irq_bus_unlock,
393};
394
395static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
396 const void *data, int len)
397{
398 int pin, irq;
399
400 const struct {
401 __le16 count;
402 __u8 type;
403 __le16 pin;
404 __u8 value;
405 } __packed *event = data;
406 struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
407
408 if (len < sizeof(*event)) {
409 dev_err(dln2->gpio.dev, "short event message\n");
410 return;
411 }
412
413 pin = le16_to_cpu(event->pin);
414 if (pin >= dln2->gpio.ngpio) {
415 dev_err(dln2->gpio.dev, "out of bounds pin %d\n", pin);
416 return;
417 }
418
419 irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
420 if (!irq) {
421 dev_err(dln2->gpio.dev, "pin %d not mapped to IRQ\n", pin);
422 return;
423 }
424
425 switch (dln2->irq_type[pin]) {
426 case DLN2_GPIO_EVENT_CHANGE_RISING:
427 if (event->value)
428 generic_handle_irq(irq);
429 break;
430 case DLN2_GPIO_EVENT_CHANGE_FALLING:
431 if (!event->value)
432 generic_handle_irq(irq);
433 break;
434 default:
435 generic_handle_irq(irq);
436 }
437}
438
439static int dln2_gpio_probe(struct platform_device *pdev)
440{
441 struct dln2_gpio *dln2;
442 struct device *dev = &pdev->dev;
443 int pins;
444 int ret;
445
446 pins = dln2_gpio_get_pin_count(pdev);
447 if (pins < 0) {
448 dev_err(dev, "failed to get pin count: %d\n", pins);
449 return pins;
450 }
451 if (pins > DLN2_GPIO_MAX_PINS) {
452 pins = DLN2_GPIO_MAX_PINS;
453 dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
454 }
455
456 dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
457 if (!dln2)
458 return -ENOMEM;
459
460 mutex_init(&dln2->irq_lock);
461
462 dln2->pdev = pdev;
463
464 dln2->gpio.label = "dln2";
465 dln2->gpio.dev = dev;
466 dln2->gpio.owner = THIS_MODULE;
467 dln2->gpio.base = -1;
468 dln2->gpio.ngpio = pins;
469 dln2->gpio.exported = true;
470 dln2->gpio.can_sleep = true;
471 dln2->gpio.irq_not_threaded = true;
472 dln2->gpio.set = dln2_gpio_set;
473 dln2->gpio.get = dln2_gpio_get;
474 dln2->gpio.request = dln2_gpio_request;
475 dln2->gpio.free = dln2_gpio_free;
476 dln2->gpio.get_direction = dln2_gpio_get_direction;
477 dln2->gpio.direction_input = dln2_gpio_direction_input;
478 dln2->gpio.direction_output = dln2_gpio_direction_output;
479 dln2->gpio.set_debounce = dln2_gpio_set_debounce;
480
481 platform_set_drvdata(pdev, dln2);
482
483 ret = gpiochip_add(&dln2->gpio);
484 if (ret < 0) {
485 dev_err(dev, "failed to add gpio chip: %d\n", ret);
486 goto out;
487 }
488
489 ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
490 handle_simple_irq, IRQ_TYPE_NONE);
491 if (ret < 0) {
492 dev_err(dev, "failed to add irq chip: %d\n", ret);
493 goto out_gpiochip_remove;
494 }
495
496 ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
497 dln2_gpio_event);
498 if (ret) {
499 dev_err(dev, "failed to register event cb: %d\n", ret);
500 goto out_gpiochip_remove;
501 }
502
503 return 0;
504
505out_gpiochip_remove:
506 gpiochip_remove(&dln2->gpio);
507out:
508 return ret;
509}
510
511static int dln2_gpio_remove(struct platform_device *pdev)
512{
513 struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
514
515 dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
516 gpiochip_remove(&dln2->gpio);
517
518 return 0;
519}
520
521static struct platform_driver dln2_gpio_driver = {
522 .driver.name = "dln2-gpio",
523 .probe = dln2_gpio_probe,
524 .remove = dln2_gpio_remove,
525};
526
527module_platform_driver(dln2_gpio_driver);
528
529MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
530MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
531MODULE_LICENSE("GPL v2");
532MODULE_ALIAS("platform:dln2-gpio");
533
