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30#include <linux/device.h>
31#include <linux/acpi.h>
32#include <drm/drmP.h>
33#include <drm/i915_drm.h>
34#include "i915_drv.h"
35#include "i915_trace.h"
36#include "intel_drv.h"
37
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <drm/drm_crtc_helper.h>
42
43static struct drm_driver driver;
44
45#define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
51
52#define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
59
60#define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
62
63#define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
65
66static const struct intel_device_info intel_i830_info = {
67 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
68 .has_overlay = 1, .overlay_needs_physical = 1,
69 .ring_mask = RENDER_RING,
70 GEN_DEFAULT_PIPEOFFSETS,
71 CURSOR_OFFSETS,
72};
73
74static const struct intel_device_info intel_845g_info = {
75 .gen = 2, .num_pipes = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
79 CURSOR_OFFSETS,
80};
81
82static const struct intel_device_info intel_i85x_info = {
83 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
84 .cursor_needs_physical = 1,
85 .has_overlay = 1, .overlay_needs_physical = 1,
86 .has_fbc = 1,
87 .ring_mask = RENDER_RING,
88 GEN_DEFAULT_PIPEOFFSETS,
89 CURSOR_OFFSETS,
90};
91
92static const struct intel_device_info intel_i865g_info = {
93 .gen = 2, .num_pipes = 1,
94 .has_overlay = 1, .overlay_needs_physical = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
97 CURSOR_OFFSETS,
98};
99
100static const struct intel_device_info intel_i915g_info = {
101 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
105 CURSOR_OFFSETS,
106};
107static const struct intel_device_info intel_i915gm_info = {
108 .gen = 3, .is_mobile = 1, .num_pipes = 2,
109 .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1,
111 .supports_tv = 1,
112 .has_fbc = 1,
113 .ring_mask = RENDER_RING,
114 GEN_DEFAULT_PIPEOFFSETS,
115 CURSOR_OFFSETS,
116};
117static const struct intel_device_info intel_i945g_info = {
118 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
119 .has_overlay = 1, .overlay_needs_physical = 1,
120 .ring_mask = RENDER_RING,
121 GEN_DEFAULT_PIPEOFFSETS,
122 CURSOR_OFFSETS,
123};
124static const struct intel_device_info intel_i945gm_info = {
125 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
126 .has_hotplug = 1, .cursor_needs_physical = 1,
127 .has_overlay = 1, .overlay_needs_physical = 1,
128 .supports_tv = 1,
129 .has_fbc = 1,
130 .ring_mask = RENDER_RING,
131 GEN_DEFAULT_PIPEOFFSETS,
132 CURSOR_OFFSETS,
133};
134
135static const struct intel_device_info intel_i965g_info = {
136 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
137 .has_hotplug = 1,
138 .has_overlay = 1,
139 .ring_mask = RENDER_RING,
140 GEN_DEFAULT_PIPEOFFSETS,
141 CURSOR_OFFSETS,
142};
143
144static const struct intel_device_info intel_i965gm_info = {
145 .gen = 4, .is_crestline = 1, .num_pipes = 2,
146 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
147 .has_overlay = 1,
148 .supports_tv = 1,
149 .ring_mask = RENDER_RING,
150 GEN_DEFAULT_PIPEOFFSETS,
151 CURSOR_OFFSETS,
152};
153
154static const struct intel_device_info intel_g33_info = {
155 .gen = 3, .is_g33 = 1, .num_pipes = 2,
156 .need_gfx_hws = 1, .has_hotplug = 1,
157 .has_overlay = 1,
158 .ring_mask = RENDER_RING,
159 GEN_DEFAULT_PIPEOFFSETS,
160 CURSOR_OFFSETS,
161};
162
163static const struct intel_device_info intel_g45_info = {
164 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
165 .has_pipe_cxsr = 1, .has_hotplug = 1,
166 .ring_mask = RENDER_RING | BSD_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
168 CURSOR_OFFSETS,
169};
170
171static const struct intel_device_info intel_gm45_info = {
172 .gen = 4, .is_g4x = 1, .num_pipes = 2,
173 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
174 .has_pipe_cxsr = 1, .has_hotplug = 1,
175 .supports_tv = 1,
176 .ring_mask = RENDER_RING | BSD_RING,
177 GEN_DEFAULT_PIPEOFFSETS,
178 CURSOR_OFFSETS,
179};
180
181static const struct intel_device_info intel_pineview_info = {
182 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
183 .need_gfx_hws = 1, .has_hotplug = 1,
184 .has_overlay = 1,
185 GEN_DEFAULT_PIPEOFFSETS,
186 CURSOR_OFFSETS,
187};
188
189static const struct intel_device_info intel_ironlake_d_info = {
190 .gen = 5, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
193 GEN_DEFAULT_PIPEOFFSETS,
194 CURSOR_OFFSETS,
195};
196
197static const struct intel_device_info intel_ironlake_m_info = {
198 .gen = 5, .is_mobile = 1, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
200 .has_fbc = 1,
201 .ring_mask = RENDER_RING | BSD_RING,
202 GEN_DEFAULT_PIPEOFFSETS,
203 CURSOR_OFFSETS,
204};
205
206static const struct intel_device_info intel_sandybridge_d_info = {
207 .gen = 6, .num_pipes = 2,
208 .need_gfx_hws = 1, .has_hotplug = 1,
209 .has_fbc = 1,
210 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
211 .has_llc = 1,
212 GEN_DEFAULT_PIPEOFFSETS,
213 CURSOR_OFFSETS,
214};
215
216static const struct intel_device_info intel_sandybridge_m_info = {
217 .gen = 6, .is_mobile = 1, .num_pipes = 2,
218 .need_gfx_hws = 1, .has_hotplug = 1,
219 .has_fbc = 1,
220 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
221 .has_llc = 1,
222 GEN_DEFAULT_PIPEOFFSETS,
223 CURSOR_OFFSETS,
224};
225
226#define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
229 .has_fbc = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
231 .has_llc = 1
232
233static const struct intel_device_info intel_ivybridge_d_info = {
234 GEN7_FEATURES,
235 .is_ivybridge = 1,
236 GEN_DEFAULT_PIPEOFFSETS,
237 IVB_CURSOR_OFFSETS,
238};
239
240static const struct intel_device_info intel_ivybridge_m_info = {
241 GEN7_FEATURES,
242 .is_ivybridge = 1,
243 .is_mobile = 1,
244 GEN_DEFAULT_PIPEOFFSETS,
245 IVB_CURSOR_OFFSETS,
246};
247
248static const struct intel_device_info intel_ivybridge_q_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .num_pipes = 0,
252 GEN_DEFAULT_PIPEOFFSETS,
253 IVB_CURSOR_OFFSETS,
254};
255
256static const struct intel_device_info intel_valleyview_m_info = {
257 GEN7_FEATURES,
258 .is_mobile = 1,
259 .num_pipes = 2,
260 .is_valleyview = 1,
261 .display_mmio_offset = VLV_DISPLAY_BASE,
262 .has_fbc = 0,
263 .has_llc = 0,
264 GEN_DEFAULT_PIPEOFFSETS,
265 CURSOR_OFFSETS,
266};
267
268static const struct intel_device_info intel_valleyview_d_info = {
269 GEN7_FEATURES,
270 .num_pipes = 2,
271 .is_valleyview = 1,
272 .display_mmio_offset = VLV_DISPLAY_BASE,
273 .has_fbc = 0,
274 .has_llc = 0,
275 GEN_DEFAULT_PIPEOFFSETS,
276 CURSOR_OFFSETS,
277};
278
279static const struct intel_device_info intel_haswell_d_info = {
280 GEN7_FEATURES,
281 .is_haswell = 1,
282 .has_ddi = 1,
283 .has_fpga_dbg = 1,
284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
285 GEN_DEFAULT_PIPEOFFSETS,
286 IVB_CURSOR_OFFSETS,
287};
288
289static const struct intel_device_info intel_haswell_m_info = {
290 GEN7_FEATURES,
291 .is_haswell = 1,
292 .is_mobile = 1,
293 .has_ddi = 1,
294 .has_fpga_dbg = 1,
295 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
296 GEN_DEFAULT_PIPEOFFSETS,
297 IVB_CURSOR_OFFSETS,
298};
299
300static const struct intel_device_info intel_broadwell_d_info = {
301 .gen = 8, .num_pipes = 3,
302 .need_gfx_hws = 1, .has_hotplug = 1,
303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
304 .has_llc = 1,
305 .has_ddi = 1,
306 .has_fpga_dbg = 1,
307 .has_fbc = 1,
308 GEN_DEFAULT_PIPEOFFSETS,
309 IVB_CURSOR_OFFSETS,
310};
311
312static const struct intel_device_info intel_broadwell_m_info = {
313 .gen = 8, .is_mobile = 1, .num_pipes = 3,
314 .need_gfx_hws = 1, .has_hotplug = 1,
315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
316 .has_llc = 1,
317 .has_ddi = 1,
318 .has_fpga_dbg = 1,
319 .has_fbc = 1,
320 GEN_DEFAULT_PIPEOFFSETS,
321 IVB_CURSOR_OFFSETS,
322};
323
324static const struct intel_device_info intel_broadwell_gt3d_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
328 .has_llc = 1,
329 .has_ddi = 1,
330 .has_fpga_dbg = 1,
331 .has_fbc = 1,
332 GEN_DEFAULT_PIPEOFFSETS,
333 IVB_CURSOR_OFFSETS,
334};
335
336static const struct intel_device_info intel_broadwell_gt3m_info = {
337 .gen = 8, .is_mobile = 1, .num_pipes = 3,
338 .need_gfx_hws = 1, .has_hotplug = 1,
339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
340 .has_llc = 1,
341 .has_ddi = 1,
342 .has_fpga_dbg = 1,
343 .has_fbc = 1,
344 GEN_DEFAULT_PIPEOFFSETS,
345 IVB_CURSOR_OFFSETS,
346};
347
348static const struct intel_device_info intel_cherryview_info = {
349 .gen = 8, .num_pipes = 3,
350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 .is_valleyview = 1,
353 .display_mmio_offset = VLV_DISPLAY_BASE,
354 GEN_CHV_PIPEOFFSETS,
355 CURSOR_OFFSETS,
356};
357
358static const struct intel_device_info intel_skylake_info = {
359 .is_preliminary = 1,
360 .is_skylake = 1,
361 .gen = 9, .num_pipes = 3,
362 .need_gfx_hws = 1, .has_hotplug = 1,
363 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
364 .has_llc = 1,
365 .has_ddi = 1,
366 .has_fbc = 1,
367 GEN_DEFAULT_PIPEOFFSETS,
368 IVB_CURSOR_OFFSETS,
369};
370
371static const struct intel_device_info intel_skylake_gt3_info = {
372 .is_preliminary = 1,
373 .is_skylake = 1,
374 .gen = 9, .num_pipes = 3,
375 .need_gfx_hws = 1, .has_hotplug = 1,
376 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
377 .has_llc = 1,
378 .has_ddi = 1,
379 .has_fbc = 1,
380 GEN_DEFAULT_PIPEOFFSETS,
381 IVB_CURSOR_OFFSETS,
382};
383
384
385
386
387
388
389
390#define INTEL_PCI_IDS \
391 INTEL_I830_IDS(&intel_i830_info), \
392 INTEL_I845G_IDS(&intel_845g_info), \
393 INTEL_I85X_IDS(&intel_i85x_info), \
394 INTEL_I865G_IDS(&intel_i865g_info), \
395 INTEL_I915G_IDS(&intel_i915g_info), \
396 INTEL_I915GM_IDS(&intel_i915gm_info), \
397 INTEL_I945G_IDS(&intel_i945g_info), \
398 INTEL_I945GM_IDS(&intel_i945gm_info), \
399 INTEL_I965G_IDS(&intel_i965g_info), \
400 INTEL_G33_IDS(&intel_g33_info), \
401 INTEL_I965GM_IDS(&intel_i965gm_info), \
402 INTEL_GM45_IDS(&intel_gm45_info), \
403 INTEL_G45_IDS(&intel_g45_info), \
404 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
405 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
406 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
407 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
408 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
409 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), \
410 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
411 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
412 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
413 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
414 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
415 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
416 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
417 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
418 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
419 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
420 INTEL_CHV_IDS(&intel_cherryview_info), \
421 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
422 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
423 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info) \
424
425static const struct pci_device_id pciidlist[] = {
426 INTEL_PCI_IDS,
427 {0, 0, 0}
428};
429
430#if defined(CONFIG_DRM_I915_KMS)
431MODULE_DEVICE_TABLE(pci, pciidlist);
432#endif
433
434void intel_detect_pch(struct drm_device *dev)
435{
436 struct drm_i915_private *dev_priv = dev->dev_private;
437 struct pci_dev *pch = NULL;
438
439
440
441
442 if (INTEL_INFO(dev)->num_pipes == 0) {
443 dev_priv->pch_type = PCH_NOP;
444 return;
445 }
446
447
448
449
450
451
452
453
454
455
456
457
458 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
459 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
460 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
461 dev_priv->pch_id = id;
462
463 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
464 dev_priv->pch_type = PCH_IBX;
465 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
466 WARN_ON(!IS_GEN5(dev));
467 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
468 dev_priv->pch_type = PCH_CPT;
469 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
470 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
471 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
472
473 dev_priv->pch_type = PCH_CPT;
474 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
475 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
476 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
477 dev_priv->pch_type = PCH_LPT;
478 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
479 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
480 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
481 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
482 dev_priv->pch_type = PCH_LPT;
483 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
484 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
485 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
486 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_SPT;
488 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
489 WARN_ON(!IS_SKYLAKE(dev));
490 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
491 dev_priv->pch_type = PCH_SPT;
492 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
493 WARN_ON(!IS_SKYLAKE(dev));
494 } else
495 continue;
496
497 break;
498 }
499 }
500 if (!pch)
501 DRM_DEBUG_KMS("No PCH found.\n");
502
503 pci_dev_put(pch);
504}
505
506bool i915_semaphore_is_enabled(struct drm_device *dev)
507{
508 if (INTEL_INFO(dev)->gen < 6)
509 return false;
510
511 if (i915.semaphores >= 0)
512 return i915.semaphores;
513
514
515 if (i915.enable_execlists)
516 return false;
517
518
519 if (IS_GEN8(dev))
520 return false;
521
522#ifdef CONFIG_INTEL_IOMMU
523
524 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
525 return false;
526#endif
527
528 return true;
529}
530
531void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
532{
533 spin_lock_irq(&dev_priv->irq_lock);
534
535 dev_priv->long_hpd_port_mask = 0;
536 dev_priv->short_hpd_port_mask = 0;
537 dev_priv->hpd_event_bits = 0;
538
539 spin_unlock_irq(&dev_priv->irq_lock);
540
541 cancel_work_sync(&dev_priv->dig_port_work);
542 cancel_work_sync(&dev_priv->hotplug_work);
543 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
544}
545
546static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
547{
548 struct drm_device *dev = dev_priv->dev;
549 struct drm_encoder *encoder;
550
551 drm_modeset_lock_all(dev);
552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
553 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
554
555 if (intel_encoder->suspend)
556 intel_encoder->suspend(intel_encoder);
557 }
558 drm_modeset_unlock_all(dev);
559}
560
561static int intel_suspend_complete(struct drm_i915_private *dev_priv);
562static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
563 bool rpm_resume);
564
565static int i915_drm_suspend(struct drm_device *dev)
566{
567 struct drm_i915_private *dev_priv = dev->dev_private;
568 struct drm_crtc *crtc;
569 pci_power_t opregion_target_state;
570 int error;
571
572
573 mutex_lock(&dev_priv->modeset_restore_lock);
574 dev_priv->modeset_restore = MODESET_SUSPENDED;
575 mutex_unlock(&dev_priv->modeset_restore_lock);
576
577
578
579 intel_display_set_init_power(dev_priv, true);
580
581 drm_kms_helper_poll_disable(dev);
582
583 pci_save_state(dev->pdev);
584
585 error = i915_gem_suspend(dev);
586 if (error) {
587 dev_err(&dev->pdev->dev,
588 "GEM idle failed, resume might fail\n");
589 return error;
590 }
591
592 intel_suspend_gt_powersave(dev);
593
594
595
596
597
598 drm_modeset_lock_all(dev);
599 for_each_crtc(dev, crtc)
600 intel_crtc_control(crtc, false);
601 drm_modeset_unlock_all(dev);
602
603 intel_dp_mst_suspend(dev);
604
605 intel_runtime_pm_disable_interrupts(dev_priv);
606 intel_hpd_cancel_work(dev_priv);
607
608 intel_suspend_encoders(dev_priv);
609
610 intel_suspend_hw(dev);
611
612 i915_gem_suspend_gtt_mappings(dev);
613
614 i915_save_state(dev);
615
616 opregion_target_state = PCI_D3cold;
617#if IS_ENABLED(CONFIG_ACPI_SLEEP)
618 if (acpi_target_system_state() < ACPI_STATE_S3)
619 opregion_target_state = PCI_D1;
620#endif
621 intel_opregion_notify_adapter(dev, opregion_target_state);
622
623 intel_uncore_forcewake_reset(dev, false);
624 intel_opregion_fini(dev);
625
626 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
627
628 dev_priv->suspend_count++;
629
630 intel_display_set_init_power(dev_priv, false);
631
632 return 0;
633}
634
635static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
636{
637 struct drm_i915_private *dev_priv = drm_dev->dev_private;
638 int ret;
639
640 ret = intel_suspend_complete(dev_priv);
641
642 if (ret) {
643 DRM_ERROR("Suspend complete failed: %d\n", ret);
644
645 return ret;
646 }
647
648 pci_disable_device(drm_dev->pdev);
649
650
651
652
653
654
655
656 if (!(hibernation &&
657 drm_dev->pdev->subsystem_vendor == PCI_VENDOR_ID_LENOVO &&
658 INTEL_INFO(dev_priv)->gen == 4))
659 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
660
661 return 0;
662}
663
664int i915_suspend_legacy(struct drm_device *dev, pm_message_t state)
665{
666 int error;
667
668 if (!dev || !dev->dev_private) {
669 DRM_ERROR("dev: %p\n", dev);
670 DRM_ERROR("DRM not initialized, aborting suspend.\n");
671 return -ENODEV;
672 }
673
674 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
675 state.event != PM_EVENT_FREEZE))
676 return -EINVAL;
677
678 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
679 return 0;
680
681 error = i915_drm_suspend(dev);
682 if (error)
683 return error;
684
685 return i915_drm_suspend_late(dev, false);
686}
687
688static int i915_drm_resume(struct drm_device *dev)
689{
690 struct drm_i915_private *dev_priv = dev->dev_private;
691
692 mutex_lock(&dev->struct_mutex);
693 i915_gem_restore_gtt_mappings(dev);
694 mutex_unlock(&dev->struct_mutex);
695
696 i915_restore_state(dev);
697 intel_opregion_setup(dev);
698
699 intel_init_pch_refclk(dev);
700 drm_mode_config_reset(dev);
701
702
703
704
705
706
707
708
709
710 intel_runtime_pm_enable_interrupts(dev_priv);
711
712 mutex_lock(&dev->struct_mutex);
713 if (i915_gem_init_hw(dev)) {
714 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
715 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
716 }
717 mutex_unlock(&dev->struct_mutex);
718
719 intel_modeset_init_hw(dev);
720
721 spin_lock_irq(&dev_priv->irq_lock);
722 if (dev_priv->display.hpd_irq_setup)
723 dev_priv->display.hpd_irq_setup(dev);
724 spin_unlock_irq(&dev_priv->irq_lock);
725
726 drm_modeset_lock_all(dev);
727 intel_modeset_setup_hw_state(dev, true);
728 drm_modeset_unlock_all(dev);
729
730 intel_dp_mst_resume(dev);
731
732
733
734
735
736
737
738 intel_hpd_init(dev_priv);
739
740 drm_helper_hpd_irq_event(dev);
741
742 intel_opregion_init(dev);
743
744 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
745
746 mutex_lock(&dev_priv->modeset_restore_lock);
747 dev_priv->modeset_restore = MODESET_DONE;
748 mutex_unlock(&dev_priv->modeset_restore_lock);
749
750 intel_opregion_notify_adapter(dev, PCI_D0);
751
752 drm_kms_helper_poll_enable(dev);
753
754 return 0;
755}
756
757static int i915_drm_resume_early(struct drm_device *dev)
758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 int ret = 0;
761
762
763
764
765
766
767
768
769
770
771 if (pci_enable_device(dev->pdev))
772 return -EIO;
773
774 pci_set_master(dev->pdev);
775
776 if (IS_VALLEYVIEW(dev_priv))
777 ret = vlv_resume_prepare(dev_priv, false);
778 if (ret)
779 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
780
781 intel_uncore_early_sanitize(dev, true);
782
783 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
784 hsw_disable_pc8(dev_priv);
785
786 intel_uncore_sanitize(dev);
787 intel_power_domains_init_hw(dev_priv);
788
789 return ret;
790}
791
792int i915_resume_legacy(struct drm_device *dev)
793{
794 int ret;
795
796 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
797 return 0;
798
799 ret = i915_drm_resume_early(dev);
800 if (ret)
801 return ret;
802
803 return i915_drm_resume(dev);
804}
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821int i915_reset(struct drm_device *dev)
822{
823 struct drm_i915_private *dev_priv = dev->dev_private;
824 bool simulated;
825 int ret;
826
827 if (!i915.reset)
828 return 0;
829
830 intel_reset_gt_powersave(dev);
831
832 mutex_lock(&dev->struct_mutex);
833
834 i915_gem_reset(dev);
835
836 simulated = dev_priv->gpu_error.stop_rings != 0;
837
838 ret = intel_gpu_reset(dev);
839
840
841 if (simulated) {
842 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
843 dev_priv->gpu_error.stop_rings = 0;
844 if (ret == -ENODEV) {
845 DRM_INFO("Reset not implemented, but ignoring "
846 "error for simulated gpu hangs\n");
847 ret = 0;
848 }
849 }
850
851 if (i915_stop_ring_allow_warn(dev_priv))
852 pr_notice("drm/i915: Resetting chip after gpu hang\n");
853
854 if (ret) {
855 DRM_ERROR("Failed to reset chip: %i\n", ret);
856 mutex_unlock(&dev->struct_mutex);
857 return ret;
858 }
859
860 intel_overlay_reset(dev_priv);
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878 dev_priv->gpu_error.reload_in_reset = true;
879
880 ret = i915_gem_init_hw(dev);
881
882 dev_priv->gpu_error.reload_in_reset = false;
883
884 mutex_unlock(&dev->struct_mutex);
885 if (ret) {
886 DRM_ERROR("Failed hw init on reset %d\n", ret);
887 return ret;
888 }
889
890
891
892
893
894
895
896 if (INTEL_INFO(dev)->gen > 5)
897 intel_enable_gt_powersave(dev);
898
899 return 0;
900}
901
902static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
903{
904 struct intel_device_info *intel_info =
905 (struct intel_device_info *) ent->driver_data;
906
907 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
908 DRM_INFO("This hardware requires preliminary hardware support.\n"
909 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
910 return -ENODEV;
911 }
912
913
914
915
916
917
918 if (PCI_FUNC(pdev->devfn))
919 return -ENODEV;
920
921 driver.driver_features &= ~(DRIVER_USE_AGP);
922
923 return drm_get_pci_dev(pdev, ent, &driver);
924}
925
926static void
927i915_pci_remove(struct pci_dev *pdev)
928{
929 struct drm_device *dev = pci_get_drvdata(pdev);
930
931 drm_put_dev(dev);
932}
933
934static int i915_pm_suspend(struct device *dev)
935{
936 struct pci_dev *pdev = to_pci_dev(dev);
937 struct drm_device *drm_dev = pci_get_drvdata(pdev);
938
939 if (!drm_dev || !drm_dev->dev_private) {
940 dev_err(dev, "DRM not initialized, aborting suspend.\n");
941 return -ENODEV;
942 }
943
944 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
945 return 0;
946
947 return i915_drm_suspend(drm_dev);
948}
949
950static int i915_pm_suspend_late(struct device *dev)
951{
952 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
953
954
955
956
957
958
959
960
961
962
963 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
964 return 0;
965
966 return i915_drm_suspend_late(drm_dev, false);
967}
968
969static int i915_pm_poweroff_late(struct device *dev)
970{
971 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
972
973 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
974 return 0;
975
976 return i915_drm_suspend_late(drm_dev, true);
977}
978
979static int i915_pm_resume_early(struct device *dev)
980{
981 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
982
983 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
984 return 0;
985
986 return i915_drm_resume_early(drm_dev);
987}
988
989static int i915_pm_resume(struct device *dev)
990{
991 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
992
993 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
994 return 0;
995
996 return i915_drm_resume(drm_dev);
997}
998
999static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1000{
1001 hsw_enable_pc8(dev_priv);
1002
1003 return 0;
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1033{
1034 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1035 int i;
1036
1037
1038 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1039 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1040 s->arb_mode = I915_READ(ARB_MODE);
1041 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1042 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1043
1044 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1045 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
1046
1047 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1048 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1049
1050 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1051 s->ecochk = I915_READ(GAM_ECOCHK);
1052 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1053 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1054
1055 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1056
1057
1058 s->g3dctl = I915_READ(VLV_G3DCTL);
1059 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1060 s->mbctl = I915_READ(GEN6_MBCTL);
1061
1062
1063 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1064 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1065 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1066 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1067 s->rstctl = I915_READ(GEN6_RSTCTL);
1068 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1069
1070
1071 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1072 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1073 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1074 s->ecobus = I915_READ(ECOBUS);
1075 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1076 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1077 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1078 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1079 s->rcedata = I915_READ(VLV_RCEDATA);
1080 s->spare2gh = I915_READ(VLV_SPAREG2H);
1081
1082
1083 s->gt_imr = I915_READ(GTIMR);
1084 s->gt_ier = I915_READ(GTIER);
1085 s->pm_imr = I915_READ(GEN6_PMIMR);
1086 s->pm_ier = I915_READ(GEN6_PMIER);
1087
1088 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1089 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1090
1091
1092 s->tilectl = I915_READ(TILECTL);
1093 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1094 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1095 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1096 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1097
1098
1099 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1100 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1101 s->pcbr = I915_READ(VLV_PCBR);
1102 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1103
1104
1105
1106
1107
1108
1109
1110
1111}
1112
1113static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1114{
1115 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1116 u32 val;
1117 int i;
1118
1119
1120 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1121 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1122 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1123 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1124 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1125
1126 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1127 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1128
1129 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1130 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1131
1132 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1133 I915_WRITE(GAM_ECOCHK, s->ecochk);
1134 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1135 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1136
1137 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1138
1139
1140 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1141 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1142 I915_WRITE(GEN6_MBCTL, s->mbctl);
1143
1144
1145 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1146 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1147 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1148 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1149 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1150 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1151
1152
1153 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1154 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1155 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1156 I915_WRITE(ECOBUS, s->ecobus);
1157 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1158 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1159 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1160 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1161 I915_WRITE(VLV_RCEDATA, s->rcedata);
1162 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1163
1164
1165 I915_WRITE(GTIMR, s->gt_imr);
1166 I915_WRITE(GTIER, s->gt_ier);
1167 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1168 I915_WRITE(GEN6_PMIER, s->pm_ier);
1169
1170 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1171 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1172
1173
1174 I915_WRITE(TILECTL, s->tilectl);
1175 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1176
1177
1178
1179
1180
1181 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1182 val &= VLV_GTLC_ALLOWWAKEREQ;
1183 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1184 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1185
1186 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1187 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1188 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1189 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1190
1191 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1192
1193
1194 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1195 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1196 I915_WRITE(VLV_PCBR, s->pcbr);
1197 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1198}
1199
1200int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1201{
1202 u32 val;
1203 int err;
1204
1205#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1206
1207 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1208 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1209 if (force_on)
1210 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1211 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1212
1213 if (!force_on)
1214 return 0;
1215
1216 err = wait_for(COND, 20);
1217 if (err)
1218 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1219 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1220
1221 return err;
1222#undef COND
1223}
1224
1225static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1226{
1227 u32 val;
1228 int err = 0;
1229
1230 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1231 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1232 if (allow)
1233 val |= VLV_GTLC_ALLOWWAKEREQ;
1234 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1235 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1236
1237#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1238 allow)
1239 err = wait_for(COND, 1);
1240 if (err)
1241 DRM_ERROR("timeout disabling GT waking\n");
1242 return err;
1243#undef COND
1244}
1245
1246static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1247 bool wait_for_on)
1248{
1249 u32 mask;
1250 u32 val;
1251 int err;
1252
1253 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1254 val = wait_for_on ? mask : 0;
1255#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1256 if (COND)
1257 return 0;
1258
1259 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1260 wait_for_on ? "on" : "off",
1261 I915_READ(VLV_GTLC_PW_STATUS));
1262
1263
1264
1265
1266
1267 err = wait_for(COND, 3);
1268 if (err)
1269 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1270 wait_for_on ? "on" : "off");
1271
1272 return err;
1273#undef COND
1274}
1275
1276static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1277{
1278 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1279 return;
1280
1281 DRM_ERROR("GT register access while GT waking disabled\n");
1282 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1283}
1284
1285static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1286{
1287 u32 mask;
1288 int err;
1289
1290
1291
1292
1293
1294 (void)vlv_wait_for_gt_wells(dev_priv, false);
1295
1296 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1297 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1298
1299 vlv_check_no_gt_access(dev_priv);
1300
1301 err = vlv_force_gfx_clock(dev_priv, true);
1302 if (err)
1303 goto err1;
1304
1305 err = vlv_allow_gt_wake(dev_priv, false);
1306 if (err)
1307 goto err2;
1308
1309 if (!IS_CHERRYVIEW(dev_priv->dev))
1310 vlv_save_gunit_s0ix_state(dev_priv);
1311
1312 err = vlv_force_gfx_clock(dev_priv, false);
1313 if (err)
1314 goto err2;
1315
1316 return 0;
1317
1318err2:
1319
1320 vlv_allow_gt_wake(dev_priv, true);
1321err1:
1322 vlv_force_gfx_clock(dev_priv, false);
1323
1324 return err;
1325}
1326
1327static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1328 bool rpm_resume)
1329{
1330 struct drm_device *dev = dev_priv->dev;
1331 int err;
1332 int ret;
1333
1334
1335
1336
1337
1338
1339 ret = vlv_force_gfx_clock(dev_priv, true);
1340
1341 if (!IS_CHERRYVIEW(dev_priv->dev))
1342 vlv_restore_gunit_s0ix_state(dev_priv);
1343
1344 err = vlv_allow_gt_wake(dev_priv, true);
1345 if (!ret)
1346 ret = err;
1347
1348 err = vlv_force_gfx_clock(dev_priv, false);
1349 if (!ret)
1350 ret = err;
1351
1352 vlv_check_no_gt_access(dev_priv);
1353
1354 if (rpm_resume) {
1355 intel_init_clock_gating(dev);
1356 i915_gem_restore_fences(dev);
1357 }
1358
1359 return ret;
1360}
1361
1362static int intel_runtime_suspend(struct device *device)
1363{
1364 struct pci_dev *pdev = to_pci_dev(device);
1365 struct drm_device *dev = pci_get_drvdata(pdev);
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int ret;
1368
1369 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1370 return -ENODEV;
1371
1372 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1373 return -ENODEV;
1374
1375 DRM_DEBUG_KMS("Suspending device\n");
1376
1377
1378
1379
1380
1381
1382
1383
1384 if (!mutex_trylock(&dev->struct_mutex)) {
1385 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1386
1387
1388
1389
1390 pm_runtime_mark_last_busy(device);
1391
1392 return -EAGAIN;
1393 }
1394
1395
1396
1397
1398 i915_gem_release_all_mmaps(dev_priv);
1399 mutex_unlock(&dev->struct_mutex);
1400
1401 intel_suspend_gt_powersave(dev);
1402 intel_runtime_pm_disable_interrupts(dev_priv);
1403
1404 ret = intel_suspend_complete(dev_priv);
1405 if (ret) {
1406 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1407 intel_runtime_pm_enable_interrupts(dev_priv);
1408
1409 return ret;
1410 }
1411
1412 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1413 intel_uncore_forcewake_reset(dev, false);
1414 dev_priv->pm.suspended = true;
1415
1416
1417
1418
1419
1420 if (IS_HASWELL(dev)) {
1421
1422
1423
1424
1425
1426
1427
1428 intel_opregion_notify_adapter(dev, PCI_D1);
1429 } else {
1430
1431
1432
1433
1434
1435
1436
1437
1438 intel_opregion_notify_adapter(dev, PCI_D3hot);
1439 }
1440
1441 assert_forcewakes_inactive(dev_priv);
1442
1443 DRM_DEBUG_KMS("Device suspended\n");
1444 return 0;
1445}
1446
1447static int intel_runtime_resume(struct device *device)
1448{
1449 struct pci_dev *pdev = to_pci_dev(device);
1450 struct drm_device *dev = pci_get_drvdata(pdev);
1451 struct drm_i915_private *dev_priv = dev->dev_private;
1452 int ret = 0;
1453
1454 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1455 return -ENODEV;
1456
1457 DRM_DEBUG_KMS("Resuming device\n");
1458
1459 intel_opregion_notify_adapter(dev, PCI_D0);
1460 dev_priv->pm.suspended = false;
1461
1462 if (IS_GEN6(dev_priv))
1463 intel_init_pch_refclk(dev);
1464 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1465 hsw_disable_pc8(dev_priv);
1466 else if (IS_VALLEYVIEW(dev_priv))
1467 ret = vlv_resume_prepare(dev_priv, true);
1468
1469
1470
1471
1472
1473 i915_gem_init_swizzling(dev);
1474 gen6_update_ring_freq(dev);
1475
1476 intel_runtime_pm_enable_interrupts(dev_priv);
1477 intel_enable_gt_powersave(dev);
1478
1479 if (ret)
1480 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1481 else
1482 DRM_DEBUG_KMS("Device resumed\n");
1483
1484 return ret;
1485}
1486
1487
1488
1489
1490
1491static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1492{
1493 struct drm_device *dev = dev_priv->dev;
1494 int ret;
1495
1496 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1497 ret = hsw_suspend_complete(dev_priv);
1498 else if (IS_VALLEYVIEW(dev))
1499 ret = vlv_suspend_complete(dev_priv);
1500 else
1501 ret = 0;
1502
1503 return ret;
1504}
1505
1506static const struct dev_pm_ops i915_pm_ops = {
1507
1508
1509
1510
1511 .suspend = i915_pm_suspend,
1512 .suspend_late = i915_pm_suspend_late,
1513 .resume_early = i915_pm_resume_early,
1514 .resume = i915_pm_resume,
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531 .freeze = i915_pm_suspend,
1532 .freeze_late = i915_pm_suspend_late,
1533 .thaw_early = i915_pm_resume_early,
1534 .thaw = i915_pm_resume,
1535 .poweroff = i915_pm_suspend,
1536 .poweroff_late = i915_pm_poweroff_late,
1537 .restore_early = i915_pm_resume_early,
1538 .restore = i915_pm_resume,
1539
1540
1541 .runtime_suspend = intel_runtime_suspend,
1542 .runtime_resume = intel_runtime_resume,
1543};
1544
1545static const struct vm_operations_struct i915_gem_vm_ops = {
1546 .fault = i915_gem_fault,
1547 .open = drm_gem_vm_open,
1548 .close = drm_gem_vm_close,
1549};
1550
1551static const struct file_operations i915_driver_fops = {
1552 .owner = THIS_MODULE,
1553 .open = drm_open,
1554 .release = drm_release,
1555 .unlocked_ioctl = drm_ioctl,
1556 .mmap = drm_gem_mmap,
1557 .poll = drm_poll,
1558 .read = drm_read,
1559#ifdef CONFIG_COMPAT
1560 .compat_ioctl = i915_compat_ioctl,
1561#endif
1562 .llseek = noop_llseek,
1563};
1564
1565static struct drm_driver driver = {
1566
1567
1568
1569 .driver_features =
1570 DRIVER_USE_AGP |
1571 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1572 DRIVER_RENDER,
1573 .load = i915_driver_load,
1574 .unload = i915_driver_unload,
1575 .open = i915_driver_open,
1576 .lastclose = i915_driver_lastclose,
1577 .preclose = i915_driver_preclose,
1578 .postclose = i915_driver_postclose,
1579 .set_busid = drm_pci_set_busid,
1580
1581
1582 .suspend = i915_suspend_legacy,
1583 .resume = i915_resume_legacy,
1584
1585 .device_is_agp = i915_driver_device_is_agp,
1586#if defined(CONFIG_DEBUG_FS)
1587 .debugfs_init = i915_debugfs_init,
1588 .debugfs_cleanup = i915_debugfs_cleanup,
1589#endif
1590 .gem_free_object = i915_gem_free_object,
1591 .gem_vm_ops = &i915_gem_vm_ops,
1592
1593 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1594 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1595 .gem_prime_export = i915_gem_prime_export,
1596 .gem_prime_import = i915_gem_prime_import,
1597
1598 .dumb_create = i915_gem_dumb_create,
1599 .dumb_map_offset = i915_gem_mmap_gtt,
1600 .dumb_destroy = drm_gem_dumb_destroy,
1601 .ioctls = i915_ioctls,
1602 .fops = &i915_driver_fops,
1603 .name = DRIVER_NAME,
1604 .desc = DRIVER_DESC,
1605 .date = DRIVER_DATE,
1606 .major = DRIVER_MAJOR,
1607 .minor = DRIVER_MINOR,
1608 .patchlevel = DRIVER_PATCHLEVEL,
1609};
1610
1611static struct pci_driver i915_pci_driver = {
1612 .name = DRIVER_NAME,
1613 .id_table = pciidlist,
1614 .probe = i915_pci_probe,
1615 .remove = i915_pci_remove,
1616 .driver.pm = &i915_pm_ops,
1617};
1618
1619static int __init i915_init(void)
1620{
1621 driver.num_ioctls = i915_max_ioctl;
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632#if defined(CONFIG_DRM_I915_KMS)
1633 if (i915.modeset != 0)
1634 driver.driver_features |= DRIVER_MODESET;
1635#endif
1636 if (i915.modeset == 1)
1637 driver.driver_features |= DRIVER_MODESET;
1638
1639#ifdef CONFIG_VGA_CONSOLE
1640 if (vgacon_text_force() && i915.modeset == -1)
1641 driver.driver_features &= ~DRIVER_MODESET;
1642#endif
1643
1644 if (!(driver.driver_features & DRIVER_MODESET)) {
1645 driver.get_vblank_timestamp = NULL;
1646
1647 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1648 return 0;
1649 }
1650
1651
1652
1653
1654
1655
1656 if (i915.nuclear_pageflip)
1657 driver.driver_features |= DRIVER_ATOMIC;
1658
1659 return drm_pci_init(&driver, &i915_pci_driver);
1660}
1661
1662static void __exit i915_exit(void)
1663{
1664 if (!(driver.driver_features & DRIVER_MODESET))
1665 return;
1666
1667 drm_pci_exit(&driver, &i915_pci_driver);
1668}
1669
1670module_init(i915_init);
1671module_exit(i915_exit);
1672
1673MODULE_AUTHOR("Tungsten Graphics, Inc.");
1674MODULE_AUTHOR("Intel Corporation");
1675
1676MODULE_DESCRIPTION(DRIVER_DESC);
1677MODULE_LICENSE("GPL and additional rights");
1678