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25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/async.h>
29#include <linux/i2c.h>
30#include <linux/hdmi.h>
31#include <drm/i915_drm.h>
32#include "i915_drv.h"
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_dp_mst_helper.h>
37#include <drm/drm_rect.h>
38#include <drm/drm_atomic.h>
39
40
41
42
43
44
45
46
47
48#define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
59 } else { \
60 cpu_relax(); \
61 } \
62 } \
63 ret__; \
64})
65
66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68#define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
70
71#define KHz(x) (1000 * (x))
72#define MHz(x) KHz(1000 * (x))
73
74
75
76
77
78
79
80
81#define MAX_OUTPUTS 6
82
83
84
85#define GEN2_CURSOR_WIDTH 64
86#define GEN2_CURSOR_HEIGHT 64
87#define MAX_CURSOR_WIDTH 256
88#define MAX_CURSOR_HEIGHT 256
89
90#define INTEL_I2C_BUS_DVO 1
91#define INTEL_I2C_BUS_SDVO 2
92
93
94
95enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108};
109
110#define INTEL_DVO_CHIP_NONE 0
111#define INTEL_DVO_CHIP_LVDS 1
112#define INTEL_DVO_CHIP_TMDS 2
113#define INTEL_DVO_CHIP_TVOUT 4
114
115#define INTEL_DSI_VIDEO_MODE 0
116#define INTEL_DSI_COMMAND_MODE 1
117
118struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
121};
122
123struct intel_fbdev {
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
128 int preferred_bpp;
129};
130
131struct intel_encoder {
132 struct drm_encoder base;
133
134
135
136
137 struct intel_crtc *new_crtc;
138
139 enum intel_output_type type;
140 unsigned int cloneable;
141 bool connectors_active;
142 void (*hot_plug)(struct intel_encoder *);
143 bool (*compute_config)(struct intel_encoder *,
144 struct intel_crtc_state *);
145 void (*pre_pll_enable)(struct intel_encoder *);
146 void (*pre_enable)(struct intel_encoder *);
147 void (*enable)(struct intel_encoder *);
148 void (*mode_set)(struct intel_encoder *intel_encoder);
149 void (*disable)(struct intel_encoder *);
150 void (*post_disable)(struct intel_encoder *);
151
152
153
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
155
156
157
158
159 void (*get_config)(struct intel_encoder *,
160 struct intel_crtc_state *pipe_config);
161
162
163
164
165
166 void (*suspend)(struct intel_encoder *);
167 int crtc_mask;
168 enum hpd_pin hpd_pin;
169};
170
171struct intel_panel {
172 struct drm_display_mode *fixed_mode;
173 struct drm_display_mode *downclock_mode;
174 int fitting_mode;
175
176
177 struct {
178 bool present;
179 u32 level;
180 u32 min;
181 u32 max;
182 bool enabled;
183 bool combination_mode;
184 bool active_low_pwm;
185 struct backlight_device *device;
186 } backlight;
187
188 void (*backlight_power)(struct intel_connector *, bool enable);
189};
190
191struct intel_connector {
192 struct drm_connector base;
193
194
195
196 struct intel_encoder *encoder;
197
198
199
200
201
202 struct intel_encoder *new_encoder;
203
204
205
206 bool (*get_hw_state)(struct intel_connector *);
207
208
209
210
211
212
213
214 void (*unregister)(struct intel_connector *);
215
216
217 struct intel_panel panel;
218
219
220 struct edid *edid;
221 struct edid *detect_edid;
222
223
224
225 u8 polled;
226
227 void *port;
228
229 struct intel_dp *mst_port;
230};
231
232typedef struct dpll {
233
234 int n;
235 int m1, m2;
236 int p1, p2;
237
238 int dot;
239 int vco;
240 int m;
241 int p;
242} intel_clock_t;
243
244struct intel_plane_state {
245 struct drm_plane_state base;
246 struct drm_rect src;
247 struct drm_rect dst;
248 struct drm_rect clip;
249 bool visible;
250
251
252
253
254
255 bool hides_primary;
256};
257
258struct intel_initial_plane_config {
259 struct intel_framebuffer *fb;
260 unsigned int tiling;
261 int size;
262 u32 base;
263};
264
265struct intel_crtc_state {
266 struct drm_crtc_state base;
267
268
269
270
271
272
273
274
275
276#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
277#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1)
278 unsigned long quirks;
279
280
281
282
283 int pipe_src_w, pipe_src_h;
284
285
286
287 bool has_pch_encoder;
288
289
290 bool has_infoframe;
291
292
293
294 enum transcoder cpu_transcoder;
295
296
297
298
299
300 bool limited_color_range;
301
302
303
304 bool has_dp_encoder;
305
306
307 bool has_hdmi_sink;
308
309
310
311 bool has_audio;
312
313
314
315
316
317 bool dither;
318
319
320 bool clock_set;
321
322
323
324 bool sdvo_tv_clock;
325
326
327
328
329
330
331 bool bw_constrained;
332
333
334
335 struct dpll dpll;
336
337
338 enum intel_dpll_id shared_dpll;
339
340
341
342
343
344 uint32_t ddi_pll_sel;
345
346
347 struct intel_dpll_hw_state dpll_hw_state;
348
349 int pipe_bpp;
350 struct intel_link_m_n dp_m_n;
351
352
353 struct intel_link_m_n dp_m2_n2;
354 bool has_drrs;
355
356
357
358
359
360
361 int port_clock;
362
363
364 unsigned pixel_multiplier;
365
366
367 struct {
368 u32 control;
369 u32 pgm_ratios;
370 u32 lvds_border_bits;
371 } gmch_pfit;
372
373
374 struct {
375 u32 pos;
376 u32 size;
377 bool enabled;
378 bool force_thru;
379 } pch_pfit;
380
381
382 int fdi_lanes;
383 struct intel_link_m_n fdi_m_n;
384
385 bool ips_enabled;
386
387 bool double_wide;
388
389 bool dp_encoder_is_mst;
390 int pbn;
391};
392
393struct intel_pipe_wm {
394 struct intel_wm_level wm[5];
395 uint32_t linetime;
396 bool fbc_wm_enabled;
397 bool pipe_enabled;
398 bool sprites_enabled;
399 bool sprites_scaled;
400};
401
402struct intel_mmio_flip {
403 struct drm_i915_gem_request *req;
404 struct work_struct work;
405};
406
407struct skl_pipe_wm {
408 struct skl_wm_level wm[8];
409 struct skl_wm_level trans_wm;
410 uint32_t linetime;
411};
412
413
414
415
416
417
418
419struct intel_crtc_atomic_commit {
420
421 bool evade;
422 unsigned start_vbl_count;
423
424
425 bool wait_for_flips;
426 bool disable_fbc;
427 bool pre_disable_primary;
428 bool update_wm;
429 unsigned disabled_planes;
430
431
432 unsigned fb_bits;
433 bool wait_vblank;
434 bool update_fbc;
435 bool post_enable_primary;
436 unsigned update_sprite_watermarks;
437};
438
439struct intel_crtc {
440 struct drm_crtc base;
441 enum pipe pipe;
442 enum plane plane;
443 u8 lut_r[256], lut_g[256], lut_b[256];
444
445
446
447
448
449 bool active;
450 unsigned long enabled_power_domains;
451 bool primary_enabled;
452 bool lowfreq_avail;
453 struct intel_overlay *overlay;
454 struct intel_unpin_work *unpin_work;
455
456 atomic_t unpin_work_count;
457
458
459
460
461 unsigned long dspaddr_offset;
462
463 struct drm_i915_gem_object *cursor_bo;
464 uint32_t cursor_addr;
465 uint32_t cursor_cntl;
466 uint32_t cursor_size;
467 uint32_t cursor_base;
468
469 struct intel_initial_plane_config plane_config;
470 struct intel_crtc_state *config;
471 struct intel_crtc_state *new_config;
472 bool new_enabled;
473
474
475 unsigned int reset_counter;
476
477
478 bool cpu_fifo_underrun_disabled;
479 bool pch_fifo_underrun_disabled;
480
481
482 struct {
483
484 struct intel_pipe_wm active;
485
486 struct skl_pipe_wm skl_active;
487 } wm;
488
489 int scanline_offset;
490 struct intel_mmio_flip mmio_flip;
491
492 struct intel_crtc_atomic_commit atomic;
493};
494
495struct intel_plane_wm_parameters {
496 uint32_t horiz_pixels;
497 uint32_t vert_pixels;
498 uint8_t bytes_per_pixel;
499 bool enabled;
500 bool scaled;
501 u64 tiling;
502 unsigned int rotation;
503};
504
505struct intel_plane {
506 struct drm_plane base;
507 int plane;
508 enum pipe pipe;
509 bool can_scale;
510 int max_downscale;
511
512
513 struct drm_intel_sprite_colorkey ckey;
514
515
516
517
518
519
520 struct intel_plane_wm_parameters wm;
521
522
523
524
525
526
527
528 void (*update_plane)(struct drm_plane *plane,
529 struct drm_crtc *crtc,
530 struct drm_framebuffer *fb,
531 int crtc_x, int crtc_y,
532 unsigned int crtc_w, unsigned int crtc_h,
533 uint32_t x, uint32_t y,
534 uint32_t src_w, uint32_t src_h);
535 void (*disable_plane)(struct drm_plane *plane,
536 struct drm_crtc *crtc);
537 int (*check_plane)(struct drm_plane *plane,
538 struct intel_plane_state *state);
539 void (*commit_plane)(struct drm_plane *plane,
540 struct intel_plane_state *state);
541};
542
543struct intel_watermark_params {
544 unsigned long fifo_size;
545 unsigned long max_wm;
546 unsigned long default_wm;
547 unsigned long guard_size;
548 unsigned long cacheline_size;
549};
550
551struct cxsr_latency {
552 int is_desktop;
553 int is_ddr3;
554 unsigned long fsb_freq;
555 unsigned long mem_freq;
556 unsigned long display_sr;
557 unsigned long display_hpll_disable;
558 unsigned long cursor_sr;
559 unsigned long cursor_hpll_disable;
560};
561
562#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
563#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
564#define to_intel_connector(x) container_of(x, struct intel_connector, base)
565#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
566#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
567#define to_intel_plane(x) container_of(x, struct intel_plane, base)
568#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
569#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
570
571struct intel_hdmi {
572 u32 hdmi_reg;
573 int ddc_bus;
574 uint32_t color_range;
575 bool color_range_auto;
576 bool has_hdmi_sink;
577 bool has_audio;
578 enum hdmi_force_audio force_audio;
579 bool rgb_quant_range_selectable;
580 enum hdmi_picture_aspect aspect_ratio;
581 void (*write_infoframe)(struct drm_encoder *encoder,
582 enum hdmi_infoframe_type type,
583 const void *frame, ssize_t len);
584 void (*set_infoframes)(struct drm_encoder *encoder,
585 bool enable,
586 struct drm_display_mode *adjusted_mode);
587 bool (*infoframe_enabled)(struct drm_encoder *encoder);
588};
589
590struct intel_dp_mst_encoder;
591#define DP_MAX_DOWNSTREAM_PORTS 0x10
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607enum link_m_n_set {
608
609 M1_N1 = 0,
610 M2_N2
611};
612
613struct intel_dp {
614 uint32_t output_reg;
615 uint32_t aux_ch_ctl_reg;
616 uint32_t DP;
617 bool has_audio;
618 enum hdmi_force_audio force_audio;
619 uint32_t color_range;
620 bool color_range_auto;
621 uint8_t link_bw;
622 uint8_t rate_select;
623 uint8_t lane_count;
624 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
625 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
626 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
627
628 uint8_t num_sink_rates;
629 int sink_rates[DP_MAX_SUPPORTED_RATES];
630 struct drm_dp_aux aux;
631 uint8_t train_set[4];
632 int panel_power_up_delay;
633 int panel_power_down_delay;
634 int panel_power_cycle_delay;
635 int backlight_on_delay;
636 int backlight_off_delay;
637 struct delayed_work panel_vdd_work;
638 bool want_panel_vdd;
639 unsigned long last_power_cycle;
640 unsigned long last_power_on;
641 unsigned long last_backlight_off;
642
643 struct notifier_block edp_notifier;
644
645
646
647
648
649 enum pipe pps_pipe;
650 struct edp_power_seq pps_delays;
651
652 bool use_tps3;
653 bool can_mst;
654 bool is_mst;
655 int active_mst_links;
656
657 struct intel_connector *attached_connector;
658
659
660 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
661 struct drm_dp_mst_topology_mgr mst_mgr;
662
663 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
664
665
666
667
668 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
669 bool has_aux_irq,
670 int send_bytes,
671 uint32_t aux_clock_divider);
672};
673
674struct intel_digital_port {
675 struct intel_encoder base;
676 enum port port;
677 u32 saved_port_bits;
678 struct intel_dp dp;
679 struct intel_hdmi hdmi;
680 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
681};
682
683struct intel_dp_mst_encoder {
684 struct intel_encoder base;
685 enum pipe pipe;
686 struct intel_digital_port *primary;
687 void *port;
688};
689
690static inline int
691vlv_dport_to_channel(struct intel_digital_port *dport)
692{
693 switch (dport->port) {
694 case PORT_B:
695 case PORT_D:
696 return DPIO_CH0;
697 case PORT_C:
698 return DPIO_CH1;
699 default:
700 BUG();
701 }
702}
703
704static inline int
705vlv_pipe_to_channel(enum pipe pipe)
706{
707 switch (pipe) {
708 case PIPE_A:
709 case PIPE_C:
710 return DPIO_CH0;
711 case PIPE_B:
712 return DPIO_CH1;
713 default:
714 BUG();
715 }
716}
717
718static inline struct drm_crtc *
719intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
720{
721 struct drm_i915_private *dev_priv = dev->dev_private;
722 return dev_priv->pipe_to_crtc_mapping[pipe];
723}
724
725static inline struct drm_crtc *
726intel_get_crtc_for_plane(struct drm_device *dev, int plane)
727{
728 struct drm_i915_private *dev_priv = dev->dev_private;
729 return dev_priv->plane_to_crtc_mapping[plane];
730}
731
732struct intel_unpin_work {
733 struct work_struct work;
734 struct drm_crtc *crtc;
735 struct drm_framebuffer *old_fb;
736 struct drm_i915_gem_object *pending_flip_obj;
737 struct drm_pending_vblank_event *event;
738 atomic_t pending;
739#define INTEL_FLIP_INACTIVE 0
740#define INTEL_FLIP_PENDING 1
741#define INTEL_FLIP_COMPLETE 2
742 u32 flip_count;
743 u32 gtt_offset;
744 struct drm_i915_gem_request *flip_queued_req;
745 int flip_queued_vblank;
746 int flip_ready_vblank;
747 bool enable_stall_check;
748};
749
750struct intel_set_config {
751 struct drm_encoder **save_connector_encoders;
752 struct drm_crtc **save_encoder_crtcs;
753 bool *save_crtc_enabled;
754
755 bool fb_changed;
756 bool mode_changed;
757};
758
759struct intel_load_detect_pipe {
760 struct drm_framebuffer *release_fb;
761 bool load_detect_temp;
762 int dpms_mode;
763};
764
765static inline struct intel_encoder *
766intel_attached_encoder(struct drm_connector *connector)
767{
768 return to_intel_connector(connector)->encoder;
769}
770
771static inline struct intel_digital_port *
772enc_to_dig_port(struct drm_encoder *encoder)
773{
774 return container_of(encoder, struct intel_digital_port, base.base);
775}
776
777static inline struct intel_dp_mst_encoder *
778enc_to_mst(struct drm_encoder *encoder)
779{
780 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
781}
782
783static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
784{
785 return &enc_to_dig_port(encoder)->dp;
786}
787
788static inline struct intel_digital_port *
789dp_to_dig_port(struct intel_dp *intel_dp)
790{
791 return container_of(intel_dp, struct intel_digital_port, dp);
792}
793
794static inline struct intel_digital_port *
795hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
796{
797 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
798}
799
800
801
802
803
804static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
805{
806 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
807}
808
809
810bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
811 enum pipe pipe, bool enable);
812bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
813 enum transcoder pch_transcoder,
814 bool enable);
815void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
816 enum pipe pipe);
817void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
818 enum transcoder pch_transcoder);
819void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
820
821
822void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
823void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
824void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
825void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
826void gen6_reset_rps_interrupts(struct drm_device *dev);
827void gen6_enable_rps_interrupts(struct drm_device *dev);
828void gen6_disable_rps_interrupts(struct drm_device *dev);
829u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
830void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
831void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
832static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
833{
834
835
836
837
838 return dev_priv->pm.irqs_enabled;
839}
840
841int intel_get_crtc_scanline(struct intel_crtc *crtc);
842void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
843 unsigned int pipe_mask);
844
845
846void intel_crt_init(struct drm_device *dev);
847
848
849
850void intel_prepare_ddi(struct drm_device *dev);
851void hsw_fdi_link_train(struct drm_crtc *crtc);
852void intel_ddi_init(struct drm_device *dev, enum port port);
853enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
854bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
855int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
856void intel_ddi_pll_init(struct drm_device *dev);
857void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
858void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
859 enum transcoder cpu_transcoder);
860void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
861void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
862bool intel_ddi_pll_select(struct intel_crtc *crtc,
863 struct intel_crtc_state *crtc_state);
864void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
865void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
866bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
867void intel_ddi_fdi_disable(struct drm_crtc *crtc);
868void intel_ddi_get_config(struct intel_encoder *encoder,
869 struct intel_crtc_state *pipe_config);
870
871void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
872void intel_ddi_clock_get(struct intel_encoder *encoder,
873 struct intel_crtc_state *pipe_config);
874void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
875
876
877void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
878 struct intel_engine_cs *ring,
879 enum fb_op_origin origin);
880void intel_frontbuffer_flip_prepare(struct drm_device *dev,
881 unsigned frontbuffer_bits);
882void intel_frontbuffer_flip_complete(struct drm_device *dev,
883 unsigned frontbuffer_bits);
884void intel_frontbuffer_flush(struct drm_device *dev,
885 unsigned frontbuffer_bits);
886
887
888
889
890
891
892
893
894
895
896
897static inline
898void intel_frontbuffer_flip(struct drm_device *dev,
899 unsigned frontbuffer_bits)
900{
901 intel_frontbuffer_flush(dev, frontbuffer_bits);
902}
903
904unsigned int intel_fb_align_height(struct drm_device *dev,
905 unsigned int height,
906 uint32_t pixel_format,
907 uint64_t fb_format_modifier);
908void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
909
910u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
911 uint32_t pixel_format);
912
913
914void intel_init_audio(struct drm_device *dev);
915void intel_audio_codec_enable(struct intel_encoder *encoder);
916void intel_audio_codec_disable(struct intel_encoder *encoder);
917void i915_audio_component_init(struct drm_i915_private *dev_priv);
918void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
919
920
921extern const struct drm_plane_funcs intel_plane_funcs;
922bool intel_has_pending_fb_unpin(struct drm_device *dev);
923int intel_pch_rawclk(struct drm_device *dev);
924void intel_mark_busy(struct drm_device *dev);
925void intel_mark_idle(struct drm_device *dev);
926void intel_crtc_restore_mode(struct drm_crtc *crtc);
927void intel_crtc_control(struct drm_crtc *crtc, bool enable);
928void intel_crtc_update_dpms(struct drm_crtc *crtc);
929void intel_encoder_destroy(struct drm_encoder *encoder);
930int intel_connector_init(struct intel_connector *);
931struct intel_connector *intel_connector_alloc(void);
932void intel_connector_dpms(struct drm_connector *, int mode);
933bool intel_connector_get_hw_state(struct intel_connector *connector);
934void intel_modeset_check_state(struct drm_device *dev);
935bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
936 struct intel_digital_port *port);
937void intel_connector_attach_encoder(struct intel_connector *connector,
938 struct intel_encoder *encoder);
939struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
940struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
941 struct drm_crtc *crtc);
942enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
943int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
944 struct drm_file *file_priv);
945enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
946 enum pipe pipe);
947bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
948static inline void
949intel_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 drm_wait_one_vblank(dev, pipe);
952}
953int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
954void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
955 struct intel_digital_port *dport);
956bool intel_get_load_detect_pipe(struct drm_connector *connector,
957 struct drm_display_mode *mode,
958 struct intel_load_detect_pipe *old,
959 struct drm_modeset_acquire_ctx *ctx);
960void intel_release_load_detect_pipe(struct drm_connector *connector,
961 struct intel_load_detect_pipe *old,
962 struct drm_modeset_acquire_ctx *ctx);
963int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
964 struct drm_framebuffer *fb,
965 const struct drm_plane_state *plane_state,
966 struct intel_engine_cs *pipelined);
967struct drm_framebuffer *
968__intel_framebuffer_create(struct drm_device *dev,
969 struct drm_mode_fb_cmd2 *mode_cmd,
970 struct drm_i915_gem_object *obj);
971void intel_prepare_page_flip(struct drm_device *dev, int plane);
972void intel_finish_page_flip(struct drm_device *dev, int pipe);
973void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
974void intel_check_page_flip(struct drm_device *dev, int pipe);
975int intel_prepare_plane_fb(struct drm_plane *plane,
976 struct drm_framebuffer *fb,
977 const struct drm_plane_state *new_state);
978void intel_cleanup_plane_fb(struct drm_plane *plane,
979 struct drm_framebuffer *fb,
980 const struct drm_plane_state *old_state);
981int intel_plane_atomic_get_property(struct drm_plane *plane,
982 const struct drm_plane_state *state,
983 struct drm_property *property,
984 uint64_t *val);
985int intel_plane_atomic_set_property(struct drm_plane *plane,
986 struct drm_plane_state *state,
987 struct drm_property *property,
988 uint64_t val);
989
990unsigned int
991intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
992 uint64_t fb_format_modifier);
993
994static inline bool
995intel_rotation_90_or_270(unsigned int rotation)
996{
997 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
998}
999
1000bool intel_wm_need_update(struct drm_plane *plane,
1001 struct drm_plane_state *state);
1002
1003
1004struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1005void assert_shared_dpll(struct drm_i915_private *dev_priv,
1006 struct intel_shared_dpll *pll,
1007 bool state);
1008#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1009#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1010struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1011 struct intel_crtc_state *state);
1012void intel_put_shared_dpll(struct intel_crtc *crtc);
1013
1014void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1015 const struct dpll *dpll);
1016void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1017
1018
1019void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1020 enum pipe pipe);
1021void assert_pll(struct drm_i915_private *dev_priv,
1022 enum pipe pipe, bool state);
1023#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1024#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1025void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1026 enum pipe pipe, bool state);
1027#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1028#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1029void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1030#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1031#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1032unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1033 unsigned int tiling_mode,
1034 unsigned int bpp,
1035 unsigned int pitch);
1036void intel_prepare_reset(struct drm_device *dev);
1037void intel_finish_reset(struct drm_device *dev);
1038void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1039void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1040void intel_dp_get_m_n(struct intel_crtc *crtc,
1041 struct intel_crtc_state *pipe_config);
1042void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1043int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1044void
1045ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1046 int dotclock);
1047bool intel_crtc_active(struct drm_crtc *crtc);
1048void hsw_enable_ips(struct intel_crtc *crtc);
1049void hsw_disable_ips(struct intel_crtc *crtc);
1050enum intel_display_power_domain
1051intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1052void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1053 struct intel_crtc_state *pipe_config);
1054void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1055void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1056
1057unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1058 struct drm_i915_gem_object *obj);
1059
1060
1061void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1062bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1063 struct intel_connector *intel_connector);
1064void intel_dp_start_link_train(struct intel_dp *intel_dp);
1065void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1066void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1067void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1068void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1069int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1070bool intel_dp_compute_config(struct intel_encoder *encoder,
1071 struct intel_crtc_state *pipe_config);
1072bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1073enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1074 bool long_hpd);
1075void intel_edp_backlight_on(struct intel_dp *intel_dp);
1076void intel_edp_backlight_off(struct intel_dp *intel_dp);
1077void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1078void intel_edp_panel_on(struct intel_dp *intel_dp);
1079void intel_edp_panel_off(struct intel_dp *intel_dp);
1080void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1081void intel_dp_mst_suspend(struct drm_device *dev);
1082void intel_dp_mst_resume(struct drm_device *dev);
1083int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1084int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1085void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1086void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1087uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1088void intel_plane_destroy(struct drm_plane *plane);
1089void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1090void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1091void intel_edp_drrs_invalidate(struct drm_device *dev,
1092 unsigned frontbuffer_bits);
1093void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1094
1095
1096int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1097void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1098
1099void intel_dsi_init(struct drm_device *dev);
1100
1101
1102
1103void intel_dvo_init(struct drm_device *dev);
1104
1105
1106
1107#ifdef CONFIG_DRM_I915_FBDEV
1108extern int intel_fbdev_init(struct drm_device *dev);
1109extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1110extern void intel_fbdev_fini(struct drm_device *dev);
1111extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1112extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1113extern void intel_fbdev_restore_mode(struct drm_device *dev);
1114#else
1115static inline int intel_fbdev_init(struct drm_device *dev)
1116{
1117 return 0;
1118}
1119
1120static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1121{
1122}
1123
1124static inline void intel_fbdev_fini(struct drm_device *dev)
1125{
1126}
1127
1128static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1129{
1130}
1131
1132static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1133{
1134}
1135#endif
1136
1137
1138bool intel_fbc_enabled(struct drm_device *dev);
1139void intel_fbc_update(struct drm_device *dev);
1140void intel_fbc_init(struct drm_i915_private *dev_priv);
1141void intel_fbc_disable(struct drm_device *dev);
1142void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1143 unsigned int frontbuffer_bits,
1144 enum fb_op_origin origin);
1145void intel_fbc_flush(struct drm_i915_private *dev_priv,
1146 unsigned int frontbuffer_bits);
1147
1148
1149void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1150void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1151 struct intel_connector *intel_connector);
1152struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1153bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_state *pipe_config);
1155
1156
1157
1158void intel_lvds_init(struct drm_device *dev);
1159bool intel_is_dual_link_lvds(struct drm_device *dev);
1160
1161
1162
1163int intel_connector_update_modes(struct drm_connector *connector,
1164 struct edid *edid);
1165int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1166void intel_attach_force_audio_property(struct drm_connector *connector);
1167void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1168
1169
1170
1171void intel_setup_overlay(struct drm_device *dev);
1172void intel_cleanup_overlay(struct drm_device *dev);
1173int intel_overlay_switch_off(struct intel_overlay *overlay);
1174int intel_overlay_put_image(struct drm_device *dev, void *data,
1175 struct drm_file *file_priv);
1176int intel_overlay_attrs(struct drm_device *dev, void *data,
1177 struct drm_file *file_priv);
1178void intel_overlay_reset(struct drm_i915_private *dev_priv);
1179
1180
1181
1182int intel_panel_init(struct intel_panel *panel,
1183 struct drm_display_mode *fixed_mode,
1184 struct drm_display_mode *downclock_mode);
1185void intel_panel_fini(struct intel_panel *panel);
1186void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1187 struct drm_display_mode *adjusted_mode);
1188void intel_pch_panel_fitting(struct intel_crtc *crtc,
1189 struct intel_crtc_state *pipe_config,
1190 int fitting_mode);
1191void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1192 struct intel_crtc_state *pipe_config,
1193 int fitting_mode);
1194void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1195 u32 level, u32 max);
1196int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1197void intel_panel_enable_backlight(struct intel_connector *connector);
1198void intel_panel_disable_backlight(struct intel_connector *connector);
1199void intel_panel_destroy_backlight(struct drm_connector *connector);
1200void intel_panel_init_backlight_funcs(struct drm_device *dev);
1201enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1202extern struct drm_display_mode *intel_find_panel_downclock(
1203 struct drm_device *dev,
1204 struct drm_display_mode *fixed_mode,
1205 struct drm_connector *connector);
1206void intel_backlight_register(struct drm_device *dev);
1207void intel_backlight_unregister(struct drm_device *dev);
1208
1209
1210
1211void intel_psr_enable(struct intel_dp *intel_dp);
1212void intel_psr_disable(struct intel_dp *intel_dp);
1213void intel_psr_invalidate(struct drm_device *dev,
1214 unsigned frontbuffer_bits);
1215void intel_psr_flush(struct drm_device *dev,
1216 unsigned frontbuffer_bits);
1217void intel_psr_init(struct drm_device *dev);
1218
1219
1220int intel_power_domains_init(struct drm_i915_private *);
1221void intel_power_domains_fini(struct drm_i915_private *);
1222void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1223void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1224
1225bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1226 enum intel_display_power_domain domain);
1227bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1228 enum intel_display_power_domain domain);
1229void intel_display_power_get(struct drm_i915_private *dev_priv,
1230 enum intel_display_power_domain domain);
1231void intel_display_power_put(struct drm_i915_private *dev_priv,
1232 enum intel_display_power_domain domain);
1233void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1234void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1235void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1236void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1237void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1238
1239void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1240
1241
1242void intel_init_clock_gating(struct drm_device *dev);
1243void intel_suspend_hw(struct drm_device *dev);
1244int ilk_wm_max_level(const struct drm_device *dev);
1245void intel_update_watermarks(struct drm_crtc *crtc);
1246void intel_update_sprite_watermarks(struct drm_plane *plane,
1247 struct drm_crtc *crtc,
1248 uint32_t sprite_width,
1249 uint32_t sprite_height,
1250 int pixel_size,
1251 bool enabled, bool scaled);
1252void intel_init_pm(struct drm_device *dev);
1253void intel_pm_setup(struct drm_device *dev);
1254void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1255void intel_gpu_ips_teardown(void);
1256void intel_init_gt_powersave(struct drm_device *dev);
1257void intel_cleanup_gt_powersave(struct drm_device *dev);
1258void intel_enable_gt_powersave(struct drm_device *dev);
1259void intel_disable_gt_powersave(struct drm_device *dev);
1260void intel_suspend_gt_powersave(struct drm_device *dev);
1261void intel_reset_gt_powersave(struct drm_device *dev);
1262void gen6_update_ring_freq(struct drm_device *dev);
1263void gen6_rps_busy(struct drm_i915_private *dev_priv);
1264void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1265void gen6_rps_idle(struct drm_i915_private *dev_priv);
1266void gen6_rps_boost(struct drm_i915_private *dev_priv);
1267void ilk_wm_get_hw_state(struct drm_device *dev);
1268void skl_wm_get_hw_state(struct drm_device *dev);
1269void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1270 struct skl_ddb_allocation *ddb );
1271
1272
1273
1274bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1275
1276
1277
1278int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1279void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1280 enum plane plane);
1281int intel_plane_restore(struct drm_plane *plane);
1282int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1283 struct drm_file *file_priv);
1284bool intel_pipe_update_start(struct intel_crtc *crtc,
1285 uint32_t *start_vbl_count);
1286void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1287void intel_post_enable_primary(struct drm_crtc *crtc);
1288void intel_pre_disable_primary(struct drm_crtc *crtc);
1289
1290
1291void intel_tv_init(struct drm_device *dev);
1292
1293
1294int intel_atomic_check(struct drm_device *dev,
1295 struct drm_atomic_state *state);
1296int intel_atomic_commit(struct drm_device *dev,
1297 struct drm_atomic_state *state,
1298 bool async);
1299int intel_connector_atomic_get_property(struct drm_connector *connector,
1300 const struct drm_connector_state *state,
1301 struct drm_property *property,
1302 uint64_t *val);
1303struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1304void intel_crtc_destroy_state(struct drm_crtc *crtc,
1305 struct drm_crtc_state *state);
1306static inline struct intel_crtc_state *
1307intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1308 struct intel_crtc *crtc)
1309{
1310 struct drm_crtc_state *crtc_state;
1311 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1312 if (IS_ERR(crtc_state))
1313 return ERR_PTR(PTR_ERR(crtc_state));
1314
1315 return to_intel_crtc_state(crtc_state);
1316}
1317
1318
1319struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1320struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1321void intel_plane_destroy_state(struct drm_plane *plane,
1322 struct drm_plane_state *state);
1323extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1324
1325#endif
1326