1#ifndef MDP5_XML
2#define MDP5_XML
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40enum mdp5_intf_type {
41 INTF_DISABLED = 0,
42 INTF_DSI = 1,
43 INTF_HDMI = 3,
44 INTF_LCDC = 5,
45 INTF_eDP = 9,
46 INTF_VIRTUAL = 100,
47 INTF_WB = 101,
48};
49
50enum mdp5_intfnum {
51 NO_INTF = 0,
52 INTF0 = 1,
53 INTF1 = 2,
54 INTF2 = 3,
55 INTF3 = 4,
56};
57
58enum mdp5_pipe {
59 SSPP_VIG0 = 0,
60 SSPP_VIG1 = 1,
61 SSPP_VIG2 = 2,
62 SSPP_RGB0 = 3,
63 SSPP_RGB1 = 4,
64 SSPP_RGB2 = 5,
65 SSPP_DMA0 = 6,
66 SSPP_DMA1 = 7,
67 SSPP_VIG3 = 8,
68 SSPP_RGB3 = 9,
69};
70
71enum mdp5_ctl_mode {
72 MODE_NONE = 0,
73 MODE_WB_0_BLOCK = 1,
74 MODE_WB_1_BLOCK = 2,
75 MODE_WB_0_LINE = 3,
76 MODE_WB_1_LINE = 4,
77 MODE_WB_2_LINE = 5,
78};
79
80enum mdp5_pack_3d {
81 PACK_3D_FRAME_INT = 0,
82 PACK_3D_H_ROW_INT = 1,
83 PACK_3D_V_ROW_INT = 2,
84 PACK_3D_COL_INT = 3,
85};
86
87enum mdp5_scale_filter {
88 SCALE_FILTER_NEAREST = 0,
89 SCALE_FILTER_BIL = 1,
90 SCALE_FILTER_PCMN = 2,
91 SCALE_FILTER_CA = 3,
92};
93
94enum mdp5_pipe_bwc {
95 BWC_LOSSLESS = 0,
96 BWC_Q_HIGH = 1,
97 BWC_Q_MED = 2,
98};
99
100enum mdp5_cursor_format {
101 CURSOR_FMT_ARGB8888 = 0,
102 CURSOR_FMT_ARGB1555 = 2,
103 CURSOR_FMT_ARGB4444 = 4,
104};
105
106enum mdp5_cursor_alpha {
107 CURSOR_ALPHA_CONST = 0,
108 CURSOR_ALPHA_PER_PIXEL = 2,
109};
110
111enum mdp5_igc_type {
112 IGC_VIG = 0,
113 IGC_RGB = 1,
114 IGC_DMA = 2,
115 IGC_DSPP = 3,
116};
117
118enum mdp5_data_format {
119 DATA_FORMAT_RGB = 0,
120 DATA_FORMAT_YUV = 1,
121};
122
123#define MDP5_IRQ_WB_0_DONE 0x00000001
124#define MDP5_IRQ_WB_1_DONE 0x00000002
125#define MDP5_IRQ_WB_2_DONE 0x00000010
126#define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
127#define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
128#define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
129#define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
130#define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
131#define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
132#define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
133#define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
134#define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
135#define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
136#define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
137#define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
138#define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
139#define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
140#define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
141#define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
142#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
143#define MDP5_IRQ_INTF0_VSYNC 0x02000000
144#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
145#define MDP5_IRQ_INTF1_VSYNC 0x08000000
146#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
147#define MDP5_IRQ_INTF2_VSYNC 0x20000000
148#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
149#define MDP5_IRQ_INTF3_VSYNC 0x80000000
150#define REG_MDSS_HW_VERSION 0x00000000
151#define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
152#define MDSS_HW_VERSION_STEP__SHIFT 0
153static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
154{
155 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
156}
157#define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
158#define MDSS_HW_VERSION_MINOR__SHIFT 16
159static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
160{
161 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
162}
163#define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
164#define MDSS_HW_VERSION_MAJOR__SHIFT 28
165static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
166{
167 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
168}
169
170#define REG_MDSS_HW_INTR_STATUS 0x00000010
171#define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
172#define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
173#define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
174#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
175#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
176
177static inline uint32_t __offset_MDP(uint32_t idx)
178{
179 switch (idx) {
180 case 0: return (mdp5_cfg->mdp.base[0]);
181 default: return INVALID_IDX(idx);
182 }
183}
184static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
185
186static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }
187#define MDP5_MDP_HW_VERSION_STEP__MASK 0x0000ffff
188#define MDP5_MDP_HW_VERSION_STEP__SHIFT 0
189static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)
190{
191 return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK;
192}
193#define MDP5_MDP_HW_VERSION_MINOR__MASK 0x0fff0000
194#define MDP5_MDP_HW_VERSION_MINOR__SHIFT 16
195static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)
196{
197 return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK;
198}
199#define MDP5_MDP_HW_VERSION_MAJOR__MASK 0xf0000000
200#define MDP5_MDP_HW_VERSION_MAJOR__SHIFT 28
201static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val)
202{
203 return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK;
204}
205
206static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); }
207#define MDP5_MDP_DISP_INTF_SEL_INTF0__MASK 0x000000ff
208#define MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT 0
209static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
210{
211 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK;
212}
213#define MDP5_MDP_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
214#define MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT 8
215static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
216{
217 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK;
218}
219#define MDP5_MDP_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
220#define MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT 16
221static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
222{
223 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK;
224}
225#define MDP5_MDP_DISP_INTF_SEL_INTF3__MASK 0xff000000
226#define MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT 24
227static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
228{
229 return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK;
230}
231
232static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); }
233
234static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); }
235
236static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); }
237
238static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); }
239
240static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); }
241
242static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); }
243
244static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); }
245#define MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
246
247static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
248
249static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; }
250#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
251#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
252static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
253{
254 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK;
255}
256#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
257#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
258static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
259{
260 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK;
261}
262#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
263#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
264static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
265{
266 return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK;
267}
268
269static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
270
271static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; }
272#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
273#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
274static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
275{
276 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK;
277}
278#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
279#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
280static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
281{
282 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK;
283}
284#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
285#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
286static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
287{
288 return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK;
289}
290
291static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
292{
293 switch (idx) {
294 case IGC_VIG: return 0x00000200;
295 case IGC_RGB: return 0x00000210;
296 case IGC_DMA: return 0x00000220;
297 case IGC_DSPP: return 0x00000300;
298 default: return INVALID_IDX(idx);
299 }
300}
301static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); }
302
303static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
304
305static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; }
306#define MDP5_MDP_IGC_LUT_REG_VAL__MASK 0x00000fff
307#define MDP5_MDP_IGC_LUT_REG_VAL__SHIFT 0
308static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)
309{
310 return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK;
311}
312#define MDP5_MDP_IGC_LUT_REG_INDEX_UPDATE 0x02000000
313#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
314#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
315#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
316
317#define REG_MDP5_SPLIT_DPL_EN 0x000003f4
318
319#define REG_MDP5_SPLIT_DPL_UPPER 0x000003f8
320#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
321#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
322#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
323#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
324
325#define REG_MDP5_SPLIT_DPL_LOWER 0x000004f0
326#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
327#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
328#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
329#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
330
331static inline uint32_t __offset_CTL(uint32_t idx)
332{
333 switch (idx) {
334 case 0: return (mdp5_cfg->ctl.base[0]);
335 case 1: return (mdp5_cfg->ctl.base[1]);
336 case 2: return (mdp5_cfg->ctl.base[2]);
337 case 3: return (mdp5_cfg->ctl.base[3]);
338 case 4: return (mdp5_cfg->ctl.base[4]);
339 default: return INVALID_IDX(idx);
340 }
341}
342static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
343
344static inline uint32_t __offset_LAYER(uint32_t idx)
345{
346 switch (idx) {
347 case 0: return 0x00000000;
348 case 1: return 0x00000004;
349 case 2: return 0x00000008;
350 case 3: return 0x0000000c;
351 case 4: return 0x00000010;
352 case 5: return 0x00000024;
353 default: return INVALID_IDX(idx);
354 }
355}
356static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
357
358static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
359#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
360#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
361static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
362{
363 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
364}
365#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
366#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
367static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
368{
369 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
370}
371#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
372#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
373static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
374{
375 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
376}
377#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
378#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
379static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
380{
381 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
382}
383#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
384#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
385static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
386{
387 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
388}
389#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
390#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
391static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
392{
393 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
394}
395#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
396#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
397static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
398{
399 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
400}
401#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
402#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
403static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
404{
405 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
406}
407#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
408#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
409#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
410#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
411static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)
412{
413 return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
414}
415#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
416#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
417static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)
418{
419 return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
420}
421
422static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
423#define MDP5_CTL_OP_MODE__MASK 0x0000000f
424#define MDP5_CTL_OP_MODE__SHIFT 0
425static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
426{
427 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
428}
429#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
430#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
431static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
432{
433 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
434}
435#define MDP5_CTL_OP_CMD_MODE 0x00020000
436#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
437#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
438#define MDP5_CTL_OP_PACK_3D__SHIFT 20
439static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
440{
441 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
442}
443
444static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
445#define MDP5_CTL_FLUSH_VIG0 0x00000001
446#define MDP5_CTL_FLUSH_VIG1 0x00000002
447#define MDP5_CTL_FLUSH_VIG2 0x00000004
448#define MDP5_CTL_FLUSH_RGB0 0x00000008
449#define MDP5_CTL_FLUSH_RGB1 0x00000010
450#define MDP5_CTL_FLUSH_RGB2 0x00000020
451#define MDP5_CTL_FLUSH_LM0 0x00000040
452#define MDP5_CTL_FLUSH_LM1 0x00000080
453#define MDP5_CTL_FLUSH_LM2 0x00000100
454#define MDP5_CTL_FLUSH_LM3 0x00000200
455#define MDP5_CTL_FLUSH_LM4 0x00000400
456#define MDP5_CTL_FLUSH_DMA0 0x00000800
457#define MDP5_CTL_FLUSH_DMA1 0x00001000
458#define MDP5_CTL_FLUSH_DSPP0 0x00002000
459#define MDP5_CTL_FLUSH_DSPP1 0x00004000
460#define MDP5_CTL_FLUSH_DSPP2 0x00008000
461#define MDP5_CTL_FLUSH_WB 0x00010000
462#define MDP5_CTL_FLUSH_CTL 0x00020000
463#define MDP5_CTL_FLUSH_VIG3 0x00040000
464#define MDP5_CTL_FLUSH_RGB3 0x00080000
465#define MDP5_CTL_FLUSH_LM5 0x00100000
466#define MDP5_CTL_FLUSH_DSPP3 0x00200000
467#define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
468#define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
469#define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
470#define MDP5_CTL_FLUSH_TIMING_3 0x10000000
471#define MDP5_CTL_FLUSH_TIMING_2 0x20000000
472#define MDP5_CTL_FLUSH_TIMING_1 0x40000000
473#define MDP5_CTL_FLUSH_TIMING_0 0x80000000
474
475static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
476
477static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
478
479static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
480{
481 switch (idx) {
482 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
483 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
484 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
485 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
486 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
487 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
488 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
489 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
490 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
491 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
492 default: return INVALID_IDX(idx);
493 }
494}
495static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
496
497static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
498#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
499#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
500static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
501{
502 return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
503}
504#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
505#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
506static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
507{
508 return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
509}
510#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
511
512static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
513
514static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
515
516static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
517
518static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
519#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
520#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
521static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
522{
523 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
524}
525#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
526#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
527static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
528{
529 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
530}
531
532static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
533#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
534#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
535static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
536{
537 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
538}
539#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
540#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
541static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
542{
543 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
544}
545
546static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
547#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
548#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
549static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
550{
551 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
552}
553#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
554#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
555static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
556{
557 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
558}
559
560static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
561#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
562#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
563static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
564{
565 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
566}
567#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
568#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
569static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
570{
571 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
572}
573
574static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
575#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
576#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
577static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
578{
579 return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
580}
581
582static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
583
584static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
585#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
586#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
587static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
588{
589 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
590}
591#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
592#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
593static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
594{
595 return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
596}
597
598static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
599
600static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
601#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
602#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
603static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
604{
605 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
606}
607#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
608#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
609static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
610{
611 return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
612}
613
614static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
615
616static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
617#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
618#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
619static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
620{
621 return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
622}
623
624static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
625
626static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
627#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
628#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
629static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
630{
631 return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
632}
633
634static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
635#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
636#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
637static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
638{
639 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
640}
641#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
642#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
643static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
644{
645 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
646}
647
648static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
649#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
650#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
651static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
652{
653 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
654}
655#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
656#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
657static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
658{
659 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
660}
661
662static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
663#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
664#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
665static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
666{
667 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
668}
669#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
670#define MDP5_PIPE_SRC_XY_X__SHIFT 0
671static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
672{
673 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
674}
675
676static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
677#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
678#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
679static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
680{
681 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
682}
683#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
684#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
685static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
686{
687 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
688}
689
690static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
691#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
692#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
693static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
694{
695 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
696}
697#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
698#define MDP5_PIPE_OUT_XY_X__SHIFT 0
699static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
700{
701 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
702}
703
704static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
705
706static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
707
708static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
709
710static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
711
712static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
713#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
714#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
715static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
716{
717 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
718}
719#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
720#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
721static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
722{
723 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
724}
725
726static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
727#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
728#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
729static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
730{
731 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
732}
733#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
734#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
735static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
736{
737 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
738}
739
740static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
741
742static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
743#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
744#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
745static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
746{
747 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
748}
749#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
750#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
751static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
752{
753 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
754}
755#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
756#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
757static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
758{
759 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
760}
761#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
762#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
763static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
764{
765 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
766}
767#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
768#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
769#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
770static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
771{
772 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
773}
774#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
775#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
776#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
777static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
778{
779 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
780}
781#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
782#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
783#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00180000
784#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
785static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)
786{
787 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
788}
789#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
790#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
791static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
792{
793 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
794}
795
796static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
797#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
798#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
799static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
800{
801 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
802}
803#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
804#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
805static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
806{
807 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
808}
809#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
810#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
811static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
812{
813 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
814}
815#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
816#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
817static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
818{
819 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
820}
821
822static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
823#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
824#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
825#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
826static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
827{
828 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
829}
830#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
831#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
832#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
833#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
834#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
835#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
836#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
837
838static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
839
840static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
841
842static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
843
844static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
845
846static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
847
848static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
849
850static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
851
852static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
853
854static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
855
856static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
857
858static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
859
860static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
861#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
862#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
863static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
864{
865 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
866}
867#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
868#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
869static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
870{
871 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
872}
873
874static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
875#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
876#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
877#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
878#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
879static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
880{
881 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
882}
883#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
884#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
885static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
886{
887 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
888}
889#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
890#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
891static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
892{
893 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
894}
895#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
896#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
897static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
898{
899 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
900}
901#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
902#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
903static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
904{
905 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
906}
907#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
908#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
909static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
910{
911 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
912}
913
914static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
915
916static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
917
918static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
919
920static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
921
922static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
923
924static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
925
926static inline uint32_t __offset_LM(uint32_t idx)
927{
928 switch (idx) {
929 case 0: return (mdp5_cfg->lm.base[0]);
930 case 1: return (mdp5_cfg->lm.base[1]);
931 case 2: return (mdp5_cfg->lm.base[2]);
932 case 3: return (mdp5_cfg->lm.base[3]);
933 case 4: return (mdp5_cfg->lm.base[4]);
934 case 5: return (mdp5_cfg->lm.base[5]);
935 default: return INVALID_IDX(idx);
936 }
937}
938static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
939
940static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
941#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
942#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
943#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
944#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
945
946static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
947#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
948#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
949static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
950{
951 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
952}
953#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
954#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
955static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
956{
957 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
958}
959
960static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
961
962static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
963
964static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
965
966static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + 0x30*i1; }
967#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
968#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
969static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
970{
971 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
972}
973#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
974#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
975#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
976#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
977#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
978#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
979static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
980{
981 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
982}
983#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
984#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
985#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
986#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
987
988static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + 0x30*i1; }
989
990static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + 0x30*i1; }
991
992static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000002c + __offset_LM(i0) + 0x30*i1; }
993
994static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000030 + __offset_LM(i0) + 0x30*i1; }
995
996static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000034 + __offset_LM(i0) + 0x30*i1; }
997
998static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000038 + __offset_LM(i0) + 0x30*i1; }
999
1000static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000003c + __offset_LM(i0) + 0x30*i1; }
1001
1002static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000040 + __offset_LM(i0) + 0x30*i1; }
1003
1004static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000044 + __offset_LM(i0) + 0x30*i1; }
1005
1006static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000048 + __offset_LM(i0) + 0x30*i1; }
1007
1008static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
1009#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
1010#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
1011static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
1012{
1013 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
1014}
1015#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
1016#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
1017static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
1018{
1019 return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
1020}
1021
1022static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
1023#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
1024#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
1025static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
1026{
1027 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
1028}
1029#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
1030#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
1031static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
1032{
1033 return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
1034}
1035
1036static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
1037#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
1038#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
1039static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
1040{
1041 return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
1042}
1043#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
1044#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
1045static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
1046{
1047 return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
1048}
1049
1050static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
1051#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
1052#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
1053static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
1054{
1055 return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
1056}
1057
1058static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
1059#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
1060#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
1061static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
1062{
1063 return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
1064}
1065
1066static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
1067
1068static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
1069#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
1070#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
1071static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
1072{
1073 return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
1074}
1075#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
1076#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
1077static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
1078{
1079 return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
1080}
1081
1082static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
1083#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
1084#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
1085#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
1086static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
1087{
1088 return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
1089}
1090#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
1091
1092static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
1093
1094static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
1095
1096static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
1097
1098static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
1099
1100static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
1101
1102static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
1103
1104static inline uint32_t __offset_DSPP(uint32_t idx)
1105{
1106 switch (idx) {
1107 case 0: return (mdp5_cfg->dspp.base[0]);
1108 case 1: return (mdp5_cfg->dspp.base[1]);
1109 case 2: return (mdp5_cfg->dspp.base[2]);
1110 case 3: return (mdp5_cfg->dspp.base[3]);
1111 default: return INVALID_IDX(idx);
1112 }
1113}
1114static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1115
1116static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
1117#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
1118#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
1119#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
1120static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
1121{
1122 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
1123}
1124#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
1125#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
1126#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
1127#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
1128#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
1129#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
1130#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
1131#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
1132
1133static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
1134
1135static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
1136
1137static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
1138
1139static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
1140
1141static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
1142
1143static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
1144
1145static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
1146
1147static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
1148
1149static inline uint32_t __offset_PP(uint32_t idx)
1150{
1151 switch (idx) {
1152 case 0: return (mdp5_cfg->pp.base[0]);
1153 case 1: return (mdp5_cfg->pp.base[1]);
1154 case 2: return (mdp5_cfg->pp.base[2]);
1155 case 3: return (mdp5_cfg->pp.base[3]);
1156 default: return INVALID_IDX(idx);
1157 }
1158}
1159static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1160
1161static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
1162
1163static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
1164#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
1165#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
1166static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
1167{
1168 return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
1169}
1170#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
1171#define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
1172
1173static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
1174
1175static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
1176#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
1177#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
1178static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
1179{
1180 return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
1181}
1182#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
1183#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
1184static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
1185{
1186 return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
1187}
1188
1189static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
1190
1191static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
1192#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
1193#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
1194static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
1195{
1196 return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
1197}
1198#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
1199#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
1200static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
1201{
1202 return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
1203}
1204
1205static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
1206#define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
1207#define MDP5_PP_SYNC_THRESH_START__SHIFT 0
1208static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
1209{
1210 return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
1211}
1212#define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
1213#define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
1214static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
1215{
1216 return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
1217}
1218
1219static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
1220
1221static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
1222
1223static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
1224
1225static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
1226
1227static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
1228
1229static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
1230
1231static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
1232
1233static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
1234
1235static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
1236
1237static inline uint32_t __offset_INTF(uint32_t idx)
1238{
1239 switch (idx) {
1240 case 0: return (mdp5_cfg->intf.base[0]);
1241 case 1: return (mdp5_cfg->intf.base[1]);
1242 case 2: return (mdp5_cfg->intf.base[2]);
1243 case 3: return (mdp5_cfg->intf.base[3]);
1244 case 4: return (mdp5_cfg->intf.base[4]);
1245 default: return INVALID_IDX(idx);
1246 }
1247}
1248static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1249
1250static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
1251
1252static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
1253
1254static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
1255#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
1256#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
1257static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
1258{
1259 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
1260}
1261#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
1262#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
1263static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
1264{
1265 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
1266}
1267
1268static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
1269
1270static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
1271
1272static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
1273
1274static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
1275
1276static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
1277
1278static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
1279
1280static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
1281
1282static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
1283
1284static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
1285#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
1286#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
1287static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
1288{
1289 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
1290}
1291#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
1292
1293static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
1294#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
1295#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
1296static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
1297{
1298 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
1299}
1300
1301static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
1302
1303static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
1304
1305static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
1306#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
1307#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
1308static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
1309{
1310 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
1311}
1312#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
1313#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
1314static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
1315{
1316 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
1317}
1318
1319static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
1320#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
1321#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
1322static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
1323{
1324 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
1325}
1326#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
1327#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
1328static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
1329{
1330 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
1331}
1332#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
1333
1334static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
1335
1336static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
1337
1338static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
1339
1340static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
1341#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
1342#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
1343#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
1344
1345static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
1346
1347static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
1348
1349static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
1350
1351static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
1352
1353static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
1354
1355static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
1356
1357static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
1358
1359static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
1360
1361static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
1362
1363static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
1364
1365static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
1366
1367static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
1368
1369static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
1370
1371static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
1372
1373static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
1374
1375static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
1376
1377static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
1378
1379static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
1380
1381static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
1382
1383static inline uint32_t __offset_AD(uint32_t idx)
1384{
1385 switch (idx) {
1386 case 0: return (mdp5_cfg->ad.base[0]);
1387 case 1: return (mdp5_cfg->ad.base[1]);
1388 default: return INVALID_IDX(idx);
1389 }
1390}
1391static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1392
1393static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
1394
1395static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
1396
1397static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
1398
1399static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
1400
1401static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
1402
1403static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
1404
1405static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
1406
1407static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
1408
1409static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
1410
1411static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
1412
1413static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
1414
1415static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
1416
1417static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
1418
1419static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
1420
1421static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
1422
1423static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
1424
1425static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
1426
1427static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
1428
1429static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
1430
1431static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
1432
1433static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
1434
1435static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
1436
1437static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
1438
1439static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
1440
1441static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
1442
1443static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
1444
1445static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
1446
1447static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
1448
1449static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
1450
1451static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
1452
1453static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
1454
1455static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
1456
1457static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
1458
1459static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
1460
1461
1462#endif
1463
