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14#ifndef __MDP5_CTL_H__
15#define __MDP5_CTL_H__
16
17#include "msm_drv.h"
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24struct mdp5_ctl_manager;
25struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
26 void __iomem *mmio_base, const struct mdp5_cfg_hw *hw_cfg);
27void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
28void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
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35struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct drm_crtc *crtc);
36int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
37
38struct mdp5_interface;
39int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf);
40int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
41
42int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
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50static inline u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
51 enum mdp_mixer_stage_id stage)
52{
53 switch (pipe) {
54 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
55 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
56 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
57 case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
58 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
59 case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
60 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
61 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
62 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
63 case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
64 default: return 0;
65 }
66}
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77int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg);
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85u32 mdp_ctl_flush_mask_lm(int lm);
86u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
87u32 mdp_ctl_flush_mask_cursor(int cursor_id);
88u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
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91int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
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93void mdp5_ctl_release(struct mdp5_ctl *ctl);
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97#endif
98