LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c

   1#include "nv20.h"
   2#include "regs.h"
   3
   4#include <engine/fifo.h>
   5
   6/*******************************************************************************
   7 * Graphics object classes
   8 ******************************************************************************/
   9
  10static struct nvkm_oclass
  11nv35_gr_sclass[] = {
  12        { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
  13        { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
  14        { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
  15        { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
  16        { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
  17        { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
  18        { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
  19        { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
  20        { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
  21        { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
  22        { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
  23        { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
  24        { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
  25        { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
  26        { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
  27        { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
  28        { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */
  29        {},
  30};
  31
  32/*******************************************************************************
  33 * PGRAPH context
  34 ******************************************************************************/
  35
  36static int
  37nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  38                     struct nvkm_oclass *oclass, void *data, u32 size,
  39                     struct nvkm_object **pobject)
  40{
  41        struct nv20_gr_chan *chan;
  42        int ret, i;
  43
  44        ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c,
  45                                     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
  46        *pobject = nv_object(chan);
  47        if (ret)
  48                return ret;
  49
  50        chan->chid = nvkm_fifo_chan(parent)->chid;
  51
  52        nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
  53        nv_wo32(chan, 0x040c, 0x00000101);
  54        nv_wo32(chan, 0x0420, 0x00000111);
  55        nv_wo32(chan, 0x0424, 0x00000060);
  56        nv_wo32(chan, 0x0440, 0x00000080);
  57        nv_wo32(chan, 0x0444, 0xffff0000);
  58        nv_wo32(chan, 0x0448, 0x00000001);
  59        nv_wo32(chan, 0x045c, 0x44400000);
  60        nv_wo32(chan, 0x0488, 0xffff0000);
  61        for (i = 0x04dc; i < 0x04e4; i += 4)
  62                nv_wo32(chan, i, 0x0fff0000);
  63        nv_wo32(chan, 0x04e8, 0x00011100);
  64        for (i = 0x0504; i < 0x0544; i += 4)
  65                nv_wo32(chan, i, 0x07ff0000);
  66        nv_wo32(chan, 0x054c, 0x4b7fffff);
  67        nv_wo32(chan, 0x0588, 0x00000080);
  68        nv_wo32(chan, 0x058c, 0x30201000);
  69        nv_wo32(chan, 0x0590, 0x70605040);
  70        nv_wo32(chan, 0x0594, 0xb8a89888);
  71        nv_wo32(chan, 0x0598, 0xf8e8d8c8);
  72        nv_wo32(chan, 0x05ac, 0xb0000000);
  73        for (i = 0x0604; i < 0x0644; i += 4)
  74                nv_wo32(chan, i, 0x00010588);
  75        for (i = 0x0644; i < 0x0684; i += 4)
  76                nv_wo32(chan, i, 0x00030303);
  77        for (i = 0x06c4; i < 0x0704; i += 4)
  78                nv_wo32(chan, i, 0x0008aae4);
  79        for (i = 0x0704; i < 0x0744; i += 4)
  80                nv_wo32(chan, i, 0x01012000);
  81        for (i = 0x0744; i < 0x0784; i += 4)
  82                nv_wo32(chan, i, 0x00080008);
  83        nv_wo32(chan, 0x0860, 0x00040000);
  84        nv_wo32(chan, 0x0864, 0x00010000);
  85        for (i = 0x0868; i < 0x0878; i += 4)
  86                nv_wo32(chan, i, 0x00040004);
  87        for (i = 0x1f1c; i <= 0x308c ; i += 16) {
  88                nv_wo32(chan, i + 0, 0x10700ff9);
  89                nv_wo32(chan, i + 4, 0x0436086c);
  90                nv_wo32(chan, i + 8, 0x000c001b);
  91        }
  92        for (i = 0x30bc; i < 0x30cc; i += 4)
  93                nv_wo32(chan, i, 0x0000ffff);
  94        nv_wo32(chan, 0x3450, 0x3f800000);
  95        nv_wo32(chan, 0x380c, 0x3f800000);
  96        nv_wo32(chan, 0x3820, 0x3f800000);
  97        nv_wo32(chan, 0x384c, 0x40000000);
  98        nv_wo32(chan, 0x3850, 0x3f800000);
  99        nv_wo32(chan, 0x3854, 0x3f000000);
 100        nv_wo32(chan, 0x385c, 0x40000000);
 101        nv_wo32(chan, 0x3860, 0x3f800000);
 102        nv_wo32(chan, 0x3868, 0xbf800000);
 103        nv_wo32(chan, 0x3870, 0xbf800000);
 104        return 0;
 105}
 106
 107static struct nvkm_oclass
 108nv35_gr_cclass = {
 109        .handle = NV_ENGCTX(GR, 0x35),
 110        .ofuncs = &(struct nvkm_ofuncs) {
 111                .ctor = nv35_gr_context_ctor,
 112                .dtor = _nvkm_gr_context_dtor,
 113                .init = nv20_gr_context_init,
 114                .fini = nv20_gr_context_fini,
 115                .rd32 = _nvkm_gr_context_rd32,
 116                .wr32 = _nvkm_gr_context_wr32,
 117        },
 118};
 119
 120/*******************************************************************************
 121 * PGRAPH engine/subdev functions
 122 ******************************************************************************/
 123
 124static int
 125nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 126             struct nvkm_oclass *oclass, void *data, u32 size,
 127             struct nvkm_object **pobject)
 128{
 129        struct nv20_gr_priv *priv;
 130        int ret;
 131
 132        ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
 133        *pobject = nv_object(priv);
 134        if (ret)
 135                return ret;
 136
 137        ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
 138                              NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
 139        if (ret)
 140                return ret;
 141
 142        nv_subdev(priv)->unit = 0x00001000;
 143        nv_subdev(priv)->intr = nv20_gr_intr;
 144        nv_engine(priv)->cclass = &nv35_gr_cclass;
 145        nv_engine(priv)->sclass = nv35_gr_sclass;
 146        nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
 147        return 0;
 148}
 149
 150struct nvkm_oclass
 151nv35_gr_oclass = {
 152        .handle = NV_ENGINE(GR, 0x35),
 153        .ofuncs = &(struct nvkm_ofuncs) {
 154                .ctor = nv35_gr_ctor,
 155                .dtor = nv20_gr_dtor,
 156                .init = nv30_gr_init,
 157                .fini = _nvkm_gr_fini,
 158        },
 159};
 160