LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "gf100.h"
  25
  26static const struct nvkm_specdom
  27gf100_pm_hub[] = {
  28        {}
  29};
  30
  31static const struct nvkm_specdom
  32gf100_pm_gpc[] = {
  33        {}
  34};
  35
  36static const struct nvkm_specdom
  37gf100_pm_part[] = {
  38        {}
  39};
  40
  41static void
  42gf100_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  43                   struct nvkm_perfctr *ctr)
  44{
  45        struct gf100_pm_priv *priv = (void *)ppm;
  46        struct gf100_pm_cntr *cntr = (void *)ctr;
  47        u32 log = ctr->logic_op;
  48        u32 src = 0x00000000;
  49        int i;
  50
  51        for (i = 0; i < 4 && ctr->signal[i]; i++)
  52                src |= (ctr->signal[i] - dom->signal) << (i * 8);
  53
  54        nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
  55        nv_wr32(priv, dom->addr + 0x100, 0x00000000);
  56        nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
  57        nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
  58}
  59
  60static void
  61gf100_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  62                   struct nvkm_perfctr *ctr)
  63{
  64        struct gf100_pm_priv *priv = (void *)ppm;
  65        struct gf100_pm_cntr *cntr = (void *)ctr;
  66
  67        switch (cntr->base.slot) {
  68        case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
  69        case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
  70        case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
  71        case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
  72        }
  73        cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
  74}
  75
  76static void
  77gf100_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
  78{
  79        struct gf100_pm_priv *priv = (void *)ppm;
  80        nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
  81        nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
  82}
  83
  84const struct nvkm_funcdom
  85gf100_perfctr_func = {
  86        .init = gf100_perfctr_init,
  87        .read = gf100_perfctr_read,
  88        .next = gf100_perfctr_next,
  89};
  90
  91int
  92gf100_pm_fini(struct nvkm_object *object, bool suspend)
  93{
  94        struct gf100_pm_priv *priv = (void *)object;
  95        nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
  96        nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
  97        return nvkm_pm_fini(&priv->base, suspend);
  98}
  99
 100static int
 101gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 102              struct nvkm_oclass *oclass, void *data, u32 size,
 103              struct nvkm_object **pobject)
 104{
 105        struct gf100_pm_priv *priv;
 106        u32 mask;
 107        int ret;
 108
 109        ret = nvkm_pm_create(parent, engine, oclass, &priv);
 110        *pobject = nv_object(priv);
 111        if (ret)
 112                return ret;
 113
 114        ret = nvkm_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, gf100_pm_pwr);
 115        if (ret)
 116                return ret;
 117
 118        /* HUB */
 119        ret = nvkm_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
 120                               gf100_pm_hub);
 121        if (ret)
 122                return ret;
 123
 124        /* GPC */
 125        mask  = (1 << nv_rd32(priv, 0x022430)) - 1;
 126        mask &= ~nv_rd32(priv, 0x022504);
 127        mask &= ~nv_rd32(priv, 0x022584);
 128
 129        ret = nvkm_perfdom_new(&priv->base, "gpc", mask, 0x180000,
 130                               0x1000, 0x200, gf100_pm_gpc);
 131        if (ret)
 132                return ret;
 133
 134        /* PART */
 135        mask  = (1 << nv_rd32(priv, 0x022438)) - 1;
 136        mask &= ~nv_rd32(priv, 0x022548);
 137        mask &= ~nv_rd32(priv, 0x0225c8);
 138
 139        ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000,
 140                               0x1000, 0x200, gf100_pm_part);
 141        if (ret)
 142                return ret;
 143
 144        nv_engine(priv)->cclass = &nvkm_pm_cclass;
 145        nv_engine(priv)->sclass =  nvkm_pm_sclass;
 146        priv->base.last = 7;
 147        return 0;
 148}
 149
 150struct nvkm_oclass
 151gf100_pm_oclass = {
 152        .handle = NV_ENGINE(PM, 0xc0),
 153        .ofuncs = &(struct nvkm_ofuncs) {
 154                .ctor = gf100_pm_ctor,
 155                .dtor = _nvkm_pm_dtor,
 156                .init = _nvkm_pm_init,
 157                .fini = gf100_pm_fini,
 158        },
 159};
 160