LXR linux/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c

   1/*
   2 * Copyright 2014 Martin Peres
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Martin Peres
  23 */
  24#include "priv.h"
  25
  26struct gf100_fuse_priv {
  27        struct nvkm_fuse base;
  28
  29        spinlock_t fuse_enable_lock;
  30};
  31
  32static u32
  33gf100_fuse_rd32(struct nvkm_object *object, u64 addr)
  34{
  35        struct gf100_fuse_priv *priv = (void *)object;
  36        unsigned long flags;
  37        u32 fuse_enable, unk, val;
  38
  39        /* racy if another part of nvkm start writing to these regs */
  40        spin_lock_irqsave(&priv->fuse_enable_lock, flags);
  41        fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800);
  42        unk = nv_mask(priv, 0x21000, 0x1, 0x1);
  43        val = nv_rd32(priv, 0x21100 + addr);
  44        nv_wr32(priv, 0x21000, unk);
  45        nv_wr32(priv, 0x22400, fuse_enable);
  46        spin_unlock_irqrestore(&priv->fuse_enable_lock, flags);
  47        return val;
  48}
  49
  50
  51static int
  52gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  53                struct nvkm_oclass *oclass, void *data, u32 size,
  54                struct nvkm_object **pobject)
  55{
  56        struct gf100_fuse_priv *priv;
  57        int ret;
  58
  59        ret = nvkm_fuse_create(parent, engine, oclass, &priv);
  60        *pobject = nv_object(priv);
  61        if (ret)
  62                return ret;
  63
  64        spin_lock_init(&priv->fuse_enable_lock);
  65        return 0;
  66}
  67
  68struct nvkm_oclass
  69gf100_fuse_oclass = {
  70        .handle = NV_SUBDEV(FUSE, 0xC0),
  71        .ofuncs = &(struct nvkm_ofuncs) {
  72                .ctor = gf100_fuse_ctor,
  73                .dtor = _nvkm_fuse_dtor,
  74                .init = _nvkm_fuse_init,
  75                .fini = _nvkm_fuse_fini,
  76                .rd32 = gf100_fuse_rd32,
  77        },
  78};
  79