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21
22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
24#include <linux/kernel.h>
25#include <linux/mm.h>
26#include <linux/slab.h>
27#include <linux/vmalloc.h>
28#include <linux/hyperv.h>
29#include <linux/version.h>
30#include <linux/interrupt.h>
31#include <linux/clockchips.h>
32#include <asm/hyperv.h>
33#include <asm/mshyperv.h>
34#include "hyperv_vmbus.h"
35
36
37struct hv_context hv_context = {
38 .synic_initialized = false,
39 .hypercall_page = NULL,
40};
41
42#define HV_TIMER_FREQUENCY (10 * 1000 * 1000)
43#define HV_MAX_MAX_DELTA_TICKS 0xffffffff
44#define HV_MIN_DELTA_TICKS 1
45
46
47
48
49unsigned int host_info_eax;
50unsigned int host_info_ebx;
51unsigned int host_info_ecx;
52unsigned int host_info_edx;
53
54static int query_hypervisor_info(void)
55{
56 unsigned int eax;
57 unsigned int ebx;
58 unsigned int ecx;
59 unsigned int edx;
60 unsigned int max_leaf;
61 unsigned int op;
62
63
64
65
66
67 eax = 0;
68 ebx = 0;
69 ecx = 0;
70 edx = 0;
71 op = HVCPUID_VENDOR_MAXFUNCTION;
72 cpuid(op, &eax, &ebx, &ecx, &edx);
73
74 max_leaf = eax;
75
76 if (max_leaf >= HVCPUID_VERSION) {
77 eax = 0;
78 ebx = 0;
79 ecx = 0;
80 edx = 0;
81 op = HVCPUID_VERSION;
82 cpuid(op, &eax, &ebx, &ecx, &edx);
83 host_info_eax = eax;
84 host_info_ebx = ebx;
85 host_info_ecx = ecx;
86 host_info_edx = edx;
87 }
88 return max_leaf;
89}
90
91
92
93
94static u64 do_hypercall(u64 control, void *input, void *output)
95{
96#ifdef CONFIG_X86_64
97 u64 hv_status = 0;
98 u64 input_address = (input) ? virt_to_phys(input) : 0;
99 u64 output_address = (output) ? virt_to_phys(output) : 0;
100 void *hypercall_page = hv_context.hypercall_page;
101
102 __asm__ __volatile__("mov %0, %%r8" : : "r" (output_address) : "r8");
103 __asm__ __volatile__("call *%3" : "=a" (hv_status) :
104 "c" (control), "d" (input_address),
105 "m" (hypercall_page));
106
107 return hv_status;
108
109#else
110
111 u32 control_hi = control >> 32;
112 u32 control_lo = control & 0xFFFFFFFF;
113 u32 hv_status_hi = 1;
114 u32 hv_status_lo = 1;
115 u64 input_address = (input) ? virt_to_phys(input) : 0;
116 u32 input_address_hi = input_address >> 32;
117 u32 input_address_lo = input_address & 0xFFFFFFFF;
118 u64 output_address = (output) ? virt_to_phys(output) : 0;
119 u32 output_address_hi = output_address >> 32;
120 u32 output_address_lo = output_address & 0xFFFFFFFF;
121 void *hypercall_page = hv_context.hypercall_page;
122
123 __asm__ __volatile__ ("call *%8" : "=d"(hv_status_hi),
124 "=a"(hv_status_lo) : "d" (control_hi),
125 "a" (control_lo), "b" (input_address_hi),
126 "c" (input_address_lo), "D"(output_address_hi),
127 "S"(output_address_lo), "m" (hypercall_page));
128
129 return hv_status_lo | ((u64)hv_status_hi << 32);
130#endif
131}
132
133
134
135
136
137
138int hv_init(void)
139{
140 int max_leaf;
141 union hv_x64_msr_hypercall_contents hypercall_msr;
142 void *virtaddr = NULL;
143
144 memset(hv_context.synic_event_page, 0, sizeof(void *) * NR_CPUS);
145 memset(hv_context.synic_message_page, 0,
146 sizeof(void *) * NR_CPUS);
147 memset(hv_context.post_msg_page, 0,
148 sizeof(void *) * NR_CPUS);
149 memset(hv_context.vp_index, 0,
150 sizeof(int) * NR_CPUS);
151 memset(hv_context.event_dpc, 0,
152 sizeof(void *) * NR_CPUS);
153 memset(hv_context.clk_evt, 0,
154 sizeof(void *) * NR_CPUS);
155
156 max_leaf = query_hypervisor_info();
157
158
159
160
161 hv_context.guestid = generate_guest_id(0, LINUX_VERSION_CODE, 0);
162 wrmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid);
163
164
165 rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
166
167 virtaddr = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL_EXEC);
168
169 if (!virtaddr)
170 goto cleanup;
171
172 hypercall_msr.enable = 1;
173
174 hypercall_msr.guest_physical_address = vmalloc_to_pfn(virtaddr);
175 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
176
177
178 hypercall_msr.as_uint64 = 0;
179 rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
180
181 if (!hypercall_msr.enable)
182 goto cleanup;
183
184 hv_context.hypercall_page = virtaddr;
185
186 return 0;
187
188cleanup:
189 if (virtaddr) {
190 if (hypercall_msr.enable) {
191 hypercall_msr.as_uint64 = 0;
192 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
193 }
194
195 vfree(virtaddr);
196 }
197
198 return -ENOTSUPP;
199}
200
201
202
203
204
205
206void hv_cleanup(void)
207{
208 union hv_x64_msr_hypercall_contents hypercall_msr;
209
210
211 wrmsrl(HV_X64_MSR_GUEST_OS_ID, 0);
212
213 if (hv_context.hypercall_page) {
214 hypercall_msr.as_uint64 = 0;
215 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
216 vfree(hv_context.hypercall_page);
217 hv_context.hypercall_page = NULL;
218 }
219}
220
221
222
223
224
225
226int hv_post_message(union hv_connection_id connection_id,
227 enum hv_message_type message_type,
228 void *payload, size_t payload_size)
229{
230
231 struct hv_input_post_message *aligned_msg;
232 u16 status;
233
234 if (payload_size > HV_MESSAGE_PAYLOAD_BYTE_COUNT)
235 return -EMSGSIZE;
236
237 aligned_msg = (struct hv_input_post_message *)
238 hv_context.post_msg_page[get_cpu()];
239
240 aligned_msg->connectionid = connection_id;
241 aligned_msg->reserved = 0;
242 aligned_msg->message_type = message_type;
243 aligned_msg->payload_size = payload_size;
244 memcpy((void *)aligned_msg->payload, payload, payload_size);
245
246 status = do_hypercall(HVCALL_POST_MESSAGE, aligned_msg, NULL)
247 & 0xFFFF;
248
249 put_cpu();
250 return status;
251}
252
253
254
255
256
257
258
259
260u16 hv_signal_event(void *con_id)
261{
262 u16 status;
263
264 status = (do_hypercall(HVCALL_SIGNAL_EVENT, con_id, NULL) & 0xFFFF);
265
266 return status;
267}
268
269static int hv_ce_set_next_event(unsigned long delta,
270 struct clock_event_device *evt)
271{
272 cycle_t current_tick;
273
274 WARN_ON(evt->mode != CLOCK_EVT_MODE_ONESHOT);
275
276 rdmsrl(HV_X64_MSR_TIME_REF_COUNT, current_tick);
277 current_tick += delta;
278 wrmsrl(HV_X64_MSR_STIMER0_COUNT, current_tick);
279 return 0;
280}
281
282static void hv_ce_setmode(enum clock_event_mode mode,
283 struct clock_event_device *evt)
284{
285 union hv_timer_config timer_cfg;
286
287 switch (mode) {
288 case CLOCK_EVT_MODE_PERIODIC:
289
290 break;
291
292 case CLOCK_EVT_MODE_ONESHOT:
293 timer_cfg.enable = 1;
294 timer_cfg.auto_enable = 1;
295 timer_cfg.sintx = VMBUS_MESSAGE_SINT;
296 wrmsrl(HV_X64_MSR_STIMER0_CONFIG, timer_cfg.as_uint64);
297 break;
298
299 case CLOCK_EVT_MODE_UNUSED:
300 case CLOCK_EVT_MODE_SHUTDOWN:
301 wrmsrl(HV_X64_MSR_STIMER0_COUNT, 0);
302 wrmsrl(HV_X64_MSR_STIMER0_CONFIG, 0);
303 break;
304 case CLOCK_EVT_MODE_RESUME:
305 break;
306 }
307}
308
309static void hv_init_clockevent_device(struct clock_event_device *dev, int cpu)
310{
311 dev->name = "Hyper-V clockevent";
312 dev->features = CLOCK_EVT_FEAT_ONESHOT;
313 dev->cpumask = cpumask_of(cpu);
314 dev->rating = 1000;
315
316
317
318
319
320
321 dev->set_mode = hv_ce_setmode;
322 dev->set_next_event = hv_ce_set_next_event;
323}
324
325
326int hv_synic_alloc(void)
327{
328 size_t size = sizeof(struct tasklet_struct);
329 size_t ced_size = sizeof(struct clock_event_device);
330 int cpu;
331
332 for_each_online_cpu(cpu) {
333 hv_context.event_dpc[cpu] = kmalloc(size, GFP_ATOMIC);
334 if (hv_context.event_dpc[cpu] == NULL) {
335 pr_err("Unable to allocate event dpc\n");
336 goto err;
337 }
338 tasklet_init(hv_context.event_dpc[cpu], vmbus_on_event, cpu);
339
340 hv_context.clk_evt[cpu] = kzalloc(ced_size, GFP_ATOMIC);
341 if (hv_context.clk_evt[cpu] == NULL) {
342 pr_err("Unable to allocate clock event device\n");
343 goto err;
344 }
345 hv_init_clockevent_device(hv_context.clk_evt[cpu], cpu);
346
347 hv_context.synic_message_page[cpu] =
348 (void *)get_zeroed_page(GFP_ATOMIC);
349
350 if (hv_context.synic_message_page[cpu] == NULL) {
351 pr_err("Unable to allocate SYNIC message page\n");
352 goto err;
353 }
354
355 hv_context.synic_event_page[cpu] =
356 (void *)get_zeroed_page(GFP_ATOMIC);
357
358 if (hv_context.synic_event_page[cpu] == NULL) {
359 pr_err("Unable to allocate SYNIC event page\n");
360 goto err;
361 }
362
363 hv_context.post_msg_page[cpu] =
364 (void *)get_zeroed_page(GFP_ATOMIC);
365
366 if (hv_context.post_msg_page[cpu] == NULL) {
367 pr_err("Unable to allocate post msg page\n");
368 goto err;
369 }
370 }
371
372 return 0;
373err:
374 return -ENOMEM;
375}
376
377static void hv_synic_free_cpu(int cpu)
378{
379 kfree(hv_context.event_dpc[cpu]);
380 kfree(hv_context.clk_evt[cpu]);
381 if (hv_context.synic_event_page[cpu])
382 free_page((unsigned long)hv_context.synic_event_page[cpu]);
383 if (hv_context.synic_message_page[cpu])
384 free_page((unsigned long)hv_context.synic_message_page[cpu]);
385 if (hv_context.post_msg_page[cpu])
386 free_page((unsigned long)hv_context.post_msg_page[cpu]);
387}
388
389void hv_synic_free(void)
390{
391 int cpu;
392
393 for_each_online_cpu(cpu)
394 hv_synic_free_cpu(cpu);
395}
396
397
398
399
400
401
402
403
404void hv_synic_init(void *arg)
405{
406 u64 version;
407 union hv_synic_simp simp;
408 union hv_synic_siefp siefp;
409 union hv_synic_sint shared_sint;
410 union hv_synic_scontrol sctrl;
411 u64 vp_index;
412
413 int cpu = smp_processor_id();
414
415 if (!hv_context.hypercall_page)
416 return;
417
418
419 rdmsrl(HV_X64_MSR_SVERSION, version);
420
421
422 rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64);
423 simp.simp_enabled = 1;
424 simp.base_simp_gpa = virt_to_phys(hv_context.synic_message_page[cpu])
425 >> PAGE_SHIFT;
426
427 wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64);
428
429
430 rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64);
431 siefp.siefp_enabled = 1;
432 siefp.base_siefp_gpa = virt_to_phys(hv_context.synic_event_page[cpu])
433 >> PAGE_SHIFT;
434
435 wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64);
436
437
438 rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
439
440 shared_sint.as_uint64 = 0;
441 shared_sint.vector = HYPERVISOR_CALLBACK_VECTOR;
442 shared_sint.masked = false;
443 shared_sint.auto_eoi = true;
444
445 wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
446
447
448 rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64);
449 sctrl.enable = 1;
450
451 wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64);
452
453 hv_context.synic_initialized = true;
454
455
456
457
458
459
460 rdmsrl(HV_X64_MSR_VP_INDEX, vp_index);
461 hv_context.vp_index[cpu] = (u32)vp_index;
462
463 INIT_LIST_HEAD(&hv_context.percpu_list[cpu]);
464
465
466
467
468 if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE)
469 clockevents_config_and_register(hv_context.clk_evt[cpu],
470 HV_TIMER_FREQUENCY,
471 HV_MIN_DELTA_TICKS,
472 HV_MAX_MAX_DELTA_TICKS);
473 return;
474}
475
476
477
478
479void hv_synic_clockevents_cleanup(void)
480{
481 int cpu;
482
483 if (!(ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE))
484 return;
485
486 for_each_online_cpu(cpu)
487 clockevents_unbind_device(hv_context.clk_evt[cpu], cpu);
488}
489
490
491
492
493void hv_synic_cleanup(void *arg)
494{
495 union hv_synic_sint shared_sint;
496 union hv_synic_simp simp;
497 union hv_synic_siefp siefp;
498 union hv_synic_scontrol sctrl;
499 int cpu = smp_processor_id();
500
501 if (!hv_context.synic_initialized)
502 return;
503
504
505 if (ms_hyperv.features & HV_X64_MSR_SYNTIMER_AVAILABLE)
506 hv_ce_setmode(CLOCK_EVT_MODE_SHUTDOWN,
507 hv_context.clk_evt[cpu]);
508
509 rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
510
511 shared_sint.masked = 1;
512
513
514
515 wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
516
517 rdmsrl(HV_X64_MSR_SIMP, simp.as_uint64);
518 simp.simp_enabled = 0;
519 simp.base_simp_gpa = 0;
520
521 wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64);
522
523 rdmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64);
524 siefp.siefp_enabled = 0;
525 siefp.base_siefp_gpa = 0;
526
527 wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64);
528
529
530 rdmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64);
531 sctrl.enable = 0;
532 wrmsrl(HV_X64_MSR_SCONTROL, sctrl.as_uint64);
533
534 hv_synic_free_cpu(cpu);
535}
536