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18#include <linux/slab.h>
19#include <linux/device.h>
20#include <linux/module.h>
21#include <linux/i2c.h>
22#include <linux/err.h>
23#include <linux/interrupt.h>
24#include <linux/completion.h>
25#include <linux/platform_device.h>
26#include <linux/jiffies.h>
27#include <linux/io.h>
28#include <linux/stmp_device.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/dma-mapping.h>
32#include <linux/dmaengine.h>
33
34#define DRIVER_NAME "mxs-i2c"
35
36#define MXS_I2C_CTRL0 (0x00)
37#define MXS_I2C_CTRL0_SET (0x04)
38#define MXS_I2C_CTRL0_CLR (0x08)
39
40#define MXS_I2C_CTRL0_SFTRST 0x80000000
41#define MXS_I2C_CTRL0_RUN 0x20000000
42#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
43#define MXS_I2C_CTRL0_PIO_MODE 0x01000000
44#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
45#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
46#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
47#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
48#define MXS_I2C_CTRL0_DIRECTION 0x00010000
49#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
50
51#define MXS_I2C_TIMING0 (0x10)
52#define MXS_I2C_TIMING1 (0x20)
53#define MXS_I2C_TIMING2 (0x30)
54
55#define MXS_I2C_CTRL1 (0x40)
56#define MXS_I2C_CTRL1_SET (0x44)
57#define MXS_I2C_CTRL1_CLR (0x48)
58
59#define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
60#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
61#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
62#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
63#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
64#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
65#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
66#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
67#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
68
69#define MXS_I2C_STAT (0x50)
70#define MXS_I2C_STAT_GOT_A_NAK 0x10000000
71#define MXS_I2C_STAT_BUS_BUSY 0x00000800
72#define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
73
74#define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
75
76#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
77
78#define MXS_I2C_DEBUG0_DMAREQ 0x80000000
79
80#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
81 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
82 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
83 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
84 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
85 MXS_I2C_CTRL1_SLAVE_IRQ)
86
87
88#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
89 MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION | \
92 MXS_I2C_CTRL0_XFER_COUNT(1))
93
94#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
95 MXS_I2C_CTRL0_MASTER_MODE | \
96 MXS_I2C_CTRL0_DIRECTION)
97
98#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
99 MXS_I2C_CTRL0_MASTER_MODE)
100
101enum mxs_i2c_devtype {
102 MXS_I2C_UNKNOWN = 0,
103 MXS_I2C_V1,
104 MXS_I2C_V2,
105};
106
107
108
109
110
111
112
113
114
115
116
117struct mxs_i2c_dev {
118 struct device *dev;
119 enum mxs_i2c_devtype dev_type;
120 void __iomem *regs;
121 struct completion cmd_complete;
122 int cmd_err;
123 struct i2c_adapter adapter;
124
125 uint32_t timing0;
126 uint32_t timing1;
127 uint32_t timing2;
128
129
130 struct dma_chan *dmach;
131 uint32_t pio_data[2];
132 uint32_t addr_data;
133 struct scatterlist sg_io[2];
134 bool dma_read;
135};
136
137static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
138{
139 int ret = stmp_reset_block(i2c->regs);
140 if (ret)
141 return ret;
142
143
144
145
146
147
148
149
150 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
151 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
152 writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
153
154 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
155
156 return 0;
157}
158
159static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
160{
161 if (i2c->dma_read) {
162 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
163 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
164 } else {
165 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
166 }
167}
168
169static void mxs_i2c_dma_irq_callback(void *param)
170{
171 struct mxs_i2c_dev *i2c = param;
172
173 complete(&i2c->cmd_complete);
174 mxs_i2c_dma_finish(i2c);
175}
176
177static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
178 struct i2c_msg *msg, uint32_t flags)
179{
180 struct dma_async_tx_descriptor *desc;
181 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
182
183 if (msg->flags & I2C_M_RD) {
184 i2c->dma_read = 1;
185 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ;
186
187
188
189
190
191
192 i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
193 desc = dmaengine_prep_slave_sg(i2c->dmach,
194 (struct scatterlist *)&i2c->pio_data[0],
195 1, DMA_TRANS_NONE, 0);
196 if (!desc) {
197 dev_err(i2c->dev,
198 "Failed to get PIO reg. write descriptor.\n");
199 goto select_init_pio_fail;
200 }
201
202
203 sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
204 dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
205 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
206 DMA_MEM_TO_DEV,
207 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
208 if (!desc) {
209 dev_err(i2c->dev,
210 "Failed to get DMA data write descriptor.\n");
211 goto select_init_dma_fail;
212 }
213
214
215
216
217
218
219 i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
220 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
221 desc = dmaengine_prep_slave_sg(i2c->dmach,
222 (struct scatterlist *)&i2c->pio_data[1],
223 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
224 if (!desc) {
225 dev_err(i2c->dev,
226 "Failed to get PIO reg. write descriptor.\n");
227 goto select_init_dma_fail;
228 }
229
230
231 sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
232 dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
233 desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
234 DMA_DEV_TO_MEM,
235 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
236 if (!desc) {
237 dev_err(i2c->dev,
238 "Failed to get DMA data write descriptor.\n");
239 goto read_init_dma_fail;
240 }
241 } else {
242 i2c->dma_read = 0;
243 i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE;
244
245
246
247
248
249
250 i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
251 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
252 desc = dmaengine_prep_slave_sg(i2c->dmach,
253 (struct scatterlist *)&i2c->pio_data[0],
254 1, DMA_TRANS_NONE, 0);
255 if (!desc) {
256 dev_err(i2c->dev,
257 "Failed to get PIO reg. write descriptor.\n");
258 goto write_init_pio_fail;
259 }
260
261
262 sg_init_table(i2c->sg_io, 2);
263 sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
264 sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
265 dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
266 desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
267 DMA_MEM_TO_DEV,
268 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
269 if (!desc) {
270 dev_err(i2c->dev,
271 "Failed to get DMA data write descriptor.\n");
272 goto write_init_dma_fail;
273 }
274 }
275
276
277
278
279
280 desc->callback = mxs_i2c_dma_irq_callback;
281 desc->callback_param = i2c;
282
283
284 dmaengine_submit(desc);
285 dma_async_issue_pending(i2c->dmach);
286 return 0;
287
288
289read_init_dma_fail:
290 dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
291select_init_dma_fail:
292 dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
293select_init_pio_fail:
294 dmaengine_terminate_all(i2c->dmach);
295 return -EINVAL;
296
297
298write_init_dma_fail:
299 dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
300write_init_pio_fail:
301 dmaengine_terminate_all(i2c->dmach);
302 return -EINVAL;
303}
304
305static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
306{
307 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
308
309 while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
310 if (readl(i2c->regs + MXS_I2C_CTRL1) &
311 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
312 return -ENXIO;
313 if (time_after(jiffies, timeout))
314 return -ETIMEDOUT;
315 cond_resched();
316 }
317
318 return 0;
319}
320
321static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
322{
323 u32 state;
324
325 state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
326
327 if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
328 i2c->cmd_err = -ENXIO;
329 else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
330 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
331 MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
332 MXS_I2C_CTRL1_SLAVE_IRQ))
333 i2c->cmd_err = -EIO;
334
335 return i2c->cmd_err;
336}
337
338static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
339{
340 u32 reg;
341
342 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
343
344
345 reg = readl(i2c->regs + MXS_I2C_CTRL0);
346 reg |= MXS_I2C_CTRL0_RUN;
347 writel(reg, i2c->regs + MXS_I2C_CTRL0);
348}
349
350
351
352
353
354
355
356
357
358static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
359 u32 data)
360{
361 writel(cmd, i2c->regs + MXS_I2C_CTRL0);
362
363 if (i2c->dev_type == MXS_I2C_V1)
364 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
365
366 writel(data, i2c->regs + MXS_I2C_DATA(i2c));
367 writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
368}
369
370static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
371 struct i2c_msg *msg, uint32_t flags)
372{
373 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
374 uint32_t addr_data = msg->addr << 1;
375 uint32_t data = 0;
376 int i, ret, xlen = 0, xmit = 0;
377 uint32_t start;
378
379
380 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399 if (msg->flags & I2C_M_RD) {
400
401
402
403
404
405
406
407
408
409
410
411
412 BUG_ON(msg->len > 4);
413
414 addr_data |= I2C_SMBUS_READ;
415
416
417 mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
418 addr_data);
419
420 ret = mxs_i2c_pio_wait_xfer_end(i2c);
421 if (ret) {
422 dev_err(i2c->dev,
423 "PIO: Failed to send SELECT command!\n");
424 goto cleanup;
425 }
426
427
428 mxs_i2c_pio_trigger_cmd(i2c,
429 MXS_CMD_I2C_READ | flags |
430 MXS_I2C_CTRL0_XFER_COUNT(msg->len));
431
432 ret = mxs_i2c_pio_wait_xfer_end(i2c);
433 if (ret) {
434 dev_err(i2c->dev,
435 "PIO: Failed to send READ command!\n");
436 goto cleanup;
437 }
438
439 data = readl(i2c->regs + MXS_I2C_DATA(i2c));
440 for (i = 0; i < msg->len; i++) {
441 msg->buf[i] = data & 0xff;
442 data >>= 8;
443 }
444 } else {
445
446
447
448
449
450
451
452
453 addr_data |= I2C_SMBUS_WRITE;
454
455
456
457
458
459
460
461 data = addr_data << 24;
462
463
464 start = MXS_I2C_CTRL0_PRE_SEND_START;
465
466
467 if (msg->len > 3)
468 start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
469
470 for (i = 0; i < msg->len; i++) {
471 data >>= 8;
472 data |= (msg->buf[i] << 24);
473
474 xmit = 0;
475
476
477 if (i + 1 == msg->len) {
478
479 start |= flags;
480
481 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
482 xmit = 1;
483 }
484
485
486 if ((i & 3) == 2)
487 xmit = 1;
488
489
490 if (!xmit)
491 continue;
492
493
494
495
496
497
498
499
500
501
502
503 if ((i % 4) == 3)
504 xlen = 1;
505 else
506 xlen = (i % 4) + 2;
507
508 data >>= (4 - xlen) * 8;
509
510 dev_dbg(i2c->dev,
511 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
512 xlen, i, msg->len,
513 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
514 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
515 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
516
517 writel(MXS_I2C_DEBUG0_DMAREQ,
518 i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
519
520 mxs_i2c_pio_trigger_write_cmd(i2c,
521 start | MXS_I2C_CTRL0_MASTER_MODE |
522 MXS_I2C_CTRL0_DIRECTION |
523 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
524
525
526 start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
527
528
529 ret = mxs_i2c_pio_wait_xfer_end(i2c);
530 if (ret) {
531 dev_err(i2c->dev,
532 "PIO: Failed to finish WRITE cmd!\n");
533 break;
534 }
535
536
537 ret = readl(i2c->regs + MXS_I2C_STAT) &
538 MXS_I2C_STAT_GOT_A_NAK;
539 if (ret) {
540 ret = -ENXIO;
541 goto cleanup;
542 }
543 }
544 }
545
546
547 ret = mxs_i2c_pio_check_error_state(i2c);
548
549cleanup:
550
551 writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
552 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
553
554
555 if (i2c->dev_type == MXS_I2C_V1)
556 writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
557
558 return ret;
559}
560
561
562
563
564static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
565 int stop)
566{
567 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
568 int ret;
569 int flags;
570 int use_pio = 0;
571 unsigned long time_left;
572
573 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
574
575 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
576 msg->addr, msg->len, msg->flags, stop);
577
578 if (msg->len == 0)
579 return -EINVAL;
580
581
582
583
584
585
586 if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
587 use_pio = 1;
588 if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
589 use_pio = 1;
590
591 i2c->cmd_err = 0;
592 if (use_pio) {
593 ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
594
595 if (ret && (ret != -ENXIO))
596 mxs_i2c_reset(i2c);
597 } else {
598 reinit_completion(&i2c->cmd_complete);
599 ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
600 if (ret)
601 return ret;
602
603 time_left = wait_for_completion_timeout(&i2c->cmd_complete,
604 msecs_to_jiffies(1000));
605 if (!time_left)
606 goto timeout;
607
608 ret = i2c->cmd_err;
609 }
610
611 if (ret == -ENXIO) {
612
613
614
615
616 writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
617 i2c->regs + MXS_I2C_CTRL1_SET);
618 }
619
620
621
622
623
624
625
626
627
628
629
630
631 if (i2c->dev_type == MXS_I2C_V1)
632 mxs_i2c_reset(i2c);
633
634 dev_dbg(i2c->dev, "Done with err=%d\n", ret);
635
636 return ret;
637
638timeout:
639 dev_dbg(i2c->dev, "Timeout!\n");
640 mxs_i2c_dma_finish(i2c);
641 ret = mxs_i2c_reset(i2c);
642 if (ret)
643 return ret;
644
645 return -ETIMEDOUT;
646}
647
648static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
649 int num)
650{
651 int i;
652 int err;
653
654 for (i = 0; i < num; i++) {
655 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
656 if (err)
657 return err;
658 }
659
660 return num;
661}
662
663static u32 mxs_i2c_func(struct i2c_adapter *adap)
664{
665 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
666}
667
668static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
669{
670 struct mxs_i2c_dev *i2c = dev_id;
671 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
672
673 if (!stat)
674 return IRQ_NONE;
675
676 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
677 i2c->cmd_err = -ENXIO;
678 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
679 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
680 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
681
682 i2c->cmd_err = -EIO;
683
684 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
685
686 return IRQ_HANDLED;
687}
688
689static const struct i2c_algorithm mxs_i2c_algo = {
690 .master_xfer = mxs_i2c_xfer,
691 .functionality = mxs_i2c_func,
692};
693
694static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
695{
696
697 const uint32_t clk = 24000000;
698 uint32_t divider;
699 uint16_t high_count, low_count, rcv_count, xmit_count;
700 uint32_t bus_free, leadin;
701 struct device *dev = i2c->dev;
702
703 divider = DIV_ROUND_UP(clk, speed);
704
705 if (divider < 25) {
706
707
708
709
710 divider = 25;
711 dev_warn(dev,
712 "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
713 speed / 1000, speed % 1000,
714 clk / divider / 1000, clk / divider % 1000);
715 } else if (divider > 1897) {
716
717
718
719
720 divider = 1897;
721 dev_warn(dev,
722 "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
723 speed / 1000, speed % 1000,
724 clk / divider / 1000, clk / divider % 1000);
725 }
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741 if (speed > 100000) {
742
743 low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
744 high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
745 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
746 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
747 } else {
748
749 low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
750 high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
751 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
752 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
753 }
754 rcv_count = high_count * 3 / 8;
755 xmit_count = low_count * 3 / 8;
756
757 dev_dbg(dev,
758 "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
759 speed, clk / divider, divider, low_count, high_count,
760 xmit_count, rcv_count, leadin, bus_free);
761
762 low_count -= 2;
763 high_count -= 7;
764 i2c->timing0 = (high_count << 16) | rcv_count;
765 i2c->timing1 = (low_count << 16) | xmit_count;
766 i2c->timing2 = (bus_free << 16 | leadin);
767}
768
769static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
770{
771 uint32_t speed;
772 struct device *dev = i2c->dev;
773 struct device_node *node = dev->of_node;
774 int ret;
775
776 ret = of_property_read_u32(node, "clock-frequency", &speed);
777 if (ret) {
778 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
779 speed = 100000;
780 }
781
782 mxs_i2c_derive_timing(i2c, speed);
783
784 return 0;
785}
786
787static struct platform_device_id mxs_i2c_devtype[] = {
788 {
789 .name = "imx23-i2c",
790 .driver_data = MXS_I2C_V1,
791 }, {
792 .name = "imx28-i2c",
793 .driver_data = MXS_I2C_V2,
794 }, { }
795};
796MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
797
798static const struct of_device_id mxs_i2c_dt_ids[] = {
799 { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
800 { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
801 { }
802};
803MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
804
805static int mxs_i2c_probe(struct platform_device *pdev)
806{
807 const struct of_device_id *of_id =
808 of_match_device(mxs_i2c_dt_ids, &pdev->dev);
809 struct device *dev = &pdev->dev;
810 struct mxs_i2c_dev *i2c;
811 struct i2c_adapter *adap;
812 struct resource *res;
813 int err, irq;
814
815 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
816 if (!i2c)
817 return -ENOMEM;
818
819 if (of_id) {
820 const struct platform_device_id *device_id = of_id->data;
821 i2c->dev_type = device_id->driver_data;
822 }
823
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
826 if (IS_ERR(i2c->regs))
827 return PTR_ERR(i2c->regs);
828
829 irq = platform_get_irq(pdev, 0);
830 if (irq < 0)
831 return irq;
832
833 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
834 if (err)
835 return err;
836
837 i2c->dev = dev;
838
839 init_completion(&i2c->cmd_complete);
840
841 if (dev->of_node) {
842 err = mxs_i2c_get_ofdata(i2c);
843 if (err)
844 return err;
845 }
846
847
848 i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
849 if (!i2c->dmach) {
850 dev_err(dev, "Failed to request dma\n");
851 return -ENODEV;
852 }
853
854 platform_set_drvdata(pdev, i2c);
855
856
857 err = mxs_i2c_reset(i2c);
858 if (err)
859 return err;
860
861 adap = &i2c->adapter;
862 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
863 adap->owner = THIS_MODULE;
864 adap->algo = &mxs_i2c_algo;
865 adap->dev.parent = dev;
866 adap->nr = pdev->id;
867 adap->dev.of_node = pdev->dev.of_node;
868 i2c_set_adapdata(adap, i2c);
869 err = i2c_add_numbered_adapter(adap);
870 if (err) {
871 dev_err(dev, "Failed to add adapter (%d)\n", err);
872 writel(MXS_I2C_CTRL0_SFTRST,
873 i2c->regs + MXS_I2C_CTRL0_SET);
874 return err;
875 }
876
877 return 0;
878}
879
880static int mxs_i2c_remove(struct platform_device *pdev)
881{
882 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
883
884 i2c_del_adapter(&i2c->adapter);
885
886 if (i2c->dmach)
887 dma_release_channel(i2c->dmach);
888
889 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
890
891 return 0;
892}
893
894static struct platform_driver mxs_i2c_driver = {
895 .driver = {
896 .name = DRIVER_NAME,
897 .of_match_table = mxs_i2c_dt_ids,
898 },
899 .probe = mxs_i2c_probe,
900 .remove = mxs_i2c_remove,
901};
902
903static int __init mxs_i2c_init(void)
904{
905 return platform_driver_register(&mxs_i2c_driver);
906}
907subsys_initcall(mxs_i2c_init);
908
909static void __exit mxs_i2c_exit(void)
910{
911 platform_driver_unregister(&mxs_i2c_driver);
912}
913module_exit(mxs_i2c_exit);
914
915MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
916MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
917MODULE_DESCRIPTION("MXS I2C Bus Driver");
918MODULE_LICENSE("GPL");
919MODULE_ALIAS("platform:" DRIVER_NAME);
920