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15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/errno.h>
20#include <linux/platform_device.h>
21#include <linux/i2c.h>
22#include <linux/interrupt.h>
23#include <linux/wait.h>
24#include <linux/i2c-ocores.h>
25#include <linux/slab.h>
26#include <linux/io.h>
27#include <linux/log2.h>
28
29struct ocores_i2c {
30 void __iomem *base;
31 u32 reg_shift;
32 u32 reg_io_width;
33 wait_queue_head_t wait;
34 struct i2c_adapter adap;
35 struct i2c_msg *msg;
36 int pos;
37 int nmsgs;
38 int state;
39 struct clk *clk;
40 int ip_clock_khz;
41 int bus_clock_khz;
42 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
43 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
44};
45
46
47#define OCI2C_PRELOW 0
48#define OCI2C_PREHIGH 1
49#define OCI2C_CONTROL 2
50#define OCI2C_DATA 3
51#define OCI2C_CMD 4
52#define OCI2C_STATUS 4
53
54#define OCI2C_CTRL_IEN 0x40
55#define OCI2C_CTRL_EN 0x80
56
57#define OCI2C_CMD_START 0x91
58#define OCI2C_CMD_STOP 0x41
59#define OCI2C_CMD_READ 0x21
60#define OCI2C_CMD_WRITE 0x11
61#define OCI2C_CMD_READ_ACK 0x21
62#define OCI2C_CMD_READ_NACK 0x29
63#define OCI2C_CMD_IACK 0x01
64
65#define OCI2C_STAT_IF 0x01
66#define OCI2C_STAT_TIP 0x02
67#define OCI2C_STAT_ARBLOST 0x20
68#define OCI2C_STAT_BUSY 0x40
69#define OCI2C_STAT_NACK 0x80
70
71#define STATE_DONE 0
72#define STATE_START 1
73#define STATE_WRITE 2
74#define STATE_READ 3
75#define STATE_ERROR 4
76
77#define TYPE_OCORES 0
78#define TYPE_GRLIB 1
79
80static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
81{
82 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
83}
84
85static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
86{
87 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
88}
89
90static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
91{
92 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
93}
94
95static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
96{
97 return ioread8(i2c->base + (reg << i2c->reg_shift));
98}
99
100static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
101{
102 return ioread16(i2c->base + (reg << i2c->reg_shift));
103}
104
105static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
106{
107 return ioread32(i2c->base + (reg << i2c->reg_shift));
108}
109
110static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
111{
112 i2c->setreg(i2c, reg, value);
113}
114
115static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
116{
117 return i2c->getreg(i2c, reg);
118}
119
120static void ocores_process(struct ocores_i2c *i2c)
121{
122 struct i2c_msg *msg = i2c->msg;
123 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
124
125 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
126
127 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
128 wake_up(&i2c->wait);
129 return;
130 }
131
132
133 if (stat & OCI2C_STAT_ARBLOST) {
134 i2c->state = STATE_ERROR;
135 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
136 return;
137 }
138
139 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
140 i2c->state =
141 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
142
143 if (stat & OCI2C_STAT_NACK) {
144 i2c->state = STATE_ERROR;
145 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
146 return;
147 }
148 } else
149 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
150
151
152 if (i2c->pos == msg->len) {
153 i2c->nmsgs--;
154 i2c->msg++;
155 i2c->pos = 0;
156 msg = i2c->msg;
157
158 if (i2c->nmsgs) {
159
160 if (!(msg->flags & I2C_M_NOSTART)) {
161 u8 addr = (msg->addr << 1);
162
163 if (msg->flags & I2C_M_RD)
164 addr |= 1;
165
166 i2c->state = STATE_START;
167
168 oc_setreg(i2c, OCI2C_DATA, addr);
169 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
170 return;
171 } else
172 i2c->state = (msg->flags & I2C_M_RD)
173 ? STATE_READ : STATE_WRITE;
174 } else {
175 i2c->state = STATE_DONE;
176 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
177 return;
178 }
179 }
180
181 if (i2c->state == STATE_READ) {
182 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
183 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
184 } else {
185 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
186 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
187 }
188}
189
190static irqreturn_t ocores_isr(int irq, void *dev_id)
191{
192 struct ocores_i2c *i2c = dev_id;
193
194 ocores_process(i2c);
195
196 return IRQ_HANDLED;
197}
198
199static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
200{
201 struct ocores_i2c *i2c = i2c_get_adapdata(adap);
202
203 i2c->msg = msgs;
204 i2c->pos = 0;
205 i2c->nmsgs = num;
206 i2c->state = STATE_START;
207
208 oc_setreg(i2c, OCI2C_DATA,
209 (i2c->msg->addr << 1) |
210 ((i2c->msg->flags & I2C_M_RD) ? 1:0));
211
212 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
213
214 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
215 (i2c->state == STATE_DONE), HZ))
216 return (i2c->state == STATE_DONE) ? num : -EIO;
217 else
218 return -ETIMEDOUT;
219}
220
221static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
222{
223 int prescale;
224 int diff;
225 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
226
227
228 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
229
230 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
231 prescale = clamp(prescale, 0, 0xffff);
232
233 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
234 if (abs(diff) > i2c->bus_clock_khz / 10) {
235 dev_err(dev,
236 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
237 i2c->ip_clock_khz, i2c->bus_clock_khz);
238 return -EINVAL;
239 }
240
241 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
242 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
243
244
245 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
246 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
247
248 return 0;
249}
250
251
252static u32 ocores_func(struct i2c_adapter *adap)
253{
254 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
255}
256
257static const struct i2c_algorithm ocores_algorithm = {
258 .master_xfer = ocores_xfer,
259 .functionality = ocores_func,
260};
261
262static struct i2c_adapter ocores_adapter = {
263 .owner = THIS_MODULE,
264 .name = "i2c-ocores",
265 .class = I2C_CLASS_DEPRECATED,
266 .algo = &ocores_algorithm,
267};
268
269static const struct of_device_id ocores_i2c_match[] = {
270 {
271 .compatible = "opencores,i2c-ocores",
272 .data = (void *)TYPE_OCORES,
273 },
274 {
275 .compatible = "aeroflexgaisler,i2cmst",
276 .data = (void *)TYPE_GRLIB,
277 },
278 {},
279};
280MODULE_DEVICE_TABLE(of, ocores_i2c_match);
281
282#ifdef CONFIG_OF
283
284
285
286static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
287{
288 u32 rd;
289 int rreg = reg;
290 if (reg != OCI2C_PRELOW)
291 rreg--;
292 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
293 if (reg == OCI2C_PREHIGH)
294 return (u8)(rd >> 8);
295 else
296 return (u8)rd;
297}
298
299static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
300{
301 u32 curr, wr;
302 int rreg = reg;
303 if (reg != OCI2C_PRELOW)
304 rreg--;
305 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
306 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
307 if (reg == OCI2C_PRELOW)
308 wr = (curr & 0xff00) | value;
309 else
310 wr = (((u32)value) << 8) | (curr & 0xff);
311 } else {
312 wr = value;
313 }
314 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
315}
316
317static int ocores_i2c_of_probe(struct platform_device *pdev,
318 struct ocores_i2c *i2c)
319{
320 struct device_node *np = pdev->dev.of_node;
321 const struct of_device_id *match;
322 u32 val;
323 u32 clock_frequency;
324 bool clock_frequency_present;
325
326 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
327
328 if (!of_property_read_u32(np, "regstep", &val)) {
329 if (!is_power_of_2(val)) {
330 dev_err(&pdev->dev, "invalid regstep %d\n",
331 val);
332 return -EINVAL;
333 }
334 i2c->reg_shift = ilog2(val);
335 dev_warn(&pdev->dev,
336 "regstep property deprecated, use reg-shift\n");
337 }
338 }
339
340 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
341 &clock_frequency);
342 i2c->bus_clock_khz = 100;
343
344 i2c->clk = devm_clk_get(&pdev->dev, NULL);
345
346 if (!IS_ERR(i2c->clk)) {
347 int ret = clk_prepare_enable(i2c->clk);
348
349 if (ret) {
350 dev_err(&pdev->dev,
351 "clk_prepare_enable failed: %d\n", ret);
352 return ret;
353 }
354 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
355 if (clock_frequency_present)
356 i2c->bus_clock_khz = clock_frequency / 1000;
357 }
358
359 if (i2c->ip_clock_khz == 0) {
360 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
361 &val)) {
362 if (!clock_frequency_present) {
363 dev_err(&pdev->dev,
364 "Missing required parameter 'opencores,ip-clock-frequency'\n");
365 return -ENODEV;
366 }
367 i2c->ip_clock_khz = clock_frequency / 1000;
368 dev_warn(&pdev->dev,
369 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
370 } else {
371 i2c->ip_clock_khz = val / 1000;
372 if (clock_frequency_present)
373 i2c->bus_clock_khz = clock_frequency / 1000;
374 }
375 }
376
377 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
378 &i2c->reg_io_width);
379
380 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
381 if (match && (long)match->data == TYPE_GRLIB) {
382 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
383 i2c->setreg = oc_setreg_grlib;
384 i2c->getreg = oc_getreg_grlib;
385 }
386
387 return 0;
388}
389#else
390#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
391#endif
392
393static int ocores_i2c_probe(struct platform_device *pdev)
394{
395 struct ocores_i2c *i2c;
396 struct ocores_i2c_platform_data *pdata;
397 struct resource *res;
398 int irq;
399 int ret;
400 int i;
401
402 irq = platform_get_irq(pdev, 0);
403 if (irq < 0)
404 return irq;
405
406 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
407 if (!i2c)
408 return -ENOMEM;
409
410 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 i2c->base = devm_ioremap_resource(&pdev->dev, res);
412 if (IS_ERR(i2c->base))
413 return PTR_ERR(i2c->base);
414
415 pdata = dev_get_platdata(&pdev->dev);
416 if (pdata) {
417 i2c->reg_shift = pdata->reg_shift;
418 i2c->reg_io_width = pdata->reg_io_width;
419 i2c->ip_clock_khz = pdata->clock_khz;
420 i2c->bus_clock_khz = 100;
421 } else {
422 ret = ocores_i2c_of_probe(pdev, i2c);
423 if (ret)
424 return ret;
425 }
426
427 if (i2c->reg_io_width == 0)
428 i2c->reg_io_width = 1;
429
430 if (!i2c->setreg || !i2c->getreg) {
431 switch (i2c->reg_io_width) {
432 case 1:
433 i2c->setreg = oc_setreg_8;
434 i2c->getreg = oc_getreg_8;
435 break;
436
437 case 2:
438 i2c->setreg = oc_setreg_16;
439 i2c->getreg = oc_getreg_16;
440 break;
441
442 case 4:
443 i2c->setreg = oc_setreg_32;
444 i2c->getreg = oc_getreg_32;
445 break;
446
447 default:
448 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
449 i2c->reg_io_width);
450 return -EINVAL;
451 }
452 }
453
454 ret = ocores_init(&pdev->dev, i2c);
455 if (ret)
456 return ret;
457
458 init_waitqueue_head(&i2c->wait);
459 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
460 pdev->name, i2c);
461 if (ret) {
462 dev_err(&pdev->dev, "Cannot claim IRQ\n");
463 return ret;
464 }
465
466
467 platform_set_drvdata(pdev, i2c);
468 i2c->adap = ocores_adapter;
469 i2c_set_adapdata(&i2c->adap, i2c);
470 i2c->adap.dev.parent = &pdev->dev;
471 i2c->adap.dev.of_node = pdev->dev.of_node;
472
473
474 ret = i2c_add_adapter(&i2c->adap);
475 if (ret) {
476 dev_err(&pdev->dev, "Failed to add adapter\n");
477 return ret;
478 }
479
480
481 if (pdata) {
482 for (i = 0; i < pdata->num_devices; i++)
483 i2c_new_device(&i2c->adap, pdata->devices + i);
484 }
485
486 return 0;
487}
488
489static int ocores_i2c_remove(struct platform_device *pdev)
490{
491 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
492
493
494 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
495 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
496
497
498 i2c_del_adapter(&i2c->adap);
499
500 if (!IS_ERR(i2c->clk))
501 clk_disable_unprepare(i2c->clk);
502
503 return 0;
504}
505
506#ifdef CONFIG_PM_SLEEP
507static int ocores_i2c_suspend(struct device *dev)
508{
509 struct ocores_i2c *i2c = dev_get_drvdata(dev);
510 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
511
512
513 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
514
515 if (!IS_ERR(i2c->clk))
516 clk_disable_unprepare(i2c->clk);
517 return 0;
518}
519
520static int ocores_i2c_resume(struct device *dev)
521{
522 struct ocores_i2c *i2c = dev_get_drvdata(dev);
523
524 if (!IS_ERR(i2c->clk)) {
525 unsigned long rate;
526 int ret = clk_prepare_enable(i2c->clk);
527
528 if (ret) {
529 dev_err(dev,
530 "clk_prepare_enable failed: %d\n", ret);
531 return ret;
532 }
533 rate = clk_get_rate(i2c->clk) / 1000;
534 if (rate)
535 i2c->ip_clock_khz = rate;
536 }
537 return ocores_init(dev, i2c);
538}
539
540static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
541#define OCORES_I2C_PM (&ocores_i2c_pm)
542#else
543#define OCORES_I2C_PM NULL
544#endif
545
546static struct platform_driver ocores_i2c_driver = {
547 .probe = ocores_i2c_probe,
548 .remove = ocores_i2c_remove,
549 .driver = {
550 .name = "ocores-i2c",
551 .of_match_table = ocores_i2c_match,
552 .pm = OCORES_I2C_PM,
553 },
554};
555
556module_platform_driver(ocores_i2c_driver);
557
558MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
559MODULE_DESCRIPTION("OpenCores I2C bus driver");
560MODULE_LICENSE("GPL");
561MODULE_ALIAS("platform:ocores-i2c");
562
