1#ifndef _QIB_KERNEL_H
2#define _QIB_KERNEL_H
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/dma-mapping.h>
45#include <linux/mutex.h>
46#include <linux/list.h>
47#include <linux/scatterlist.h>
48#include <linux/slab.h>
49#include <linux/io.h>
50#include <linux/fs.h>
51#include <linux/completion.h>
52#include <linux/kref.h>
53#include <linux/sched.h>
54#include <linux/kthread.h>
55
56#include "qib_common.h"
57#include "qib_verbs.h"
58
59
60#define QIB_CHIP_VERS_MAJ 2U
61
62
63#define QIB_CHIP_VERS_MIN 0U
64
65
66#define QIB_OUI 0x001175
67#define QIB_OUI_LSB 40
68
69
70
71
72
73
74
75
76
77struct qlogic_ib_stats {
78 __u64 sps_ints;
79 __u64 sps_errints;
80 __u64 sps_txerrs;
81 __u64 sps_rcverrs;
82 __u64 sps_hwerrs;
83 __u64 sps_nopiobufs;
84 __u64 sps_ctxts;
85 __u64 sps_lenerrs;
86 __u64 sps_buffull;
87 __u64 sps_hdrfull;
88};
89
90extern struct qlogic_ib_stats qib_stats;
91extern const struct pci_error_handlers qib_pci_err_handler;
92
93#define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
94
95
96
97
98
99
100#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
101
102
103
104
105
106
107
108#define QIB_EEP_LOG_CNT (4)
109struct qib_eep_log_mask {
110 u64 errs_to_log;
111 u64 hwerrs_to_log;
112};
113
114
115
116
117
118#ifdef CONFIG_DEBUG_FS
119struct qib_opcode_stats_perctx;
120#endif
121
122struct qib_ctxtdata {
123 void **rcvegrbuf;
124 dma_addr_t *rcvegrbuf_phys;
125
126 void *rcvhdrq;
127
128 void *rcvhdrtail_kvaddr;
129
130
131
132
133 void *tid_pg_list;
134
135
136
137
138
139 unsigned long *user_event_mask;
140
141 wait_queue_head_t wait;
142
143
144
145
146 dma_addr_t rcvegr_phys;
147
148 dma_addr_t rcvhdrq_phys;
149 dma_addr_t rcvhdrqtailaddr_phys;
150
151
152
153
154
155 int cnt;
156
157
158
159
160
161 unsigned ctxt;
162
163 int node_id;
164
165 u16 subctxt_cnt;
166
167 u16 subctxt_id;
168
169 u16 rcvegrcnt;
170
171 u16 rcvegr_tid_base;
172
173 u32 piocnt;
174
175 u32 pio_base;
176
177 u32 piobufs;
178
179 u32 rcvegrbuf_chunks;
180
181 u16 rcvegrbufs_perchunk;
182
183 u16 rcvegrbufs_perchunk_shift;
184
185 size_t rcvegrbuf_size;
186
187 size_t rcvhdrq_size;
188
189 unsigned long flag;
190
191 u32 tidcursor;
192
193 u32 rcvwait_to;
194
195 u32 piowait_to;
196
197 u32 rcvnowait;
198
199 u32 pionowait;
200
201 u32 urgent;
202
203 u32 urgent_poll;
204
205 pid_t pid;
206 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
207
208 char comm[16];
209
210 u16 pkeys[4];
211
212 struct qib_devdata *dd;
213
214 struct qib_pportdata *ppd;
215
216 void *subctxt_uregbase;
217
218 void *subctxt_rcvegrbuf;
219
220 void *subctxt_rcvhdr_base;
221
222 u32 userversion;
223
224 u32 active_slaves;
225
226 u16 poll_type;
227
228 u8 seq_cnt;
229 u8 redirect_seq_cnt;
230
231 u32 head;
232
233 struct qib_qp *lookaside_qp;
234 u32 lookaside_qpn;
235
236 struct list_head qp_wait_list;
237#ifdef CONFIG_DEBUG_FS
238
239 struct qib_opcode_stats_perctx *opstats;
240#endif
241};
242
243struct qib_sge_state;
244
245struct qib_sdma_txreq {
246 int flags;
247 int sg_count;
248 dma_addr_t addr;
249 void (*callback)(struct qib_sdma_txreq *, int);
250 u16 start_idx;
251 u16 next_descq_idx;
252 struct list_head list;
253};
254
255struct qib_sdma_desc {
256 __le64 qw[2];
257};
258
259struct qib_verbs_txreq {
260 struct qib_sdma_txreq txreq;
261 struct qib_qp *qp;
262 struct qib_swqe *wqe;
263 u32 dwords;
264 u16 hdr_dwords;
265 u16 hdr_inx;
266 struct qib_pio_header *align_buf;
267 struct qib_mregion *mr;
268 struct qib_sge_state *ss;
269};
270
271#define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
272#define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
273#define QIB_SDMA_TXREQ_F_INTREQ 0x4
274#define QIB_SDMA_TXREQ_F_FREEBUF 0x8
275#define QIB_SDMA_TXREQ_F_FREEDESC 0x10
276
277#define QIB_SDMA_TXREQ_S_OK 0
278#define QIB_SDMA_TXREQ_S_SENDERROR 1
279#define QIB_SDMA_TXREQ_S_ABORTED 2
280#define QIB_SDMA_TXREQ_S_SHUTDOWN 3
281
282
283
284
285
286
287#define QIB_IB_CFG_LIDLMC 0
288#define QIB_IB_CFG_LWID_ENB 2
289#define QIB_IB_CFG_LWID 3
290#define QIB_IB_CFG_SPD_ENB 4
291#define QIB_IB_CFG_SPD 5
292#define QIB_IB_CFG_RXPOL_ENB 6
293#define QIB_IB_CFG_LREV_ENB 7
294#define QIB_IB_CFG_LINKLATENCY 8
295#define QIB_IB_CFG_HRTBT 9
296#define QIB_IB_CFG_OP_VLS 10
297#define QIB_IB_CFG_VL_HIGH_CAP 11
298#define QIB_IB_CFG_VL_LOW_CAP 12
299#define QIB_IB_CFG_OVERRUN_THRESH 13
300#define QIB_IB_CFG_PHYERR_THRESH 14
301#define QIB_IB_CFG_LINKDEFAULT 15
302#define QIB_IB_CFG_PKEYS 16
303#define QIB_IB_CFG_MTU 17
304#define QIB_IB_CFG_LSTATE 18
305#define QIB_IB_CFG_VL_HIGH_LIMIT 19
306#define QIB_IB_CFG_PMA_TICKS 20
307#define QIB_IB_CFG_PORT 21
308
309
310
311
312
313
314#define IB_LINKCMD_DOWN (0 << 16)
315#define IB_LINKCMD_ARMED (1 << 16)
316#define IB_LINKCMD_ACTIVE (2 << 16)
317#define IB_LINKINITCMD_NOP 0
318#define IB_LINKINITCMD_POLL 1
319#define IB_LINKINITCMD_SLEEP 2
320#define IB_LINKINITCMD_DISABLE 3
321
322
323
324
325#define QIB_IB_LINKDOWN 0
326#define QIB_IB_LINKARM 1
327#define QIB_IB_LINKACTIVE 2
328#define QIB_IB_LINKDOWN_ONLY 3
329#define QIB_IB_LINKDOWN_SLEEP 4
330#define QIB_IB_LINKDOWN_DISABLE 5
331
332
333
334
335
336
337
338
339#define QIB_IB_SDR 1
340#define QIB_IB_DDR 2
341#define QIB_IB_QDR 4
342
343#define QIB_DEFAULT_MTU 4096
344
345
346#define QIB_MAX_IB_PORTS 2
347
348
349
350
351#define QIB_IB_TBL_VL_HIGH_ARB 1
352#define QIB_IB_TBL_VL_LOW_ARB 2
353
354
355
356
357
358
359#define QIB_RCVCTRL_TAILUPD_ENB 0x01
360#define QIB_RCVCTRL_TAILUPD_DIS 0x02
361#define QIB_RCVCTRL_CTXT_ENB 0x04
362#define QIB_RCVCTRL_CTXT_DIS 0x08
363#define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
364#define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
365#define QIB_RCVCTRL_PKEY_ENB 0x40
366#define QIB_RCVCTRL_PKEY_DIS 0x80
367#define QIB_RCVCTRL_BP_ENB 0x0100
368#define QIB_RCVCTRL_BP_DIS 0x0200
369#define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
370#define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
371
372
373
374
375
376
377
378
379#define QIB_SENDCTRL_DISARM (0x1000)
380#define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
381
382#define QIB_SENDCTRL_AVAIL_DIS (0x4000)
383#define QIB_SENDCTRL_AVAIL_ENB (0x8000)
384#define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
385#define QIB_SENDCTRL_SEND_DIS (0x20000)
386#define QIB_SENDCTRL_SEND_ENB (0x40000)
387#define QIB_SENDCTRL_FLUSH (0x80000)
388#define QIB_SENDCTRL_CLEAR (0x100000)
389#define QIB_SENDCTRL_DISARM_ALL (0x200000)
390
391
392
393
394
395
396
397
398#define QIBPORTCNTR_PKTSEND 0U
399#define QIBPORTCNTR_WORDSEND 1U
400#define QIBPORTCNTR_PSXMITDATA 2U
401#define QIBPORTCNTR_PSXMITPKTS 3U
402#define QIBPORTCNTR_PSXMITWAIT 4U
403#define QIBPORTCNTR_SENDSTALL 5U
404
405#define QIBPORTCNTR_PKTRCV 6U
406#define QIBPORTCNTR_PSRCVDATA 7U
407#define QIBPORTCNTR_PSRCVPKTS 8U
408#define QIBPORTCNTR_RCVEBP 9U
409#define QIBPORTCNTR_RCVOVFL 10U
410#define QIBPORTCNTR_WORDRCV 11U
411
412#define QIBPORTCNTR_RXLOCALPHYERR 12U
413#define QIBPORTCNTR_RXVLERR 13U
414#define QIBPORTCNTR_ERRICRC 14U
415#define QIBPORTCNTR_ERRVCRC 15U
416#define QIBPORTCNTR_ERRLPCRC 16U
417#define QIBPORTCNTR_BADFORMAT 17U
418#define QIBPORTCNTR_ERR_RLEN 18U
419#define QIBPORTCNTR_IBSYMBOLERR 19U
420#define QIBPORTCNTR_INVALIDRLEN 20U
421#define QIBPORTCNTR_UNSUPVL 21U
422#define QIBPORTCNTR_EXCESSBUFOVFL 22U
423#define QIBPORTCNTR_ERRLINK 23U
424#define QIBPORTCNTR_IBLINKDOWN 24U
425#define QIBPORTCNTR_IBLINKERRRECOV 25U
426#define QIBPORTCNTR_LLI 26U
427
428#define QIBPORTCNTR_RXDROPPKT 27U
429#define QIBPORTCNTR_VL15PKTDROP 28U
430#define QIBPORTCNTR_ERRPKEY 29U
431#define QIBPORTCNTR_KHDROVFL 30U
432
433#define QIBPORTCNTR_PSINTERVAL 31U
434#define QIBPORTCNTR_PSSTART 32U
435#define QIBPORTCNTR_PSSTAT 33U
436
437
438#define ACTIVITY_TIMER 5
439
440#define MAX_NAME_SIZE 64
441
442#ifdef CONFIG_INFINIBAND_QIB_DCA
443struct qib_irq_notify;
444#endif
445
446struct qib_msix_entry {
447 struct msix_entry msix;
448 void *arg;
449#ifdef CONFIG_INFINIBAND_QIB_DCA
450 int dca;
451 int rcv;
452 struct qib_irq_notify *notifier;
453#endif
454 char name[MAX_NAME_SIZE];
455 cpumask_var_t mask;
456};
457
458
459
460
461
462
463struct qib_chip_specific;
464struct qib_chipport_specific;
465
466enum qib_sdma_states {
467 qib_sdma_state_s00_hw_down,
468 qib_sdma_state_s10_hw_start_up_wait,
469 qib_sdma_state_s20_idle,
470 qib_sdma_state_s30_sw_clean_up_wait,
471 qib_sdma_state_s40_hw_clean_up_wait,
472 qib_sdma_state_s50_hw_halt_wait,
473 qib_sdma_state_s99_running,
474};
475
476enum qib_sdma_events {
477 qib_sdma_event_e00_go_hw_down,
478 qib_sdma_event_e10_go_hw_start,
479 qib_sdma_event_e20_hw_started,
480 qib_sdma_event_e30_go_running,
481 qib_sdma_event_e40_sw_cleaned,
482 qib_sdma_event_e50_hw_cleaned,
483 qib_sdma_event_e60_hw_halted,
484 qib_sdma_event_e70_go_idle,
485 qib_sdma_event_e7220_err_halted,
486 qib_sdma_event_e7322_err_halted,
487 qib_sdma_event_e90_timer_tick,
488};
489
490extern char *qib_sdma_state_names[];
491extern char *qib_sdma_event_names[];
492
493struct sdma_set_state_action {
494 unsigned op_enable:1;
495 unsigned op_intenable:1;
496 unsigned op_halt:1;
497 unsigned op_drain:1;
498 unsigned go_s99_running_tofalse:1;
499 unsigned go_s99_running_totrue:1;
500};
501
502struct qib_sdma_state {
503 struct kref kref;
504 struct completion comp;
505 enum qib_sdma_states current_state;
506 struct sdma_set_state_action *set_state_action;
507 unsigned current_op;
508 unsigned go_s99_running;
509 unsigned first_sendbuf;
510 unsigned last_sendbuf;
511
512 enum qib_sdma_states previous_state;
513 unsigned previous_op;
514 enum qib_sdma_events last_event;
515};
516
517struct xmit_wait {
518 struct timer_list timer;
519 u64 counter;
520 u8 flags;
521 struct cache {
522 u64 psxmitdata;
523 u64 psrcvdata;
524 u64 psxmitpkts;
525 u64 psrcvpkts;
526 u64 psxmitwait;
527 } counter_cache;
528};
529
530
531
532
533
534
535
536struct qib_pportdata {
537 struct qib_ibport ibport_data;
538
539 struct qib_devdata *dd;
540 struct qib_chippport_specific *cpspec;
541 struct kobject pport_kobj;
542 struct kobject pport_cc_kobj;
543 struct kobject sl2vl_kobj;
544 struct kobject diagc_kobj;
545
546
547 __be64 guid;
548
549
550 u32 lflags;
551
552 u32 state_wanted;
553 spinlock_t lflags_lock;
554
555
556 atomic_t pkeyrefs[4];
557
558
559
560
561
562 u64 *statusp;
563
564
565
566
567 struct qib_sdma_desc *sdma_descq;
568 struct workqueue_struct *qib_wq;
569 struct qib_sdma_state sdma_state;
570 dma_addr_t sdma_descq_phys;
571 volatile __le64 *sdma_head_dma;
572 dma_addr_t sdma_head_phys;
573 u16 sdma_descq_cnt;
574
575
576 spinlock_t sdma_lock ____cacheline_aligned_in_smp;
577 struct list_head sdma_activelist;
578 struct list_head sdma_userpending;
579 u64 sdma_descq_added;
580 u64 sdma_descq_removed;
581 u16 sdma_descq_tail;
582 u16 sdma_descq_head;
583 u8 sdma_generation;
584 u8 sdma_intrequest;
585
586 struct tasklet_struct sdma_sw_clean_up_task
587 ____cacheline_aligned_in_smp;
588
589 wait_queue_head_t state_wait;
590
591
592 unsigned hol_state;
593 struct timer_list hol_timer;
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610 u64 lastibcstat;
611
612
613
614
615
616
617
618 unsigned long p_rcvctrl;
619 unsigned long p_sendctrl;
620
621 u32 ibmtu;
622
623
624
625
626 u32 ibmaxlen;
627
628
629
630
631 u32 init_ibmaxlen;
632
633 u16 lid;
634
635 u16 pkeys[4];
636
637 u8 lmc;
638 u8 link_width_supported;
639 u8 link_speed_supported;
640 u8 link_width_enabled;
641 u8 link_speed_enabled;
642 u8 link_width_active;
643 u8 link_speed_active;
644 u8 vls_supported;
645 u8 vls_operational;
646
647 u8 rx_pol_inv;
648
649 u8 hw_pidx;
650 u8 port;
651
652 u8 delay_mult;
653
654
655 u8 led_override;
656 u16 led_override_timeoff;
657 u8 led_override_vals[2];
658 u8 led_override_phase;
659 atomic_t led_override_timer_active;
660
661 struct timer_list led_override_timer;
662 struct xmit_wait cong_stats;
663 struct timer_list symerr_clear_timer;
664
665
666 spinlock_t cc_shadow_lock
667 ____cacheline_aligned_in_smp;
668
669
670 struct cc_table_shadow *ccti_entries_shadow;
671
672
673 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;
674
675
676 struct ib_cc_table_entry_shadow *ccti_entries;
677
678
679 struct ib_cc_congestion_entry_shadow *congestion_entries;
680
681
682
683
684 u16 cc_supported_table_entries;
685
686
687 u16 total_cct_entry;
688
689
690 u16 cc_sl_control_map;
691
692
693 u16 ccti_limit;
694
695
696 u8 cc_max_table_entries;
697};
698
699
700
701
702
703
704
705
706struct diag_observer;
707
708typedef int (*diag_hook) (struct qib_devdata *dd,
709 const struct diag_observer *op,
710 u32 offs, u64 *data, u64 mask, int only_32);
711
712struct diag_observer {
713 diag_hook hook;
714 u32 bottom;
715 u32 top;
716};
717
718extern int qib_register_observer(struct qib_devdata *dd,
719 const struct diag_observer *op);
720
721
722struct diag_observer_list_elt;
723
724
725
726
727
728
729struct qib_devdata {
730 struct qib_ibdev verbs_dev;
731 struct list_head list;
732
733
734 struct pci_dev *pcidev;
735 struct cdev *user_cdev;
736 struct cdev *diag_cdev;
737 struct device *user_device;
738 struct device *diag_device;
739
740
741 u64 __iomem *kregbase;
742
743 u64 __iomem *kregend;
744
745 resource_size_t physaddr;
746
747 struct qib_ctxtdata **rcd;
748
749
750
751
752 struct qib_pportdata *pport;
753 struct qib_chip_specific *cspec;
754
755
756 void __iomem *pio2kbase;
757
758 void __iomem *pio4kbase;
759
760 void __iomem *piobase;
761
762 u64 __iomem *userbase;
763 void __iomem *piovl15base;
764
765
766
767
768
769
770
771 volatile __le64 *pioavailregs_dma;
772
773 dma_addr_t pioavailregs_phys;
774
775
776
777
778
779
780
781 int (*f_intr_fallback)(struct qib_devdata *);
782
783 int (*f_reset)(struct qib_devdata *);
784 void (*f_quiet_serdes)(struct qib_pportdata *);
785 int (*f_bringup_serdes)(struct qib_pportdata *);
786 int (*f_early_init)(struct qib_devdata *);
787 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
788 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
789 u32, unsigned long);
790 void (*f_cleanup)(struct qib_devdata *);
791 void (*f_setextled)(struct qib_pportdata *, u32);
792
793 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
794
795 void (*f_free_irq)(struct qib_devdata *);
796 struct qib_message_header *(*f_get_msgheader)
797 (struct qib_devdata *, __le32 *);
798 void (*f_config_ctxts)(struct qib_devdata *);
799 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
800 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
801 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
802 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
803 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
804 u32 (*f_iblink_state)(u64);
805 u8 (*f_ibphys_portstate)(u64);
806 void (*f_xgxs_reset)(struct qib_pportdata *);
807
808 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
809 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
810
811 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
812 u32 mask);
813
814 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
815
816
817
818
819
820
821 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
822 int ctxt);
823
824 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
825 void (*f_set_intr_state)(struct qib_devdata *, u32);
826 void (*f_set_armlaunch)(struct qib_devdata *, u32);
827 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
828 int (*f_late_initreg)(struct qib_devdata *);
829 int (*f_init_sdma_regs)(struct qib_pportdata *);
830 u16 (*f_sdma_gethead)(struct qib_pportdata *);
831 int (*f_sdma_busy)(struct qib_pportdata *);
832 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
833 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
834 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
835 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
836 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
837 void (*f_sdma_init_early)(struct qib_pportdata *);
838 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
839 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
840 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
841 u64 (*f_portcntr)(struct qib_pportdata *, u32);
842 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
843 u64 **);
844 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
845 char **, u64 **);
846 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
847 void (*f_initvl15_bufs)(struct qib_devdata *);
848 void (*f_init_ctxt)(struct qib_ctxtdata *);
849 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
850 struct qib_ctxtdata *);
851 void (*f_writescratch)(struct qib_devdata *, u32);
852 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
853#ifdef CONFIG_INFINIBAND_QIB_DCA
854 int (*f_notify_dca)(struct qib_devdata *, unsigned long event);
855#endif
856
857 char *boardname;
858
859
860 u64 tidtemplate;
861
862 u64 tidinvalid;
863
864
865 u32 pioavregs;
866
867 u32 flags;
868
869 u32 lastctxt_piobuf;
870
871
872 u64 z_int_counter;
873
874 u64 __percpu *int_counter;
875
876
877 u32 pbufsctxt;
878
879 u32 ctxts_extrabuf;
880
881
882
883
884 u32 cfgctxts;
885
886
887
888 u32 freectxts;
889
890
891
892
893
894 u32 upd_pio_shadow;
895
896
897 u32 maxpkts_call;
898 u32 avgpkts_call;
899 u64 nopiobufs;
900
901
902 u16 vendorid;
903
904 u16 deviceid;
905
906 int wc_cookie;
907 unsigned long wc_base;
908 unsigned long wc_len;
909
910
911 struct page **pageshadow;
912
913 dma_addr_t *physshadow;
914 u64 __iomem *egrtidbase;
915 spinlock_t sendctrl_lock;
916
917 spinlock_t uctxt_lock;
918
919
920
921
922
923 u64 *devstatusp;
924 char *freezemsg;
925 u32 freezelen;
926
927 struct timer_list stats_timer;
928
929
930 struct timer_list intrchk_timer;
931 unsigned long ureg_align;
932
933
934
935
936
937 spinlock_t pioavail_lock;
938
939
940
941 u32 last_pio;
942
943
944
945 u32 min_kernel_pio;
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961 unsigned long pioavailshadow[6];
962
963 unsigned long pioavailkernel[6];
964
965 unsigned long pio_need_disarm[3];
966
967 unsigned long pio_writing[3];
968
969 u64 revision;
970
971 __be64 base_guid;
972
973
974
975
976
977 u64 piobufbase;
978 u32 pio2k_bufbase;
979
980
981
982
983 u32 nguid;
984
985
986
987
988 unsigned long rcvctrl;
989 unsigned long sendctrl;
990
991
992 u32 rcvhdrcnt;
993
994 u32 rcvhdrsize;
995
996 u32 rcvhdrentsize;
997
998 u32 ctxtcnt;
999
1000 u32 palign;
1001
1002 u32 piobcnt2k;
1003
1004 u32 piosize2k;
1005
1006 u32 piosize2kmax_dwords;
1007
1008 u32 piobcnt4k;
1009
1010 u32 piosize4k;
1011
1012 u32 rcvegrbase;
1013
1014 u32 rcvtidbase;
1015
1016 u32 rcvtidcnt;
1017
1018 u32 uregbase;
1019
1020 u32 control;
1021
1022
1023 u32 align4k;
1024
1025 u16 rcvegrbufsize;
1026
1027 u16 rcvegrbufsize_shift;
1028
1029 u32 lbus_width;
1030
1031 u32 lbus_speed;
1032 int unit;
1033
1034
1035
1036 u32 msi_lo;
1037
1038 u32 msi_hi;
1039
1040 u16 msi_data;
1041
1042 u32 pcibar0;
1043
1044 u32 pcibar1;
1045 u64 rhdrhead_intr_off;
1046
1047
1048
1049
1050
1051 u8 serial[16];
1052
1053 u8 boardversion[96];
1054 u8 lbus_info[32];
1055
1056 u8 majrev;
1057
1058 u8 minrev;
1059
1060
1061
1062 u8 num_pports;
1063
1064 u8 first_user_ctxt;
1065 u8 n_krcv_queues;
1066 u8 qpn_mask;
1067 u8 skip_kctxt_mask;
1068
1069 u16 rhf_offset;
1070
1071
1072
1073
1074 u8 gpio_sda_num;
1075 u8 gpio_scl_num;
1076 u8 twsi_eeprom_dev;
1077 u8 board_atten;
1078
1079
1080
1081 spinlock_t eep_st_lock;
1082
1083 struct mutex eep_lock;
1084 uint64_t traffic_wds;
1085
1086
1087
1088
1089 struct qib_eep_log_mask eep_st_masks[QIB_EEP_LOG_CNT];
1090 struct qib_diag_client *diag_client;
1091 spinlock_t qib_diag_trans_lock;
1092 struct diag_observer_list_elt *diag_observer_list;
1093
1094 u8 psxmitwait_supported;
1095
1096 u16 psxmitwait_check_rate;
1097
1098 struct tasklet_struct error_tasklet;
1099
1100 struct kthread_worker *worker;
1101
1102 int assigned_node_id;
1103};
1104
1105
1106#define QIB_HOL_UP 0
1107#define QIB_HOL_INIT 1
1108
1109#define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1110#define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1111#define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1112#define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1113#define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1114
1115
1116#define TXCHK_CHG_TYPE_DIS1 3
1117#define TXCHK_CHG_TYPE_ENAB1 2
1118#define TXCHK_CHG_TYPE_KERN 1
1119#define TXCHK_CHG_TYPE_USER 0
1120
1121#define QIB_CHASE_TIME msecs_to_jiffies(145)
1122#define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1123
1124
1125struct qib_filedata {
1126 struct qib_ctxtdata *rcd;
1127 unsigned subctxt;
1128 unsigned tidcursor;
1129 struct qib_user_sdma_queue *pq;
1130 int rec_cpu_num;
1131};
1132
1133extern struct list_head qib_dev_list;
1134extern spinlock_t qib_devs_lock;
1135extern struct qib_devdata *qib_lookup(int unit);
1136extern u32 qib_cpulist_count;
1137extern unsigned long *qib_cpulist;
1138
1139extern unsigned qib_cc_table_size;
1140int qib_init(struct qib_devdata *, int);
1141int init_chip_wc_pat(struct qib_devdata *dd, u32);
1142int qib_enable_wc(struct qib_devdata *dd);
1143void qib_disable_wc(struct qib_devdata *dd);
1144int qib_count_units(int *npresentp, int *nupp);
1145int qib_count_active_units(void);
1146
1147int qib_cdev_init(int minor, const char *name,
1148 const struct file_operations *fops,
1149 struct cdev **cdevp, struct device **devp);
1150void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1151int qib_dev_init(void);
1152void qib_dev_cleanup(void);
1153
1154int qib_diag_add(struct qib_devdata *);
1155void qib_diag_remove(struct qib_devdata *);
1156void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1157void qib_sdma_update_tail(struct qib_pportdata *, u16);
1158
1159int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1160void qib_bad_intrstatus(struct qib_devdata *);
1161void qib_handle_urcv(struct qib_devdata *, u64);
1162
1163
1164void qib_chip_cleanup(struct qib_devdata *);
1165
1166void qib_chip_done(void);
1167
1168
1169int qib_unordered_wc(void);
1170void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1171
1172void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1173int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1174void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1175void qib_cancel_sends(struct qib_pportdata *);
1176
1177int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1178int qib_setup_eagerbufs(struct qib_ctxtdata *);
1179void qib_set_ctxtcnt(struct qib_devdata *);
1180int qib_create_ctxts(struct qib_devdata *dd);
1181struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int);
1182int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1183void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1184
1185u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1186int qib_reset_device(int);
1187int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1188int qib_set_linkstate(struct qib_pportdata *, u8);
1189int qib_set_mtu(struct qib_pportdata *, u16);
1190int qib_set_lid(struct qib_pportdata *, u32, u8);
1191void qib_hol_down(struct qib_pportdata *);
1192void qib_hol_init(struct qib_pportdata *);
1193void qib_hol_up(struct qib_pportdata *);
1194void qib_hol_event(unsigned long);
1195void qib_disable_after_error(struct qib_devdata *);
1196int qib_set_uevent_bits(struct qib_pportdata *, const int);
1197
1198
1199#define ctxt_fp(fp) \
1200 (((struct qib_filedata *)(fp)->private_data)->rcd)
1201#define subctxt_fp(fp) \
1202 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1203#define tidcursor_fp(fp) \
1204 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1205#define user_sdma_queue_fp(fp) \
1206 (((struct qib_filedata *)(fp)->private_data)->pq)
1207
1208static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1209{
1210 return ppd->dd;
1211}
1212
1213static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1214{
1215 return container_of(dev, struct qib_devdata, verbs_dev);
1216}
1217
1218static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1219{
1220 return dd_from_dev(to_idev(ibdev));
1221}
1222
1223static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1224{
1225 return container_of(ibp, struct qib_pportdata, ibport_data);
1226}
1227
1228static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u8 port)
1229{
1230 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1231 unsigned pidx = port - 1;
1232
1233 WARN_ON(pidx >= dd->num_pports);
1234 return &dd->pport[pidx].ibport_data;
1235}
1236
1237
1238
1239
1240#define QIB_HAS_LINK_LATENCY 0x1
1241#define QIB_INITTED 0x2
1242#define QIB_DOING_RESET 0x4
1243#define QIB_PRESENT 0x8
1244#define QIB_PIO_FLUSH_WC 0x10
1245#define QIB_HAS_THRESH_UPDATE 0x40
1246#define QIB_HAS_SDMA_TIMEOUT 0x80
1247#define QIB_USE_SPCL_TRIG 0x100
1248#define QIB_NODMA_RTAIL 0x200
1249#define QIB_HAS_INTX 0x800
1250#define QIB_HAS_SEND_DMA 0x1000
1251#define QIB_HAS_VLSUPP 0x2000
1252#define QIB_HAS_HDRSUPP 0x4000
1253#define QIB_BADINTR 0x8000
1254#define QIB_DCA_ENABLED 0x10000
1255#define QIB_HAS_QSFP 0x20000
1256
1257
1258
1259
1260#define QIBL_LINKV 0x1
1261#define QIBL_LINKDOWN 0x8
1262#define QIBL_LINKINIT 0x10
1263#define QIBL_LINKARMED 0x20
1264#define QIBL_LINKACTIVE 0x40
1265
1266#define QIBL_IB_AUTONEG_INPROG 0x1000
1267#define QIBL_IB_AUTONEG_FAILED 0x2000
1268#define QIBL_IB_LINK_DISABLED 0x4000
1269
1270#define QIBL_IB_FORCE_NOTIFY 0x8000
1271
1272
1273#define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1274
1275
1276
1277
1278#define QIB_CTXT_WAITING_RCV 2
1279
1280#define QIB_CTXT_MASTER_UNINIT 4
1281
1282#define QIB_CTXT_WAITING_URG 5
1283
1284
1285void qib_free_data(struct qib_ctxtdata *dd);
1286void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1287 u32, struct qib_ctxtdata *);
1288struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1289 const struct pci_device_id *);
1290struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1291 const struct pci_device_id *);
1292struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1293 const struct pci_device_id *);
1294void qib_free_devdata(struct qib_devdata *);
1295struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1296
1297#define QIB_TWSI_NO_DEV 0xFF
1298
1299int qib_twsi_reset(struct qib_devdata *dd);
1300int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1301 int len);
1302int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1303 const void *buffer, int len);
1304void qib_get_eeprom_info(struct qib_devdata *);
1305#define qib_inc_eeprom_err(dd, eidx, incr)
1306void qib_dump_lookup_output_queue(struct qib_devdata *);
1307void qib_force_pio_avail_update(struct qib_devdata *);
1308void qib_clear_symerror_on_linkup(unsigned long opaque);
1309
1310
1311
1312
1313
1314
1315#define QIB_LED_PHYS 1
1316#define QIB_LED_LOG 2
1317void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1318
1319
1320int qib_setup_sdma(struct qib_pportdata *);
1321void qib_teardown_sdma(struct qib_pportdata *);
1322void __qib_sdma_intr(struct qib_pportdata *);
1323void qib_sdma_intr(struct qib_pportdata *);
1324void qib_user_sdma_send_desc(struct qib_pportdata *dd,
1325 struct list_head *pktlist);
1326int qib_sdma_verbs_send(struct qib_pportdata *, struct qib_sge_state *,
1327 u32, struct qib_verbs_txreq *);
1328
1329int qib_sdma_make_progress(struct qib_pportdata *dd);
1330
1331static inline int qib_sdma_empty(const struct qib_pportdata *ppd)
1332{
1333 return ppd->sdma_descq_added == ppd->sdma_descq_removed;
1334}
1335
1336
1337static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1338{
1339 return ppd->sdma_descq_cnt -
1340 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1341}
1342
1343static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1344{
1345 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1346}
1347int qib_sdma_running(struct qib_pportdata *);
1348void dump_sdma_state(struct qib_pportdata *ppd);
1349void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1350void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1351
1352
1353
1354
1355#define QIB_DFLT_RCVHDRSIZE 9
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368#define QIB_RCVHDR_ENTSIZE 32
1369
1370int qib_get_user_pages(unsigned long, size_t, struct page **);
1371void qib_release_user_pages(struct page **, size_t);
1372int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1373int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1374u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1375void qib_sendbuf_done(struct qib_devdata *, unsigned);
1376
1377static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1378{
1379 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1380}
1381
1382static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1383{
1384
1385
1386
1387
1388 return (u32) le64_to_cpu(
1389 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr));
1390}
1391
1392static inline u32 qib_get_hdrqtail(const struct qib_ctxtdata *rcd)
1393{
1394 const struct qib_devdata *dd = rcd->dd;
1395 u32 hdrqtail;
1396
1397 if (dd->flags & QIB_NODMA_RTAIL) {
1398 __le32 *rhf_addr;
1399 u32 seq;
1400
1401 rhf_addr = (__le32 *) rcd->rcvhdrq +
1402 rcd->head + dd->rhf_offset;
1403 seq = qib_hdrget_seq(rhf_addr);
1404 hdrqtail = rcd->head;
1405 if (seq == rcd->seq_cnt)
1406 hdrqtail++;
1407 } else
1408 hdrqtail = qib_get_rcvhdrtail(rcd);
1409
1410 return hdrqtail;
1411}
1412
1413
1414
1415
1416
1417extern const char ib_qib_version[];
1418
1419int qib_device_create(struct qib_devdata *);
1420void qib_device_remove(struct qib_devdata *);
1421
1422int qib_create_port_files(struct ib_device *ibdev, u8 port_num,
1423 struct kobject *kobj);
1424int qib_verbs_register_sysfs(struct qib_devdata *);
1425void qib_verbs_unregister_sysfs(struct qib_devdata *);
1426
1427extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1428
1429int __init qib_init_qibfs(void);
1430int __exit qib_exit_qibfs(void);
1431
1432int qibfs_add(struct qib_devdata *);
1433int qibfs_remove(struct qib_devdata *);
1434
1435int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1436int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1437 const struct pci_device_id *);
1438void qib_pcie_ddcleanup(struct qib_devdata *);
1439int qib_pcie_params(struct qib_devdata *, u32, u32 *, struct qib_msix_entry *);
1440int qib_reinit_intr(struct qib_devdata *);
1441void qib_enable_intx(struct pci_dev *);
1442void qib_nomsi(struct qib_devdata *);
1443void qib_nomsix(struct qib_devdata *);
1444void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1445void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1446
1447u64 qib_int_counter(struct qib_devdata *);
1448
1449u64 qib_sps_ints(void);
1450
1451
1452
1453
1454dma_addr_t qib_map_page(struct pci_dev *, struct page *, unsigned long,
1455 size_t, int);
1456const char *qib_get_unit_name(int unit);
1457
1458
1459
1460
1461
1462static inline void qib_flush_wc(void)
1463{
1464#if defined(CONFIG_X86_64)
1465 asm volatile("sfence" : : : "memory");
1466#else
1467 wmb();
1468#endif
1469}
1470
1471
1472extern unsigned qib_ibmtu;
1473extern ushort qib_cfgctxts;
1474extern ushort qib_num_cfg_vls;
1475extern ushort qib_mini_init;
1476extern unsigned qib_n_krcv_queues;
1477extern unsigned qib_sdma_fetch_arb;
1478extern unsigned qib_compat_ddr_negotiate;
1479extern int qib_special_trigger;
1480extern unsigned qib_numa_aware;
1481
1482extern struct mutex qib_mutex;
1483
1484
1485#define STATUS_TIMEOUT 60
1486
1487#define QIB_DRV_NAME "ib_qib"
1488#define QIB_USER_MINOR_BASE 0
1489#define QIB_TRACE_MINOR 127
1490#define QIB_DIAGPKT_MINOR 128
1491#define QIB_DIAG_MINOR_BASE 129
1492#define QIB_NMINORS 255
1493
1494#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1495#define PCI_VENDOR_ID_QLOGIC 0x1077
1496#define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1497#define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1498#define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509#define qib_early_err(dev, fmt, ...) \
1510 dev_err(dev, fmt, ##__VA_ARGS__)
1511
1512#define qib_dev_err(dd, fmt, ...) \
1513 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1514 qib_get_unit_name((dd)->unit), ##__VA_ARGS__)
1515
1516#define qib_dev_warn(dd, fmt, ...) \
1517 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1518 qib_get_unit_name((dd)->unit), ##__VA_ARGS__)
1519
1520#define qib_dev_porterr(dd, port, fmt, ...) \
1521 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1522 qib_get_unit_name((dd)->unit), (dd)->unit, (port), \
1523 ##__VA_ARGS__)
1524
1525#define qib_devinfo(pcidev, fmt, ...) \
1526 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__)
1527
1528
1529
1530
1531struct qib_hwerror_msgs {
1532 u64 mask;
1533 const char *msg;
1534 size_t sz;
1535};
1536
1537#define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1538
1539
1540void qib_format_hwerrors(u64 hwerrs,
1541 const struct qib_hwerror_msgs *hwerrmsgs,
1542 size_t nhwerrmsgs, char *msg, size_t lmsg);
1543#endif
1544