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14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/card.h>
31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/sd.h>
34#include <linux/mmc/sdio.h>
35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
37#include <linux/regulator/consumer.h>
38#include <linux/of.h>
39#include <linux/of_gpio.h>
40#include <linux/mmc/slot-gpio.h>
41
42#include "dw_mmc.h"
43
44
45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
56#define DW_MCI_FREQ_MAX 200000000
57#define DW_MCI_FREQ_MIN 400000
58
59#ifdef CONFIG_MMC_DW_IDMAC
60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65struct idmac_desc_64addr {
66 u32 des0;
67
68 u32 des1;
69
70 u32 des2;
71#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74
75 u32 des3;
76
77 u32 des4;
78 u32 des5;
79
80 u32 des6;
81 u32 des7;
82};
83
84struct idmac_desc {
85 __le32 des0;
86#define IDMAC_DES0_DIC BIT(1)
87#define IDMAC_DES0_LD BIT(2)
88#define IDMAC_DES0_FD BIT(3)
89#define IDMAC_DES0_CH BIT(4)
90#define IDMAC_DES0_ER BIT(5)
91#define IDMAC_DES0_CES BIT(30)
92#define IDMAC_DES0_OWN BIT(31)
93
94 __le32 des1;
95#define IDMAC_SET_BUFFER1_SIZE(d, s) \
96 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
97
98 __le32 des2;
99
100 __le32 des3;
101};
102#endif
103
104static bool dw_mci_reset(struct dw_mci *host);
105static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
106static int dw_mci_card_busy(struct mmc_host *mmc);
107
108#if defined(CONFIG_DEBUG_FS)
109static int dw_mci_req_show(struct seq_file *s, void *v)
110{
111 struct dw_mci_slot *slot = s->private;
112 struct mmc_request *mrq;
113 struct mmc_command *cmd;
114 struct mmc_command *stop;
115 struct mmc_data *data;
116
117
118 spin_lock_bh(&slot->host->lock);
119 mrq = slot->mrq;
120
121 if (mrq) {
122 cmd = mrq->cmd;
123 data = mrq->data;
124 stop = mrq->stop;
125
126 if (cmd)
127 seq_printf(s,
128 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
129 cmd->opcode, cmd->arg, cmd->flags,
130 cmd->resp[0], cmd->resp[1], cmd->resp[2],
131 cmd->resp[2], cmd->error);
132 if (data)
133 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
134 data->bytes_xfered, data->blocks,
135 data->blksz, data->flags, data->error);
136 if (stop)
137 seq_printf(s,
138 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
139 stop->opcode, stop->arg, stop->flags,
140 stop->resp[0], stop->resp[1], stop->resp[2],
141 stop->resp[2], stop->error);
142 }
143
144 spin_unlock_bh(&slot->host->lock);
145
146 return 0;
147}
148
149static int dw_mci_req_open(struct inode *inode, struct file *file)
150{
151 return single_open(file, dw_mci_req_show, inode->i_private);
152}
153
154static const struct file_operations dw_mci_req_fops = {
155 .owner = THIS_MODULE,
156 .open = dw_mci_req_open,
157 .read = seq_read,
158 .llseek = seq_lseek,
159 .release = single_release,
160};
161
162static int dw_mci_regs_show(struct seq_file *s, void *v)
163{
164 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
165 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
166 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
167 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
168 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
169 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
170
171 return 0;
172}
173
174static int dw_mci_regs_open(struct inode *inode, struct file *file)
175{
176 return single_open(file, dw_mci_regs_show, inode->i_private);
177}
178
179static const struct file_operations dw_mci_regs_fops = {
180 .owner = THIS_MODULE,
181 .open = dw_mci_regs_open,
182 .read = seq_read,
183 .llseek = seq_lseek,
184 .release = single_release,
185};
186
187static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
188{
189 struct mmc_host *mmc = slot->mmc;
190 struct dw_mci *host = slot->host;
191 struct dentry *root;
192 struct dentry *node;
193
194 root = mmc->debugfs_root;
195 if (!root)
196 return;
197
198 node = debugfs_create_file("regs", S_IRUSR, root, host,
199 &dw_mci_regs_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_file("req", S_IRUSR, root, slot,
204 &dw_mci_req_fops);
205 if (!node)
206 goto err;
207
208 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("pending_events", S_IRUSR, root,
213 (u32 *)&host->pending_events);
214 if (!node)
215 goto err;
216
217 node = debugfs_create_x32("completed_events", S_IRUSR, root,
218 (u32 *)&host->completed_events);
219 if (!node)
220 goto err;
221
222 return;
223
224err:
225 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
226}
227#endif
228
229static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
230
231static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
232{
233 struct mmc_data *data;
234 struct dw_mci_slot *slot = mmc_priv(mmc);
235 struct dw_mci *host = slot->host;
236 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
237 u32 cmdr;
238 cmd->error = -EINPROGRESS;
239
240 cmdr = cmd->opcode;
241
242 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
243 cmd->opcode == MMC_GO_IDLE_STATE ||
244 cmd->opcode == MMC_GO_INACTIVE_STATE ||
245 (cmd->opcode == SD_IO_RW_DIRECT &&
246 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
247 cmdr |= SDMMC_CMD_STOP;
248 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
249 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
250
251 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
252 u32 clk_en_a;
253
254
255 cmdr |= SDMMC_CMD_VOLT_SWITCH;
256
257
258 WARN_ON(slot->host->state != STATE_SENDING_CMD);
259 slot->host->state = STATE_SENDING_CMD11;
260
261
262
263
264
265
266
267
268
269
270
271
272 clk_en_a = mci_readl(host, CLKENA);
273 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
274 mci_writel(host, CLKENA, clk_en_a);
275 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
276 SDMMC_CMD_PRV_DAT_WAIT, 0);
277 }
278
279 if (cmd->flags & MMC_RSP_PRESENT) {
280
281 cmdr |= SDMMC_CMD_RESP_EXP;
282 if (cmd->flags & MMC_RSP_136)
283 cmdr |= SDMMC_CMD_RESP_LONG;
284 }
285
286 if (cmd->flags & MMC_RSP_CRC)
287 cmdr |= SDMMC_CMD_RESP_CRC;
288
289 data = cmd->data;
290 if (data) {
291 cmdr |= SDMMC_CMD_DAT_EXP;
292 if (data->flags & MMC_DATA_STREAM)
293 cmdr |= SDMMC_CMD_STRM_MODE;
294 if (data->flags & MMC_DATA_WRITE)
295 cmdr |= SDMMC_CMD_DAT_WR;
296 }
297
298 if (drv_data && drv_data->prepare_command)
299 drv_data->prepare_command(slot->host, &cmdr);
300
301 return cmdr;
302}
303
304static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
305{
306 struct mmc_command *stop;
307 u32 cmdr;
308
309 if (!cmd->data)
310 return 0;
311
312 stop = &host->stop_abort;
313 cmdr = cmd->opcode;
314 memset(stop, 0, sizeof(struct mmc_command));
315
316 if (cmdr == MMC_READ_SINGLE_BLOCK ||
317 cmdr == MMC_READ_MULTIPLE_BLOCK ||
318 cmdr == MMC_WRITE_BLOCK ||
319 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
322 stop->opcode = MMC_STOP_TRANSMISSION;
323 stop->arg = 0;
324 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
325 } else if (cmdr == SD_IO_RW_EXTENDED) {
326 stop->opcode = SD_IO_RW_DIRECT;
327 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
328 ((cmd->arg >> 28) & 0x7);
329 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
330 } else {
331 return 0;
332 }
333
334 cmdr = stop->opcode | SDMMC_CMD_STOP |
335 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
336
337 return cmdr;
338}
339
340static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
341{
342 unsigned long timeout = jiffies + msecs_to_jiffies(500);
343
344
345
346
347
348
349
350
351
352 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
353 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
354 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
355 if (time_after(jiffies, timeout)) {
356
357 dev_err(host->dev, "Busy; trying anyway\n");
358 break;
359 }
360 udelay(10);
361 }
362 }
363}
364
365static void dw_mci_start_command(struct dw_mci *host,
366 struct mmc_command *cmd, u32 cmd_flags)
367{
368 host->cmd = cmd;
369 dev_vdbg(host->dev,
370 "start command: ARGR=0x%08x CMDR=0x%08x\n",
371 cmd->arg, cmd_flags);
372
373 mci_writel(host, CMDARG, cmd->arg);
374 wmb();
375 dw_mci_wait_while_busy(host, cmd_flags);
376
377 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
378}
379
380static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
381{
382 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
383 dw_mci_start_command(host, stop, host->stop_cmdr);
384}
385
386
387static void dw_mci_stop_dma(struct dw_mci *host)
388{
389 if (host->using_dma) {
390 host->dma_ops->stop(host);
391 host->dma_ops->cleanup(host);
392 }
393
394
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
396}
397
398static int dw_mci_get_dma_dir(struct mmc_data *data)
399{
400 if (data->flags & MMC_DATA_WRITE)
401 return DMA_TO_DEVICE;
402 else
403 return DMA_FROM_DEVICE;
404}
405
406#ifdef CONFIG_MMC_DW_IDMAC
407static void dw_mci_dma_cleanup(struct dw_mci *host)
408{
409 struct mmc_data *data = host->data;
410
411 if (data)
412 if (!data->host_cookie)
413 dma_unmap_sg(host->dev,
414 data->sg,
415 data->sg_len,
416 dw_mci_get_dma_dir(data));
417}
418
419static void dw_mci_idmac_reset(struct dw_mci *host)
420{
421 u32 bmod = mci_readl(host, BMOD);
422
423 bmod |= SDMMC_IDMAC_SWRESET;
424 mci_writel(host, BMOD, bmod);
425}
426
427static void dw_mci_idmac_stop_dma(struct dw_mci *host)
428{
429 u32 temp;
430
431
432 temp = mci_readl(host, CTRL);
433 temp &= ~SDMMC_CTRL_USE_IDMAC;
434 temp |= SDMMC_CTRL_DMA_RESET;
435 mci_writel(host, CTRL, temp);
436
437
438 temp = mci_readl(host, BMOD);
439 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
440 temp |= SDMMC_IDMAC_SWRESET;
441 mci_writel(host, BMOD, temp);
442}
443
444static void dw_mci_idmac_complete_dma(struct dw_mci *host)
445{
446 struct mmc_data *data = host->data;
447
448 dev_vdbg(host->dev, "DMA complete\n");
449
450 host->dma_ops->cleanup(host);
451
452
453
454
455
456 if (data) {
457 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
458 tasklet_schedule(&host->tasklet);
459 }
460}
461
462static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
463 unsigned int sg_len)
464{
465 int i;
466 if (host->dma_64bit_address == 1) {
467 struct idmac_desc_64addr *desc = host->sg_cpu;
468
469 for (i = 0; i < sg_len; i++, desc++) {
470 unsigned int length = sg_dma_len(&data->sg[i]);
471 u64 mem_addr = sg_dma_address(&data->sg[i]);
472
473
474
475
476
477 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
478 IDMAC_DES0_CH;
479
480 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
481
482
483 desc->des4 = mem_addr & 0xffffffff;
484 desc->des5 = mem_addr >> 32;
485 }
486
487
488 desc = host->sg_cpu;
489 desc->des0 |= IDMAC_DES0_FD;
490
491
492 desc = host->sg_cpu + (i - 1) *
493 sizeof(struct idmac_desc_64addr);
494 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
495 desc->des0 |= IDMAC_DES0_LD;
496
497 } else {
498 struct idmac_desc *desc = host->sg_cpu;
499
500 for (i = 0; i < sg_len; i++, desc++) {
501 unsigned int length = sg_dma_len(&data->sg[i]);
502 u32 mem_addr = sg_dma_address(&data->sg[i]);
503
504
505
506
507
508 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
509 IDMAC_DES0_DIC | IDMAC_DES0_CH);
510
511 IDMAC_SET_BUFFER1_SIZE(desc, length);
512
513
514 desc->des2 = cpu_to_le32(mem_addr);
515 }
516
517
518 desc = host->sg_cpu;
519 desc->des0 |= cpu_to_le32(IDMAC_DES0_FD);
520
521
522 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
523 desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC));
524 desc->des0 |= cpu_to_le32(IDMAC_DES0_LD);
525 }
526
527 wmb();
528}
529
530static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
531{
532 u32 temp;
533
534 dw_mci_translate_sglist(host, host->data, sg_len);
535
536
537 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
538 dw_mci_idmac_reset(host);
539
540
541 temp = mci_readl(host, CTRL);
542 temp |= SDMMC_CTRL_USE_IDMAC;
543 mci_writel(host, CTRL, temp);
544
545 wmb();
546
547
548 temp = mci_readl(host, BMOD);
549 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
550 mci_writel(host, BMOD, temp);
551
552
553 mci_writel(host, PLDMND, 1);
554}
555
556static int dw_mci_idmac_init(struct dw_mci *host)
557{
558 int i;
559
560 if (host->dma_64bit_address == 1) {
561 struct idmac_desc_64addr *p;
562
563 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
564
565
566 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
567 i++, p++) {
568 p->des6 = (host->sg_dma +
569 (sizeof(struct idmac_desc_64addr) *
570 (i + 1))) & 0xffffffff;
571
572 p->des7 = (u64)(host->sg_dma +
573 (sizeof(struct idmac_desc_64addr) *
574 (i + 1))) >> 32;
575
576 p->des1 = 0;
577 p->des2 = 0;
578 p->des3 = 0;
579 }
580
581
582 p->des6 = host->sg_dma & 0xffffffff;
583 p->des7 = (u64)host->sg_dma >> 32;
584 p->des0 = IDMAC_DES0_ER;
585
586 } else {
587 struct idmac_desc *p;
588
589 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
590
591
592 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
593 p->des3 = cpu_to_le32(host->sg_dma +
594 (sizeof(struct idmac_desc) * (i + 1)));
595 p->des1 = 0;
596 }
597
598
599 p->des3 = cpu_to_le32(host->sg_dma);
600 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
601 }
602
603 dw_mci_idmac_reset(host);
604
605 if (host->dma_64bit_address == 1) {
606
607 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
608 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
609 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
610
611
612 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
613 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
614
615 } else {
616
617 mci_writel(host, IDSTS, IDMAC_INT_CLR);
618 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
619 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
620
621
622 mci_writel(host, DBADDR, host->sg_dma);
623 }
624
625 return 0;
626}
627
628static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
629 .init = dw_mci_idmac_init,
630 .start = dw_mci_idmac_start_dma,
631 .stop = dw_mci_idmac_stop_dma,
632 .complete = dw_mci_idmac_complete_dma,
633 .cleanup = dw_mci_dma_cleanup,
634};
635#endif
636
637static int dw_mci_pre_dma_transfer(struct dw_mci *host,
638 struct mmc_data *data,
639 bool next)
640{
641 struct scatterlist *sg;
642 unsigned int i, sg_len;
643
644 if (!next && data->host_cookie)
645 return data->host_cookie;
646
647
648
649
650
651
652 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
653 return -EINVAL;
654
655 if (data->blksz & 3)
656 return -EINVAL;
657
658 for_each_sg(data->sg, sg, data->sg_len, i) {
659 if (sg->offset & 3 || sg->length & 3)
660 return -EINVAL;
661 }
662
663 sg_len = dma_map_sg(host->dev,
664 data->sg,
665 data->sg_len,
666 dw_mci_get_dma_dir(data));
667 if (sg_len == 0)
668 return -EINVAL;
669
670 if (next)
671 data->host_cookie = sg_len;
672
673 return sg_len;
674}
675
676static void dw_mci_pre_req(struct mmc_host *mmc,
677 struct mmc_request *mrq,
678 bool is_first_req)
679{
680 struct dw_mci_slot *slot = mmc_priv(mmc);
681 struct mmc_data *data = mrq->data;
682
683 if (!slot->host->use_dma || !data)
684 return;
685
686 if (data->host_cookie) {
687 data->host_cookie = 0;
688 return;
689 }
690
691 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
692 data->host_cookie = 0;
693}
694
695static void dw_mci_post_req(struct mmc_host *mmc,
696 struct mmc_request *mrq,
697 int err)
698{
699 struct dw_mci_slot *slot = mmc_priv(mmc);
700 struct mmc_data *data = mrq->data;
701
702 if (!slot->host->use_dma || !data)
703 return;
704
705 if (data->host_cookie)
706 dma_unmap_sg(slot->host->dev,
707 data->sg,
708 data->sg_len,
709 dw_mci_get_dma_dir(data));
710 data->host_cookie = 0;
711}
712
713static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
714{
715#ifdef CONFIG_MMC_DW_IDMAC
716 unsigned int blksz = data->blksz;
717 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
718 u32 fifo_width = 1 << host->data_shift;
719 u32 blksz_depth = blksz / fifo_width, fifoth_val;
720 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
721 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
722
723 tx_wmark = (host->fifo_depth) / 2;
724 tx_wmark_invers = host->fifo_depth - tx_wmark;
725
726
727
728
729
730 if (blksz % fifo_width) {
731 msize = 0;
732 rx_wmark = 1;
733 goto done;
734 }
735
736 do {
737 if (!((blksz_depth % mszs[idx]) ||
738 (tx_wmark_invers % mszs[idx]))) {
739 msize = idx;
740 rx_wmark = mszs[idx] - 1;
741 break;
742 }
743 } while (--idx > 0);
744
745
746
747
748done:
749 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
750 mci_writel(host, FIFOTH, fifoth_val);
751#endif
752}
753
754static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
755{
756 unsigned int blksz = data->blksz;
757 u32 blksz_depth, fifo_depth;
758 u16 thld_size;
759
760 WARN_ON(!(data->flags & MMC_DATA_READ));
761
762
763
764
765
766 if (host->verid < DW_MMC_240A)
767 return;
768
769 if (host->timing != MMC_TIMING_MMC_HS200 &&
770 host->timing != MMC_TIMING_MMC_HS400 &&
771 host->timing != MMC_TIMING_UHS_SDR104)
772 goto disable;
773
774 blksz_depth = blksz / (1 << host->data_shift);
775 fifo_depth = host->fifo_depth;
776
777 if (blksz_depth > fifo_depth)
778 goto disable;
779
780
781
782
783
784
785 thld_size = blksz;
786 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
787 return;
788
789disable:
790 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
791}
792
793static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
794{
795 unsigned long irqflags;
796 int sg_len;
797 u32 temp;
798
799 host->using_dma = 0;
800
801
802 if (!host->use_dma)
803 return -ENODEV;
804
805 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
806 if (sg_len < 0) {
807 host->dma_ops->stop(host);
808 return sg_len;
809 }
810
811 host->using_dma = 1;
812
813 dev_vdbg(host->dev,
814 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
815 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
816 sg_len);
817
818
819
820
821
822
823 if (host->prev_blksz != data->blksz)
824 dw_mci_adjust_fifoth(host, data);
825
826
827 temp = mci_readl(host, CTRL);
828 temp |= SDMMC_CTRL_DMA_ENABLE;
829 mci_writel(host, CTRL, temp);
830
831
832 spin_lock_irqsave(&host->irq_lock, irqflags);
833 temp = mci_readl(host, INTMASK);
834 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
835 mci_writel(host, INTMASK, temp);
836 spin_unlock_irqrestore(&host->irq_lock, irqflags);
837
838 host->dma_ops->start(host, sg_len);
839
840 return 0;
841}
842
843static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
844{
845 unsigned long irqflags;
846 u32 temp;
847
848 data->error = -EINPROGRESS;
849
850 WARN_ON(host->data);
851 host->sg = NULL;
852 host->data = data;
853
854 if (data->flags & MMC_DATA_READ) {
855 host->dir_status = DW_MCI_RECV_STATUS;
856 dw_mci_ctrl_rd_thld(host, data);
857 } else {
858 host->dir_status = DW_MCI_SEND_STATUS;
859 }
860
861 if (dw_mci_submit_data_dma(host, data)) {
862 int flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867
868 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
869 host->sg = data->sg;
870 host->part_buf_start = 0;
871 host->part_buf_count = 0;
872
873 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
874
875 spin_lock_irqsave(&host->irq_lock, irqflags);
876 temp = mci_readl(host, INTMASK);
877 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
878 mci_writel(host, INTMASK, temp);
879 spin_unlock_irqrestore(&host->irq_lock, irqflags);
880
881 temp = mci_readl(host, CTRL);
882 temp &= ~SDMMC_CTRL_DMA_ENABLE;
883 mci_writel(host, CTRL, temp);
884
885
886
887
888
889
890 mci_writel(host, FIFOTH, host->fifoth_val);
891 host->prev_blksz = 0;
892 } else {
893
894
895
896
897
898 host->prev_blksz = data->blksz;
899 }
900}
901
902static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
903{
904 struct dw_mci *host = slot->host;
905 unsigned long timeout = jiffies + msecs_to_jiffies(500);
906 unsigned int cmd_status = 0;
907
908 mci_writel(host, CMDARG, arg);
909 wmb();
910 dw_mci_wait_while_busy(host, cmd);
911 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
912
913 while (time_before(jiffies, timeout)) {
914 cmd_status = mci_readl(host, CMD);
915 if (!(cmd_status & SDMMC_CMD_START))
916 return;
917 }
918 dev_err(&slot->mmc->class_dev,
919 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
920 cmd, arg, cmd_status);
921}
922
923static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
924{
925 struct dw_mci *host = slot->host;
926 unsigned int clock = slot->clock;
927 u32 div;
928 u32 clk_en_a;
929 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
930
931
932 if (host->state == STATE_WAITING_CMD11_DONE)
933 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
934
935 if (!clock) {
936 mci_writel(host, CLKENA, 0);
937 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
938 } else if (clock != host->current_speed || force_clkinit) {
939 div = host->bus_hz / clock;
940 if (host->bus_hz % clock && host->bus_hz > clock)
941
942
943
944
945 div += 1;
946
947 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
948
949 if ((clock << div) != slot->__clk_old || force_clkinit)
950 dev_info(&slot->mmc->class_dev,
951 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
952 slot->id, host->bus_hz, clock,
953 div ? ((host->bus_hz / div) >> 1) :
954 host->bus_hz, div);
955
956
957 mci_writel(host, CLKENA, 0);
958 mci_writel(host, CLKSRC, 0);
959
960
961 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
962
963
964 mci_writel(host, CLKDIV, div);
965
966
967 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
968
969
970 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
971 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
972 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
973 mci_writel(host, CLKENA, clk_en_a);
974
975
976 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
977
978
979 slot->__clk_old = clock << div;
980 }
981
982 host->current_speed = clock;
983
984
985 mci_writel(host, CTYPE, (slot->ctype << slot->id));
986}
987
988static void __dw_mci_start_request(struct dw_mci *host,
989 struct dw_mci_slot *slot,
990 struct mmc_command *cmd)
991{
992 struct mmc_request *mrq;
993 struct mmc_data *data;
994 u32 cmdflags;
995
996 mrq = slot->mrq;
997
998 host->cur_slot = slot;
999 host->mrq = mrq;
1000
1001 host->pending_events = 0;
1002 host->completed_events = 0;
1003 host->cmd_status = 0;
1004 host->data_status = 0;
1005 host->dir_status = 0;
1006
1007 data = cmd->data;
1008 if (data) {
1009 mci_writel(host, TMOUT, 0xFFFFFFFF);
1010 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1011 mci_writel(host, BLKSIZ, data->blksz);
1012 }
1013
1014 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1015
1016
1017 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1018 cmdflags |= SDMMC_CMD_INIT;
1019
1020 if (data) {
1021 dw_mci_submit_data(host, data);
1022 wmb();
1023 }
1024
1025 dw_mci_start_command(host, cmd, cmdflags);
1026
1027 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1028 unsigned long irqflags;
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040 spin_lock_irqsave(&host->irq_lock, irqflags);
1041 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1042 mod_timer(&host->cmd11_timer,
1043 jiffies + msecs_to_jiffies(500) + 1);
1044 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1045 }
1046
1047 if (mrq->stop)
1048 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1049 else
1050 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1051}
1052
1053static void dw_mci_start_request(struct dw_mci *host,
1054 struct dw_mci_slot *slot)
1055{
1056 struct mmc_request *mrq = slot->mrq;
1057 struct mmc_command *cmd;
1058
1059 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1060 __dw_mci_start_request(host, slot, cmd);
1061}
1062
1063
1064static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1065 struct mmc_request *mrq)
1066{
1067 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1068 host->state);
1069
1070 slot->mrq = mrq;
1071
1072 if (host->state == STATE_WAITING_CMD11_DONE) {
1073 dev_warn(&slot->mmc->class_dev,
1074 "Voltage change didn't complete\n");
1075
1076
1077
1078
1079
1080 host->state = STATE_IDLE;
1081 }
1082
1083 if (host->state == STATE_IDLE) {
1084 host->state = STATE_SENDING_CMD;
1085 dw_mci_start_request(host, slot);
1086 } else {
1087 list_add_tail(&slot->queue_node, &host->queue);
1088 }
1089}
1090
1091static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1092{
1093 struct dw_mci_slot *slot = mmc_priv(mmc);
1094 struct dw_mci *host = slot->host;
1095
1096 WARN_ON(slot->mrq);
1097
1098
1099
1100
1101
1102
1103 spin_lock_bh(&host->lock);
1104
1105 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1106 spin_unlock_bh(&host->lock);
1107 mrq->cmd->error = -ENOMEDIUM;
1108 mmc_request_done(mmc, mrq);
1109 return;
1110 }
1111
1112 dw_mci_queue_request(host, slot, mrq);
1113
1114 spin_unlock_bh(&host->lock);
1115}
1116
1117static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1118{
1119 struct dw_mci_slot *slot = mmc_priv(mmc);
1120 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1121 u32 regs;
1122 int ret;
1123
1124 switch (ios->bus_width) {
1125 case MMC_BUS_WIDTH_4:
1126 slot->ctype = SDMMC_CTYPE_4BIT;
1127 break;
1128 case MMC_BUS_WIDTH_8:
1129 slot->ctype = SDMMC_CTYPE_8BIT;
1130 break;
1131 default:
1132
1133 slot->ctype = SDMMC_CTYPE_1BIT;
1134 }
1135
1136 regs = mci_readl(slot->host, UHS_REG);
1137
1138
1139 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1140 ios->timing == MMC_TIMING_MMC_HS400)
1141 regs |= ((0x1 << slot->id) << 16);
1142 else
1143 regs &= ~((0x1 << slot->id) << 16);
1144
1145 mci_writel(slot->host, UHS_REG, regs);
1146 slot->host->timing = ios->timing;
1147
1148
1149
1150
1151
1152 slot->clock = ios->clock;
1153
1154 if (drv_data && drv_data->set_ios)
1155 drv_data->set_ios(slot->host, ios);
1156
1157 switch (ios->power_mode) {
1158 case MMC_POWER_UP:
1159 if (!IS_ERR(mmc->supply.vmmc)) {
1160 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1161 ios->vdd);
1162 if (ret) {
1163 dev_err(slot->host->dev,
1164 "failed to enable vmmc regulator\n");
1165
1166 return;
1167 }
1168 }
1169 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1170 regs = mci_readl(slot->host, PWREN);
1171 regs |= (1 << slot->id);
1172 mci_writel(slot->host, PWREN, regs);
1173 break;
1174 case MMC_POWER_ON:
1175 if (!slot->host->vqmmc_enabled) {
1176 if (!IS_ERR(mmc->supply.vqmmc)) {
1177 ret = regulator_enable(mmc->supply.vqmmc);
1178 if (ret < 0)
1179 dev_err(slot->host->dev,
1180 "failed to enable vqmmc\n");
1181 else
1182 slot->host->vqmmc_enabled = true;
1183
1184 } else {
1185
1186 slot->host->vqmmc_enabled = true;
1187 }
1188
1189
1190 dw_mci_ctrl_reset(slot->host,
1191 SDMMC_CTRL_ALL_RESET_FLAGS);
1192 }
1193
1194
1195 dw_mci_setup_bus(slot, false);
1196
1197 break;
1198 case MMC_POWER_OFF:
1199
1200 dw_mci_setup_bus(slot, false);
1201
1202 if (!IS_ERR(mmc->supply.vmmc))
1203 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1204
1205 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1206 regulator_disable(mmc->supply.vqmmc);
1207 slot->host->vqmmc_enabled = false;
1208
1209 regs = mci_readl(slot->host, PWREN);
1210 regs &= ~(1 << slot->id);
1211 mci_writel(slot->host, PWREN, regs);
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1218 slot->host->state = STATE_IDLE;
1219}
1220
1221static int dw_mci_card_busy(struct mmc_host *mmc)
1222{
1223 struct dw_mci_slot *slot = mmc_priv(mmc);
1224 u32 status;
1225
1226
1227
1228
1229
1230 status = mci_readl(slot->host, STATUS);
1231
1232 return !!(status & SDMMC_STATUS_BUSY);
1233}
1234
1235static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1236{
1237 struct dw_mci_slot *slot = mmc_priv(mmc);
1238 struct dw_mci *host = slot->host;
1239 u32 uhs;
1240 u32 v18 = SDMMC_UHS_18V << slot->id;
1241 int min_uv, max_uv;
1242 int ret;
1243
1244
1245
1246
1247
1248
1249 uhs = mci_readl(host, UHS_REG);
1250 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1251 min_uv = 2700000;
1252 max_uv = 3600000;
1253 uhs &= ~v18;
1254 } else {
1255 min_uv = 1700000;
1256 max_uv = 1950000;
1257 uhs |= v18;
1258 }
1259 if (!IS_ERR(mmc->supply.vqmmc)) {
1260 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1261
1262 if (ret) {
1263 dev_dbg(&mmc->class_dev,
1264 "Regulator set error %d: %d - %d\n",
1265 ret, min_uv, max_uv);
1266 return ret;
1267 }
1268 }
1269 mci_writel(host, UHS_REG, uhs);
1270
1271 return 0;
1272}
1273
1274static int dw_mci_get_ro(struct mmc_host *mmc)
1275{
1276 int read_only;
1277 struct dw_mci_slot *slot = mmc_priv(mmc);
1278 int gpio_ro = mmc_gpio_get_ro(mmc);
1279
1280
1281 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1282 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1283 read_only = 0;
1284 else if (!IS_ERR_VALUE(gpio_ro))
1285 read_only = gpio_ro;
1286 else
1287 read_only =
1288 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1289
1290 dev_dbg(&mmc->class_dev, "card is %s\n",
1291 read_only ? "read-only" : "read-write");
1292
1293 return read_only;
1294}
1295
1296static int dw_mci_get_cd(struct mmc_host *mmc)
1297{
1298 int present;
1299 struct dw_mci_slot *slot = mmc_priv(mmc);
1300 struct dw_mci_board *brd = slot->host->pdata;
1301 struct dw_mci *host = slot->host;
1302 int gpio_cd = mmc_gpio_get_cd(mmc);
1303
1304
1305 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1306 (mmc->caps & MMC_CAP_NONREMOVABLE))
1307 present = 1;
1308 else if (!IS_ERR_VALUE(gpio_cd))
1309 present = gpio_cd;
1310 else
1311 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1312 == 0 ? 1 : 0;
1313
1314 spin_lock_bh(&host->lock);
1315 if (present) {
1316 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1317 dev_dbg(&mmc->class_dev, "card is present\n");
1318 } else {
1319 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1320 dev_dbg(&mmc->class_dev, "card is not present\n");
1321 }
1322 spin_unlock_bh(&host->lock);
1323
1324 return present;
1325}
1326
1327static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1328{
1329 struct dw_mci_slot *slot = mmc_priv(mmc);
1330 struct dw_mci *host = slot->host;
1331
1332
1333
1334
1335
1336
1337 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1338 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1339 u32 clk_en_a_old;
1340 u32 clk_en_a;
1341
1342 clk_en_a_old = mci_readl(host, CLKENA);
1343
1344 if (card->type == MMC_TYPE_SDIO ||
1345 card->type == MMC_TYPE_SD_COMBO) {
1346 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1347 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1348 } else {
1349 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1350 clk_en_a = clk_en_a_old | clken_low_pwr;
1351 }
1352
1353 if (clk_en_a != clk_en_a_old) {
1354 mci_writel(host, CLKENA, clk_en_a);
1355 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1356 SDMMC_CMD_PRV_DAT_WAIT, 0);
1357 }
1358 }
1359}
1360
1361static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1362{
1363 struct dw_mci_slot *slot = mmc_priv(mmc);
1364 struct dw_mci *host = slot->host;
1365 unsigned long irqflags;
1366 u32 int_mask;
1367
1368 spin_lock_irqsave(&host->irq_lock, irqflags);
1369
1370
1371 int_mask = mci_readl(host, INTMASK);
1372 if (enb)
1373 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1374 else
1375 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1376 mci_writel(host, INTMASK, int_mask);
1377
1378 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1379}
1380
1381static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1382{
1383 struct dw_mci_slot *slot = mmc_priv(mmc);
1384 struct dw_mci *host = slot->host;
1385 const struct dw_mci_drv_data *drv_data = host->drv_data;
1386 int err = -ENOSYS;
1387
1388 if (drv_data && drv_data->execute_tuning)
1389 err = drv_data->execute_tuning(slot);
1390 return err;
1391}
1392
1393static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1394{
1395 struct dw_mci_slot *slot = mmc_priv(mmc);
1396 struct dw_mci *host = slot->host;
1397 const struct dw_mci_drv_data *drv_data = host->drv_data;
1398
1399 if (drv_data && drv_data->prepare_hs400_tuning)
1400 return drv_data->prepare_hs400_tuning(host, ios);
1401
1402 return 0;
1403}
1404
1405static const struct mmc_host_ops dw_mci_ops = {
1406 .request = dw_mci_request,
1407 .pre_req = dw_mci_pre_req,
1408 .post_req = dw_mci_post_req,
1409 .set_ios = dw_mci_set_ios,
1410 .get_ro = dw_mci_get_ro,
1411 .get_cd = dw_mci_get_cd,
1412 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1413 .execute_tuning = dw_mci_execute_tuning,
1414 .card_busy = dw_mci_card_busy,
1415 .start_signal_voltage_switch = dw_mci_switch_voltage,
1416 .init_card = dw_mci_init_card,
1417 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1418};
1419
1420static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1421 __releases(&host->lock)
1422 __acquires(&host->lock)
1423{
1424 struct dw_mci_slot *slot;
1425 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1426
1427 WARN_ON(host->cmd || host->data);
1428
1429 host->cur_slot->mrq = NULL;
1430 host->mrq = NULL;
1431 if (!list_empty(&host->queue)) {
1432 slot = list_entry(host->queue.next,
1433 struct dw_mci_slot, queue_node);
1434 list_del(&slot->queue_node);
1435 dev_vdbg(host->dev, "list not empty: %s is next\n",
1436 mmc_hostname(slot->mmc));
1437 host->state = STATE_SENDING_CMD;
1438 dw_mci_start_request(host, slot);
1439 } else {
1440 dev_vdbg(host->dev, "list empty\n");
1441
1442 if (host->state == STATE_SENDING_CMD11)
1443 host->state = STATE_WAITING_CMD11_DONE;
1444 else
1445 host->state = STATE_IDLE;
1446 }
1447
1448 spin_unlock(&host->lock);
1449 mmc_request_done(prev_mmc, mrq);
1450 spin_lock(&host->lock);
1451}
1452
1453static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1454{
1455 u32 status = host->cmd_status;
1456
1457 host->cmd_status = 0;
1458
1459
1460 if (cmd->flags & MMC_RSP_PRESENT) {
1461 if (cmd->flags & MMC_RSP_136) {
1462 cmd->resp[3] = mci_readl(host, RESP0);
1463 cmd->resp[2] = mci_readl(host, RESP1);
1464 cmd->resp[1] = mci_readl(host, RESP2);
1465 cmd->resp[0] = mci_readl(host, RESP3);
1466 } else {
1467 cmd->resp[0] = mci_readl(host, RESP0);
1468 cmd->resp[1] = 0;
1469 cmd->resp[2] = 0;
1470 cmd->resp[3] = 0;
1471 }
1472 }
1473
1474 if (status & SDMMC_INT_RTO)
1475 cmd->error = -ETIMEDOUT;
1476 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1477 cmd->error = -EILSEQ;
1478 else if (status & SDMMC_INT_RESP_ERR)
1479 cmd->error = -EIO;
1480 else
1481 cmd->error = 0;
1482
1483 if (cmd->error) {
1484
1485 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1486 mdelay(20);
1487 }
1488
1489 return cmd->error;
1490}
1491
1492static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1493{
1494 u32 status = host->data_status;
1495
1496 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1497 if (status & SDMMC_INT_DRTO) {
1498 data->error = -ETIMEDOUT;
1499 } else if (status & SDMMC_INT_DCRC) {
1500 data->error = -EILSEQ;
1501 } else if (status & SDMMC_INT_EBE) {
1502 if (host->dir_status ==
1503 DW_MCI_SEND_STATUS) {
1504
1505
1506
1507
1508
1509 data->bytes_xfered = 0;
1510 data->error = -ETIMEDOUT;
1511 } else if (host->dir_status ==
1512 DW_MCI_RECV_STATUS) {
1513 data->error = -EIO;
1514 }
1515 } else {
1516
1517 data->error = -EIO;
1518 }
1519
1520 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1521
1522
1523
1524
1525
1526 dw_mci_reset(host);
1527 } else {
1528 data->bytes_xfered = data->blocks * data->blksz;
1529 data->error = 0;
1530 }
1531
1532 return data->error;
1533}
1534
1535static void dw_mci_tasklet_func(unsigned long priv)
1536{
1537 struct dw_mci *host = (struct dw_mci *)priv;
1538 struct mmc_data *data;
1539 struct mmc_command *cmd;
1540 struct mmc_request *mrq;
1541 enum dw_mci_state state;
1542 enum dw_mci_state prev_state;
1543 unsigned int err;
1544
1545 spin_lock(&host->lock);
1546
1547 state = host->state;
1548 data = host->data;
1549 mrq = host->mrq;
1550
1551 do {
1552 prev_state = state;
1553
1554 switch (state) {
1555 case STATE_IDLE:
1556 case STATE_WAITING_CMD11_DONE:
1557 break;
1558
1559 case STATE_SENDING_CMD11:
1560 case STATE_SENDING_CMD:
1561 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1562 &host->pending_events))
1563 break;
1564
1565 cmd = host->cmd;
1566 host->cmd = NULL;
1567 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1568 err = dw_mci_command_complete(host, cmd);
1569 if (cmd == mrq->sbc && !err) {
1570 prev_state = state = STATE_SENDING_CMD;
1571 __dw_mci_start_request(host, host->cur_slot,
1572 mrq->cmd);
1573 goto unlock;
1574 }
1575
1576 if (cmd->data && err) {
1577 dw_mci_stop_dma(host);
1578 send_stop_abort(host, data);
1579 state = STATE_SENDING_STOP;
1580 break;
1581 }
1582
1583 if (!cmd->data || err) {
1584 dw_mci_request_end(host, mrq);
1585 goto unlock;
1586 }
1587
1588 prev_state = state = STATE_SENDING_DATA;
1589
1590
1591 case STATE_SENDING_DATA:
1592
1593
1594
1595
1596
1597
1598
1599
1600 if (test_and_clear_bit(EVENT_DATA_ERROR,
1601 &host->pending_events)) {
1602 dw_mci_stop_dma(host);
1603 if (data->stop ||
1604 !(host->data_status & (SDMMC_INT_DRTO |
1605 SDMMC_INT_EBE)))
1606 send_stop_abort(host, data);
1607 state = STATE_DATA_ERROR;
1608 break;
1609 }
1610
1611 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1612 &host->pending_events))
1613 break;
1614
1615 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630 if (test_and_clear_bit(EVENT_DATA_ERROR,
1631 &host->pending_events)) {
1632 dw_mci_stop_dma(host);
1633 if (data->stop ||
1634 !(host->data_status & (SDMMC_INT_DRTO |
1635 SDMMC_INT_EBE)))
1636 send_stop_abort(host, data);
1637 state = STATE_DATA_ERROR;
1638 break;
1639 }
1640 prev_state = state = STATE_DATA_BUSY;
1641
1642
1643
1644 case STATE_DATA_BUSY:
1645 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1646 &host->pending_events))
1647 break;
1648
1649 host->data = NULL;
1650 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1651 err = dw_mci_data_complete(host, data);
1652
1653 if (!err) {
1654 if (!data->stop || mrq->sbc) {
1655 if (mrq->sbc && data->stop)
1656 data->stop->error = 0;
1657 dw_mci_request_end(host, mrq);
1658 goto unlock;
1659 }
1660
1661
1662 if (data->stop)
1663 send_stop_abort(host, data);
1664 } else {
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674 if (!test_bit(EVENT_CMD_COMPLETE,
1675 &host->pending_events)) {
1676 host->cmd = NULL;
1677 dw_mci_request_end(host, mrq);
1678 goto unlock;
1679 }
1680 }
1681
1682
1683
1684
1685
1686 prev_state = state = STATE_SENDING_STOP;
1687
1688
1689
1690 case STATE_SENDING_STOP:
1691 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1692 &host->pending_events))
1693 break;
1694
1695
1696 if (mrq->cmd->error && mrq->data)
1697 dw_mci_reset(host);
1698
1699 host->cmd = NULL;
1700 host->data = NULL;
1701
1702 if (mrq->stop)
1703 dw_mci_command_complete(host, mrq->stop);
1704 else
1705 host->cmd_status = 0;
1706
1707 dw_mci_request_end(host, mrq);
1708 goto unlock;
1709
1710 case STATE_DATA_ERROR:
1711 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1712 &host->pending_events))
1713 break;
1714
1715 state = STATE_DATA_BUSY;
1716 break;
1717 }
1718 } while (state != prev_state);
1719
1720 host->state = state;
1721unlock:
1722 spin_unlock(&host->lock);
1723
1724}
1725
1726
1727static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1728{
1729 memcpy((void *)&host->part_buf, buf, cnt);
1730 host->part_buf_count = cnt;
1731}
1732
1733
1734static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1735{
1736 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1737 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1738 host->part_buf_count += cnt;
1739 return cnt;
1740}
1741
1742
1743static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1744{
1745 cnt = min(cnt, (int)host->part_buf_count);
1746 if (cnt) {
1747 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1748 cnt);
1749 host->part_buf_count -= cnt;
1750 host->part_buf_start += cnt;
1751 }
1752 return cnt;
1753}
1754
1755
1756static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1757{
1758 memcpy(buf, &host->part_buf, cnt);
1759 host->part_buf_start = cnt;
1760 host->part_buf_count = (1 << host->data_shift) - cnt;
1761}
1762
1763static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1764{
1765 struct mmc_data *data = host->data;
1766 int init_cnt = cnt;
1767
1768
1769 if (unlikely(host->part_buf_count)) {
1770 int len = dw_mci_push_part_bytes(host, buf, cnt);
1771 buf += len;
1772 cnt -= len;
1773 if (host->part_buf_count == 2) {
1774 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1775 host->part_buf_count = 0;
1776 }
1777 }
1778#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1779 if (unlikely((unsigned long)buf & 0x1)) {
1780 while (cnt >= 2) {
1781 u16 aligned_buf[64];
1782 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1783 int items = len >> 1;
1784 int i;
1785
1786 memcpy(aligned_buf, buf, len);
1787 buf += len;
1788 cnt -= len;
1789
1790 for (i = 0; i < items; ++i)
1791 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
1792 }
1793 } else
1794#endif
1795 {
1796 u16 *pdata = buf;
1797 for (; cnt >= 2; cnt -= 2)
1798 mci_fifo_writew(host->fifo_reg, *pdata++);
1799 buf = pdata;
1800 }
1801
1802 if (cnt) {
1803 dw_mci_set_part_bytes(host, buf, cnt);
1804
1805 if ((data->bytes_xfered + init_cnt) ==
1806 (data->blksz * data->blocks))
1807 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1808 }
1809}
1810
1811static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1812{
1813#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1814 if (unlikely((unsigned long)buf & 0x1)) {
1815 while (cnt >= 2) {
1816
1817 u16 aligned_buf[64];
1818 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1819 int items = len >> 1;
1820 int i;
1821 for (i = 0; i < items; ++i)
1822 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
1823
1824 memcpy(buf, aligned_buf, len);
1825 buf += len;
1826 cnt -= len;
1827 }
1828 } else
1829#endif
1830 {
1831 u16 *pdata = buf;
1832 for (; cnt >= 2; cnt -= 2)
1833 *pdata++ = mci_fifo_readw(host->fifo_reg);
1834 buf = pdata;
1835 }
1836 if (cnt) {
1837 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
1838 dw_mci_pull_final_bytes(host, buf, cnt);
1839 }
1840}
1841
1842static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1843{
1844 struct mmc_data *data = host->data;
1845 int init_cnt = cnt;
1846
1847
1848 if (unlikely(host->part_buf_count)) {
1849 int len = dw_mci_push_part_bytes(host, buf, cnt);
1850 buf += len;
1851 cnt -= len;
1852 if (host->part_buf_count == 4) {
1853 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1854 host->part_buf_count = 0;
1855 }
1856 }
1857#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1858 if (unlikely((unsigned long)buf & 0x3)) {
1859 while (cnt >= 4) {
1860 u32 aligned_buf[32];
1861 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1862 int items = len >> 2;
1863 int i;
1864
1865 memcpy(aligned_buf, buf, len);
1866 buf += len;
1867 cnt -= len;
1868
1869 for (i = 0; i < items; ++i)
1870 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
1871 }
1872 } else
1873#endif
1874 {
1875 u32 *pdata = buf;
1876 for (; cnt >= 4; cnt -= 4)
1877 mci_fifo_writel(host->fifo_reg, *pdata++);
1878 buf = pdata;
1879 }
1880
1881 if (cnt) {
1882 dw_mci_set_part_bytes(host, buf, cnt);
1883
1884 if ((data->bytes_xfered + init_cnt) ==
1885 (data->blksz * data->blocks))
1886 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1887 }
1888}
1889
1890static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1891{
1892#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1893 if (unlikely((unsigned long)buf & 0x3)) {
1894 while (cnt >= 4) {
1895
1896 u32 aligned_buf[32];
1897 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1898 int items = len >> 2;
1899 int i;
1900 for (i = 0; i < items; ++i)
1901 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
1902
1903 memcpy(buf, aligned_buf, len);
1904 buf += len;
1905 cnt -= len;
1906 }
1907 } else
1908#endif
1909 {
1910 u32 *pdata = buf;
1911 for (; cnt >= 4; cnt -= 4)
1912 *pdata++ = mci_fifo_readl(host->fifo_reg);
1913 buf = pdata;
1914 }
1915 if (cnt) {
1916 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
1917 dw_mci_pull_final_bytes(host, buf, cnt);
1918 }
1919}
1920
1921static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1922{
1923 struct mmc_data *data = host->data;
1924 int init_cnt = cnt;
1925
1926
1927 if (unlikely(host->part_buf_count)) {
1928 int len = dw_mci_push_part_bytes(host, buf, cnt);
1929 buf += len;
1930 cnt -= len;
1931
1932 if (host->part_buf_count == 8) {
1933 mci_fifo_writeq(host->fifo_reg, host->part_buf);
1934 host->part_buf_count = 0;
1935 }
1936 }
1937#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1938 if (unlikely((unsigned long)buf & 0x7)) {
1939 while (cnt >= 8) {
1940 u64 aligned_buf[16];
1941 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1942 int items = len >> 3;
1943 int i;
1944
1945 memcpy(aligned_buf, buf, len);
1946 buf += len;
1947 cnt -= len;
1948
1949 for (i = 0; i < items; ++i)
1950 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
1951 }
1952 } else
1953#endif
1954 {
1955 u64 *pdata = buf;
1956 for (; cnt >= 8; cnt -= 8)
1957 mci_fifo_writeq(host->fifo_reg, *pdata++);
1958 buf = pdata;
1959 }
1960
1961 if (cnt) {
1962 dw_mci_set_part_bytes(host, buf, cnt);
1963
1964 if ((data->bytes_xfered + init_cnt) ==
1965 (data->blksz * data->blocks))
1966 mci_fifo_writeq(host->fifo_reg, host->part_buf);
1967 }
1968}
1969
1970static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1971{
1972#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1973 if (unlikely((unsigned long)buf & 0x7)) {
1974 while (cnt >= 8) {
1975
1976 u64 aligned_buf[16];
1977 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1978 int items = len >> 3;
1979 int i;
1980 for (i = 0; i < items; ++i)
1981 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
1982
1983
1984 memcpy(buf, aligned_buf, len);
1985 buf += len;
1986 cnt -= len;
1987 }
1988 } else
1989#endif
1990 {
1991 u64 *pdata = buf;
1992 for (; cnt >= 8; cnt -= 8)
1993 *pdata++ = mci_fifo_readq(host->fifo_reg);
1994 buf = pdata;
1995 }
1996 if (cnt) {
1997 host->part_buf = mci_fifo_readq(host->fifo_reg);
1998 dw_mci_pull_final_bytes(host, buf, cnt);
1999 }
2000}
2001
2002static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2003{
2004 int len;
2005
2006
2007 len = dw_mci_pull_part_bytes(host, buf, cnt);
2008 if (unlikely(len == cnt))
2009 return;
2010 buf += len;
2011 cnt -= len;
2012
2013
2014 host->pull_data(host, buf, cnt);
2015}
2016
2017static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2018{
2019 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2020 void *buf;
2021 unsigned int offset;
2022 struct mmc_data *data = host->data;
2023 int shift = host->data_shift;
2024 u32 status;
2025 unsigned int len;
2026 unsigned int remain, fcnt;
2027
2028 do {
2029 if (!sg_miter_next(sg_miter))
2030 goto done;
2031
2032 host->sg = sg_miter->piter.sg;
2033 buf = sg_miter->addr;
2034 remain = sg_miter->length;
2035 offset = 0;
2036
2037 do {
2038 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2039 << shift) + host->part_buf_count;
2040 len = min(remain, fcnt);
2041 if (!len)
2042 break;
2043 dw_mci_pull_data(host, (void *)(buf + offset), len);
2044 data->bytes_xfered += len;
2045 offset += len;
2046 remain -= len;
2047 } while (remain);
2048
2049 sg_miter->consumed = offset;
2050 status = mci_readl(host, MINTSTS);
2051 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2052
2053 } while ((status & SDMMC_INT_RXDR) ||
2054 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2055
2056 if (!remain) {
2057 if (!sg_miter_next(sg_miter))
2058 goto done;
2059 sg_miter->consumed = 0;
2060 }
2061 sg_miter_stop(sg_miter);
2062 return;
2063
2064done:
2065 sg_miter_stop(sg_miter);
2066 host->sg = NULL;
2067 smp_wmb();
2068 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2069}
2070
2071static void dw_mci_write_data_pio(struct dw_mci *host)
2072{
2073 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2074 void *buf;
2075 unsigned int offset;
2076 struct mmc_data *data = host->data;
2077 int shift = host->data_shift;
2078 u32 status;
2079 unsigned int len;
2080 unsigned int fifo_depth = host->fifo_depth;
2081 unsigned int remain, fcnt;
2082
2083 do {
2084 if (!sg_miter_next(sg_miter))
2085 goto done;
2086
2087 host->sg = sg_miter->piter.sg;
2088 buf = sg_miter->addr;
2089 remain = sg_miter->length;
2090 offset = 0;
2091
2092 do {
2093 fcnt = ((fifo_depth -
2094 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2095 << shift) - host->part_buf_count;
2096 len = min(remain, fcnt);
2097 if (!len)
2098 break;
2099 host->push_data(host, (void *)(buf + offset), len);
2100 data->bytes_xfered += len;
2101 offset += len;
2102 remain -= len;
2103 } while (remain);
2104
2105 sg_miter->consumed = offset;
2106 status = mci_readl(host, MINTSTS);
2107 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2108 } while (status & SDMMC_INT_TXDR);
2109
2110 if (!remain) {
2111 if (!sg_miter_next(sg_miter))
2112 goto done;
2113 sg_miter->consumed = 0;
2114 }
2115 sg_miter_stop(sg_miter);
2116 return;
2117
2118done:
2119 sg_miter_stop(sg_miter);
2120 host->sg = NULL;
2121 smp_wmb();
2122 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2123}
2124
2125static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2126{
2127 if (!host->cmd_status)
2128 host->cmd_status = status;
2129
2130 smp_wmb();
2131
2132 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2133 tasklet_schedule(&host->tasklet);
2134}
2135
2136static void dw_mci_handle_cd(struct dw_mci *host)
2137{
2138 int i;
2139
2140 for (i = 0; i < host->num_slots; i++) {
2141 struct dw_mci_slot *slot = host->slot[i];
2142
2143 if (!slot)
2144 continue;
2145
2146 if (slot->mmc->ops->card_event)
2147 slot->mmc->ops->card_event(slot->mmc);
2148 mmc_detect_change(slot->mmc,
2149 msecs_to_jiffies(host->pdata->detect_delay_ms));
2150 }
2151}
2152
2153static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2154{
2155 struct dw_mci *host = dev_id;
2156 u32 pending;
2157 int i;
2158
2159 pending = mci_readl(host, MINTSTS);
2160
2161
2162
2163
2164
2165 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2166 if (!pending &&
2167 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2168 pending |= SDMMC_INT_DATA_OVER;
2169 }
2170
2171 if (pending) {
2172
2173 if ((host->state == STATE_SENDING_CMD11) &&
2174 (pending & SDMMC_INT_VOLT_SWITCH)) {
2175 unsigned long irqflags;
2176
2177 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2178 pending &= ~SDMMC_INT_VOLT_SWITCH;
2179
2180
2181
2182
2183
2184 spin_lock_irqsave(&host->irq_lock, irqflags);
2185 dw_mci_cmd_interrupt(host, pending);
2186 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2187
2188 del_timer(&host->cmd11_timer);
2189 }
2190
2191 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2192 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2193 host->cmd_status = pending;
2194 smp_wmb();
2195 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2196 }
2197
2198 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2199
2200 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2201 host->data_status = pending;
2202 smp_wmb();
2203 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2204 tasklet_schedule(&host->tasklet);
2205 }
2206
2207 if (pending & SDMMC_INT_DATA_OVER) {
2208 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2209 if (!host->data_status)
2210 host->data_status = pending;
2211 smp_wmb();
2212 if (host->dir_status == DW_MCI_RECV_STATUS) {
2213 if (host->sg != NULL)
2214 dw_mci_read_data_pio(host, true);
2215 }
2216 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2217 tasklet_schedule(&host->tasklet);
2218 }
2219
2220 if (pending & SDMMC_INT_RXDR) {
2221 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2222 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2223 dw_mci_read_data_pio(host, false);
2224 }
2225
2226 if (pending & SDMMC_INT_TXDR) {
2227 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2228 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2229 dw_mci_write_data_pio(host);
2230 }
2231
2232 if (pending & SDMMC_INT_CMD_DONE) {
2233 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2234 dw_mci_cmd_interrupt(host, pending);
2235 }
2236
2237 if (pending & SDMMC_INT_CD) {
2238 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2239 dw_mci_handle_cd(host);
2240 }
2241
2242
2243 for (i = 0; i < host->num_slots; i++) {
2244 struct dw_mci_slot *slot = host->slot[i];
2245
2246 if (!slot)
2247 continue;
2248
2249 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2250 mci_writel(host, RINTSTS,
2251 SDMMC_INT_SDIO(slot->sdio_id));
2252 mmc_signal_sdio_irq(slot->mmc);
2253 }
2254 }
2255
2256 }
2257
2258#ifdef CONFIG_MMC_DW_IDMAC
2259
2260 if (host->dma_64bit_address == 1) {
2261 pending = mci_readl(host, IDSTS64);
2262 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2263 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2264 SDMMC_IDMAC_INT_RI);
2265 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2266 host->dma_ops->complete(host);
2267 }
2268 } else {
2269 pending = mci_readl(host, IDSTS);
2270 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2271 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2272 SDMMC_IDMAC_INT_RI);
2273 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2274 host->dma_ops->complete(host);
2275 }
2276 }
2277#endif
2278
2279 return IRQ_HANDLED;
2280}
2281
2282#ifdef CONFIG_OF
2283
2284static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2285{
2286 struct device_node *np;
2287 const __be32 *addr;
2288 int len;
2289
2290 if (!dev || !dev->of_node)
2291 return NULL;
2292
2293 for_each_child_of_node(dev->of_node, np) {
2294 addr = of_get_property(np, "reg", &len);
2295 if (!addr || (len < sizeof(int)))
2296 continue;
2297 if (be32_to_cpup(addr) == slot)
2298 return np;
2299 }
2300 return NULL;
2301}
2302
2303static struct dw_mci_of_slot_quirks {
2304 char *quirk;
2305 int id;
2306} of_slot_quirks[] = {
2307 {
2308 .quirk = "disable-wp",
2309 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2310 },
2311};
2312
2313static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2314{
2315 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2316 int quirks = 0;
2317 int idx;
2318
2319
2320 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2321 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2322 dev_warn(dev, "Slot quirk %s is deprecated\n",
2323 of_slot_quirks[idx].quirk);
2324 quirks |= of_slot_quirks[idx].id;
2325 }
2326
2327 return quirks;
2328}
2329#else
2330static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2331{
2332 return 0;
2333}
2334#endif
2335
2336static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2337{
2338 struct mmc_host *mmc;
2339 struct dw_mci_slot *slot;
2340 const struct dw_mci_drv_data *drv_data = host->drv_data;
2341 int ctrl_id, ret;
2342 u32 freq[2];
2343
2344 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2345 if (!mmc)
2346 return -ENOMEM;
2347
2348 slot = mmc_priv(mmc);
2349 slot->id = id;
2350 slot->sdio_id = host->sdio_id0 + id;
2351 slot->mmc = mmc;
2352 slot->host = host;
2353 host->slot[id] = slot;
2354
2355 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2356
2357 mmc->ops = &dw_mci_ops;
2358 if (of_property_read_u32_array(host->dev->of_node,
2359 "clock-freq-min-max", freq, 2)) {
2360 mmc->f_min = DW_MCI_FREQ_MIN;
2361 mmc->f_max = DW_MCI_FREQ_MAX;
2362 } else {
2363 mmc->f_min = freq[0];
2364 mmc->f_max = freq[1];
2365 }
2366
2367
2368 ret = mmc_regulator_get_supply(mmc);
2369 if (ret == -EPROBE_DEFER)
2370 goto err_host_allocated;
2371
2372 if (!mmc->ocr_avail)
2373 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2374
2375 if (host->pdata->caps)
2376 mmc->caps = host->pdata->caps;
2377
2378 if (host->pdata->pm_caps)
2379 mmc->pm_caps = host->pdata->pm_caps;
2380
2381 if (host->dev->of_node) {
2382 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2383 if (ctrl_id < 0)
2384 ctrl_id = 0;
2385 } else {
2386 ctrl_id = to_platform_device(host->dev)->id;
2387 }
2388 if (drv_data && drv_data->caps)
2389 mmc->caps |= drv_data->caps[ctrl_id];
2390
2391 if (host->pdata->caps2)
2392 mmc->caps2 = host->pdata->caps2;
2393
2394 ret = mmc_of_parse(mmc);
2395 if (ret)
2396 goto err_host_allocated;
2397
2398 if (host->pdata->blk_settings) {
2399 mmc->max_segs = host->pdata->blk_settings->max_segs;
2400 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2401 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2402 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2403 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2404 } else {
2405
2406#ifdef CONFIG_MMC_DW_IDMAC
2407 mmc->max_segs = host->ring_size;
2408 mmc->max_blk_size = 65536;
2409 mmc->max_seg_size = 0x1000;
2410 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2411 mmc->max_blk_count = mmc->max_req_size / 512;
2412#else
2413 mmc->max_segs = 64;
2414 mmc->max_blk_size = 65536;
2415 mmc->max_blk_count = 512;
2416 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2417 mmc->max_seg_size = mmc->max_req_size;
2418#endif
2419 }
2420
2421 if (dw_mci_get_cd(mmc))
2422 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2423 else
2424 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2425
2426 ret = mmc_add_host(mmc);
2427 if (ret)
2428 goto err_host_allocated;
2429
2430#if defined(CONFIG_DEBUG_FS)
2431 dw_mci_init_debugfs(slot);
2432#endif
2433
2434 return 0;
2435
2436err_host_allocated:
2437 mmc_free_host(mmc);
2438 return ret;
2439}
2440
2441static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2442{
2443
2444 mmc_remove_host(slot->mmc);
2445 slot->host->slot[id] = NULL;
2446 mmc_free_host(slot->mmc);
2447}
2448
2449static void dw_mci_init_dma(struct dw_mci *host)
2450{
2451 int addr_config;
2452
2453 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2454
2455 if (addr_config == 1) {
2456
2457 host->dma_64bit_address = 1;
2458 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2459 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2460 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2461 } else {
2462
2463 host->dma_64bit_address = 0;
2464 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2465 }
2466
2467
2468 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2469 &host->sg_dma, GFP_KERNEL);
2470 if (!host->sg_cpu) {
2471 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2472 __func__);
2473 goto no_dma;
2474 }
2475
2476
2477#ifdef CONFIG_MMC_DW_IDMAC
2478 host->dma_ops = &dw_mci_idmac_ops;
2479 dev_info(host->dev, "Using internal DMA controller.\n");
2480#endif
2481
2482 if (!host->dma_ops)
2483 goto no_dma;
2484
2485 if (host->dma_ops->init && host->dma_ops->start &&
2486 host->dma_ops->stop && host->dma_ops->cleanup) {
2487 if (host->dma_ops->init(host)) {
2488 dev_err(host->dev, "%s: Unable to initialize "
2489 "DMA Controller.\n", __func__);
2490 goto no_dma;
2491 }
2492 } else {
2493 dev_err(host->dev, "DMA initialization not found.\n");
2494 goto no_dma;
2495 }
2496
2497 host->use_dma = 1;
2498 return;
2499
2500no_dma:
2501 dev_info(host->dev, "Using PIO mode.\n");
2502 host->use_dma = 0;
2503 return;
2504}
2505
2506static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2507{
2508 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2509 u32 ctrl;
2510
2511 ctrl = mci_readl(host, CTRL);
2512 ctrl |= reset;
2513 mci_writel(host, CTRL, ctrl);
2514
2515
2516 do {
2517 ctrl = mci_readl(host, CTRL);
2518 if (!(ctrl & reset))
2519 return true;
2520 } while (time_before(jiffies, timeout));
2521
2522 dev_err(host->dev,
2523 "Timeout resetting block (ctrl reset %#x)\n",
2524 ctrl & reset);
2525
2526 return false;
2527}
2528
2529static bool dw_mci_reset(struct dw_mci *host)
2530{
2531 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2532 bool ret = false;
2533
2534
2535
2536
2537
2538 if (host->sg) {
2539 sg_miter_stop(&host->sg_miter);
2540 host->sg = NULL;
2541 }
2542
2543 if (host->use_dma)
2544 flags |= SDMMC_CTRL_DMA_RESET;
2545
2546 if (dw_mci_ctrl_reset(host, flags)) {
2547
2548
2549
2550
2551 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2552
2553
2554 if (host->use_dma) {
2555 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2556 u32 status;
2557 do {
2558 status = mci_readl(host, STATUS);
2559 if (!(status & SDMMC_STATUS_DMA_REQ))
2560 break;
2561 cpu_relax();
2562 } while (time_before(jiffies, timeout));
2563
2564 if (status & SDMMC_STATUS_DMA_REQ) {
2565 dev_err(host->dev,
2566 "%s: Timeout waiting for dma_req to "
2567 "clear during reset\n", __func__);
2568 goto ciu_out;
2569 }
2570
2571
2572 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2573 goto ciu_out;
2574 }
2575 } else {
2576
2577 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2578 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2579 "clear but ciu was reset, doing clock update\n",
2580 __func__);
2581 goto ciu_out;
2582 }
2583 }
2584
2585#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2586
2587 dw_mci_idmac_reset(host);
2588#endif
2589
2590 ret = true;
2591
2592ciu_out:
2593
2594 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2595
2596 return ret;
2597}
2598
2599static void dw_mci_cmd11_timer(unsigned long arg)
2600{
2601 struct dw_mci *host = (struct dw_mci *)arg;
2602
2603 if (host->state != STATE_SENDING_CMD11) {
2604 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2605 return;
2606 }
2607
2608 host->cmd_status = SDMMC_INT_RTO;
2609 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2610 tasklet_schedule(&host->tasklet);
2611}
2612
2613#ifdef CONFIG_OF
2614static struct dw_mci_of_quirks {
2615 char *quirk;
2616 int id;
2617} of_quirks[] = {
2618 {
2619 .quirk = "broken-cd",
2620 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2621 }, {
2622 .quirk = "disable-wp",
2623 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2624 },
2625};
2626
2627static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2628{
2629 struct dw_mci_board *pdata;
2630 struct device *dev = host->dev;
2631 struct device_node *np = dev->of_node;
2632 const struct dw_mci_drv_data *drv_data = host->drv_data;
2633 int idx, ret;
2634 u32 clock_frequency;
2635
2636 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2637 if (!pdata)
2638 return ERR_PTR(-ENOMEM);
2639
2640
2641 if (of_property_read_u32(dev->of_node, "num-slots",
2642 &pdata->num_slots)) {
2643 dev_info(dev, "num-slots property not found, "
2644 "assuming 1 slot is available\n");
2645 pdata->num_slots = 1;
2646 }
2647
2648
2649 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2650 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2651 pdata->quirks |= of_quirks[idx].id;
2652
2653 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2654 dev_info(dev, "fifo-depth property not found, using "
2655 "value of FIFOTH register as default\n");
2656
2657 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2658
2659 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2660 pdata->bus_hz = clock_frequency;
2661
2662 if (drv_data && drv_data->parse_dt) {
2663 ret = drv_data->parse_dt(host);
2664 if (ret)
2665 return ERR_PTR(ret);
2666 }
2667
2668 if (of_find_property(np, "supports-highspeed", NULL))
2669 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2670
2671 return pdata;
2672}
2673
2674#else
2675static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2676{
2677 return ERR_PTR(-EINVAL);
2678}
2679#endif
2680
2681static void dw_mci_enable_cd(struct dw_mci *host)
2682{
2683 struct dw_mci_board *brd = host->pdata;
2684 unsigned long irqflags;
2685 u32 temp;
2686 int i;
2687
2688
2689 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2690 return;
2691
2692
2693 for (i = 0; i < host->num_slots; i++) {
2694 struct dw_mci_slot *slot = host->slot[i];
2695
2696 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2697 break;
2698 }
2699 if (i == host->num_slots)
2700 return;
2701
2702 spin_lock_irqsave(&host->irq_lock, irqflags);
2703 temp = mci_readl(host, INTMASK);
2704 temp |= SDMMC_INT_CD;
2705 mci_writel(host, INTMASK, temp);
2706 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2707}
2708
2709int dw_mci_probe(struct dw_mci *host)
2710{
2711 const struct dw_mci_drv_data *drv_data = host->drv_data;
2712 int width, i, ret = 0;
2713 u32 fifo_size;
2714 int init_slots = 0;
2715
2716 if (!host->pdata) {
2717 host->pdata = dw_mci_parse_dt(host);
2718 if (IS_ERR(host->pdata)) {
2719 dev_err(host->dev, "platform data not available\n");
2720 return -EINVAL;
2721 }
2722 }
2723
2724 if (host->pdata->num_slots > 1) {
2725 dev_err(host->dev,
2726 "Platform data must supply num_slots.\n");
2727 return -ENODEV;
2728 }
2729
2730 host->biu_clk = devm_clk_get(host->dev, "biu");
2731 if (IS_ERR(host->biu_clk)) {
2732 dev_dbg(host->dev, "biu clock not available\n");
2733 } else {
2734 ret = clk_prepare_enable(host->biu_clk);
2735 if (ret) {
2736 dev_err(host->dev, "failed to enable biu clock\n");
2737 return ret;
2738 }
2739 }
2740
2741 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2742 if (IS_ERR(host->ciu_clk)) {
2743 dev_dbg(host->dev, "ciu clock not available\n");
2744 host->bus_hz = host->pdata->bus_hz;
2745 } else {
2746 ret = clk_prepare_enable(host->ciu_clk);
2747 if (ret) {
2748 dev_err(host->dev, "failed to enable ciu clock\n");
2749 goto err_clk_biu;
2750 }
2751
2752 if (host->pdata->bus_hz) {
2753 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2754 if (ret)
2755 dev_warn(host->dev,
2756 "Unable to set bus rate to %uHz\n",
2757 host->pdata->bus_hz);
2758 }
2759 host->bus_hz = clk_get_rate(host->ciu_clk);
2760 }
2761
2762 if (!host->bus_hz) {
2763 dev_err(host->dev,
2764 "Platform data must supply bus speed\n");
2765 ret = -ENODEV;
2766 goto err_clk_ciu;
2767 }
2768
2769 if (drv_data && drv_data->init) {
2770 ret = drv_data->init(host);
2771 if (ret) {
2772 dev_err(host->dev,
2773 "implementation specific init failed\n");
2774 goto err_clk_ciu;
2775 }
2776 }
2777
2778 if (drv_data && drv_data->setup_clock) {
2779 ret = drv_data->setup_clock(host);
2780 if (ret) {
2781 dev_err(host->dev,
2782 "implementation specific clock setup failed\n");
2783 goto err_clk_ciu;
2784 }
2785 }
2786
2787 setup_timer(&host->cmd11_timer,
2788 dw_mci_cmd11_timer, (unsigned long)host);
2789
2790 host->quirks = host->pdata->quirks;
2791
2792 spin_lock_init(&host->lock);
2793 spin_lock_init(&host->irq_lock);
2794 INIT_LIST_HEAD(&host->queue);
2795
2796
2797
2798
2799
2800 i = (mci_readl(host, HCON) >> 7) & 0x7;
2801 if (!i) {
2802 host->push_data = dw_mci_push_data16;
2803 host->pull_data = dw_mci_pull_data16;
2804 width = 16;
2805 host->data_shift = 1;
2806 } else if (i == 2) {
2807 host->push_data = dw_mci_push_data64;
2808 host->pull_data = dw_mci_pull_data64;
2809 width = 64;
2810 host->data_shift = 3;
2811 } else {
2812
2813 WARN((i != 1),
2814 "HCON reports a reserved host data width!\n"
2815 "Defaulting to 32-bit access.\n");
2816 host->push_data = dw_mci_push_data32;
2817 host->pull_data = dw_mci_pull_data32;
2818 width = 32;
2819 host->data_shift = 2;
2820 }
2821
2822
2823 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2824 return -ENODEV;
2825
2826 host->dma_ops = host->pdata->dma_ops;
2827 dw_mci_init_dma(host);
2828
2829
2830 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2831 mci_writel(host, INTMASK, 0);
2832
2833
2834 mci_writel(host, TMOUT, 0xFFFFFFFF);
2835
2836
2837
2838
2839
2840 if (!host->pdata->fifo_depth) {
2841
2842
2843
2844
2845
2846
2847 fifo_size = mci_readl(host, FIFOTH);
2848 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2849 } else {
2850 fifo_size = host->pdata->fifo_depth;
2851 }
2852 host->fifo_depth = fifo_size;
2853 host->fifoth_val =
2854 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2855 mci_writel(host, FIFOTH, host->fifoth_val);
2856
2857
2858 mci_writel(host, CLKENA, 0);
2859 mci_writel(host, CLKSRC, 0);
2860
2861
2862
2863
2864
2865 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2866 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2867
2868 if (host->verid < DW_MMC_240A)
2869 host->fifo_reg = host->regs + DATA_OFFSET;
2870 else
2871 host->fifo_reg = host->regs + DATA_240A_OFFSET;
2872
2873 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2874 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2875 host->irq_flags, "dw-mci", host);
2876 if (ret)
2877 goto err_dmaunmap;
2878
2879 if (host->pdata->num_slots)
2880 host->num_slots = host->pdata->num_slots;
2881 else
2882 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2883
2884
2885
2886
2887
2888 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2889 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2890 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2891 DW_MCI_ERROR_FLAGS);
2892 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2893
2894 dev_info(host->dev, "DW MMC controller at irq %d, "
2895 "%d bit host data width, "
2896 "%u deep fifo\n",
2897 host->irq, width, fifo_size);
2898
2899
2900 for (i = 0; i < host->num_slots; i++) {
2901 ret = dw_mci_init_slot(host, i);
2902 if (ret)
2903 dev_dbg(host->dev, "slot %d init failed\n", i);
2904 else
2905 init_slots++;
2906 }
2907
2908 if (init_slots) {
2909 dev_info(host->dev, "%d slots initialized\n", init_slots);
2910 } else {
2911 dev_dbg(host->dev, "attempted to initialize %d slots, "
2912 "but failed on all\n", host->num_slots);
2913 goto err_dmaunmap;
2914 }
2915
2916
2917 dw_mci_enable_cd(host);
2918
2919 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2920 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2921
2922 return 0;
2923
2924err_dmaunmap:
2925 if (host->use_dma && host->dma_ops->exit)
2926 host->dma_ops->exit(host);
2927
2928err_clk_ciu:
2929 if (!IS_ERR(host->ciu_clk))
2930 clk_disable_unprepare(host->ciu_clk);
2931
2932err_clk_biu:
2933 if (!IS_ERR(host->biu_clk))
2934 clk_disable_unprepare(host->biu_clk);
2935
2936 return ret;
2937}
2938EXPORT_SYMBOL(dw_mci_probe);
2939
2940void dw_mci_remove(struct dw_mci *host)
2941{
2942 int i;
2943
2944 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2945 mci_writel(host, INTMASK, 0);
2946
2947 for (i = 0; i < host->num_slots; i++) {
2948 dev_dbg(host->dev, "remove slot %d\n", i);
2949 if (host->slot[i])
2950 dw_mci_cleanup_slot(host->slot[i], i);
2951 }
2952
2953
2954 mci_writel(host, CLKENA, 0);
2955 mci_writel(host, CLKSRC, 0);
2956
2957 if (host->use_dma && host->dma_ops->exit)
2958 host->dma_ops->exit(host);
2959
2960 if (!IS_ERR(host->ciu_clk))
2961 clk_disable_unprepare(host->ciu_clk);
2962
2963 if (!IS_ERR(host->biu_clk))
2964 clk_disable_unprepare(host->biu_clk);
2965}
2966EXPORT_SYMBOL(dw_mci_remove);
2967
2968
2969
2970#ifdef CONFIG_PM_SLEEP
2971
2972
2973
2974int dw_mci_suspend(struct dw_mci *host)
2975{
2976 return 0;
2977}
2978EXPORT_SYMBOL(dw_mci_suspend);
2979
2980int dw_mci_resume(struct dw_mci *host)
2981{
2982 int i, ret;
2983
2984 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2985 ret = -ENODEV;
2986 return ret;
2987 }
2988
2989 if (host->use_dma && host->dma_ops->init)
2990 host->dma_ops->init(host);
2991
2992
2993
2994
2995
2996 mci_writel(host, FIFOTH, host->fifoth_val);
2997 host->prev_blksz = 0;
2998
2999
3000 mci_writel(host, TMOUT, 0xFFFFFFFF);
3001
3002 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3003 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3004 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3005 DW_MCI_ERROR_FLAGS);
3006 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3007
3008 for (i = 0; i < host->num_slots; i++) {
3009 struct dw_mci_slot *slot = host->slot[i];
3010 if (!slot)
3011 continue;
3012 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3013 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3014 dw_mci_setup_bus(slot, true);
3015 }
3016 }
3017
3018
3019 dw_mci_enable_cd(host);
3020
3021 return 0;
3022}
3023EXPORT_SYMBOL(dw_mci_resume);
3024#endif
3025
3026static int __init dw_mci_init(void)
3027{
3028 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3029 return 0;
3030}
3031
3032static void __exit dw_mci_exit(void)
3033{
3034}
3035
3036module_init(dw_mci_init);
3037module_exit(dw_mci_exit);
3038
3039MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3040MODULE_AUTHOR("NXP Semiconductor VietNam");
3041MODULE_AUTHOR("Imagination Technologies Ltd");
3042MODULE_LICENSE("GPL v2");
3043