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18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/debugfs.h>
22#include <linux/dmaengine.h>
23#include <linux/seq_file.h>
24#include <linux/sizes.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/timer.h>
30#include <linux/clk.h>
31#include <linux/of.h>
32#include <linux/of_irq.h>
33#include <linux/of_gpio.h>
34#include <linux/of_device.h>
35#include <linux/omap-dmaengine.h>
36#include <linux/mmc/host.h>
37#include <linux/mmc/core.h>
38#include <linux/mmc/mmc.h>
39#include <linux/mmc/slot-gpio.h>
40#include <linux/io.h>
41#include <linux/irq.h>
42#include <linux/gpio.h>
43#include <linux/regulator/consumer.h>
44#include <linux/pinctrl/consumer.h>
45#include <linux/pm_runtime.h>
46#include <linux/platform_data/hsmmc-omap.h>
47
48
49#define OMAP_HSMMC_SYSSTATUS 0x0014
50#define OMAP_HSMMC_CON 0x002C
51#define OMAP_HSMMC_SDMASA 0x0100
52#define OMAP_HSMMC_BLK 0x0104
53#define OMAP_HSMMC_ARG 0x0108
54#define OMAP_HSMMC_CMD 0x010C
55#define OMAP_HSMMC_RSP10 0x0110
56#define OMAP_HSMMC_RSP32 0x0114
57#define OMAP_HSMMC_RSP54 0x0118
58#define OMAP_HSMMC_RSP76 0x011C
59#define OMAP_HSMMC_DATA 0x0120
60#define OMAP_HSMMC_PSTATE 0x0124
61#define OMAP_HSMMC_HCTL 0x0128
62#define OMAP_HSMMC_SYSCTL 0x012C
63#define OMAP_HSMMC_STAT 0x0130
64#define OMAP_HSMMC_IE 0x0134
65#define OMAP_HSMMC_ISE 0x0138
66#define OMAP_HSMMC_AC12 0x013C
67#define OMAP_HSMMC_CAPA 0x0140
68
69#define VS18 (1 << 26)
70#define VS30 (1 << 25)
71#define HSS (1 << 21)
72#define SDVS18 (0x5 << 9)
73#define SDVS30 (0x6 << 9)
74#define SDVS33 (0x7 << 9)
75#define SDVS_MASK 0x00000E00
76#define SDVSCLR 0xFFFFF1FF
77#define SDVSDET 0x00000400
78#define AUTOIDLE 0x1
79#define SDBP (1 << 8)
80#define DTO 0xe
81#define ICE 0x1
82#define ICS 0x2
83#define CEN (1 << 2)
84#define CLKD_MAX 0x3FF
85#define CLKD_MASK 0x0000FFC0
86#define CLKD_SHIFT 6
87#define DTO_MASK 0x000F0000
88#define DTO_SHIFT 16
89#define INIT_STREAM (1 << 1)
90#define ACEN_ACMD23 (2 << 2)
91#define DP_SELECT (1 << 21)
92#define DDIR (1 << 4)
93#define DMAE 0x1
94#define MSBS (1 << 5)
95#define BCE (1 << 1)
96#define FOUR_BIT (1 << 1)
97#define HSPE (1 << 2)
98#define IWE (1 << 24)
99#define DDR (1 << 19)
100#define CLKEXTFREE (1 << 16)
101#define CTPL (1 << 11)
102#define DW8 (1 << 5)
103#define OD 0x1
104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
109#define SOFTRESET (1 << 1)
110
111
112#define DLEV_DAT(x) (1 << (20 + (x)))
113
114
115#define CC_EN (1 << 0)
116#define TC_EN (1 << 1)
117#define BWR_EN (1 << 4)
118#define BRR_EN (1 << 5)
119#define CIRQ_EN (1 << 8)
120#define ERR_EN (1 << 15)
121#define CTO_EN (1 << 16)
122#define CCRC_EN (1 << 17)
123#define CEB_EN (1 << 18)
124#define CIE_EN (1 << 19)
125#define DTO_EN (1 << 20)
126#define DCRC_EN (1 << 21)
127#define DEB_EN (1 << 22)
128#define ACE_EN (1 << 24)
129#define CERR_EN (1 << 28)
130#define BADA_EN (1 << 29)
131
132#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
135
136#define CNI (1 << 7)
137#define ACIE (1 << 4)
138#define ACEB (1 << 3)
139#define ACCE (1 << 2)
140#define ACTO (1 << 1)
141#define ACNE (1 << 0)
142
143#define MMC_AUTOSUSPEND_DELAY 100
144#define MMC_TIMEOUT_MS 20
145#define MMC_TIMEOUT_US 20000
146#define OMAP_MMC_MIN_CLOCK 400000
147#define OMAP_MMC_MAX_CLOCK 52000000
148#define DRIVER_NAME "omap_hsmmc"
149
150#define VDD_1V8 1800000
151#define VDD_3V0 3000000
152#define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
153
154
155
156
157
158
159#define mmc_pdata(host) host->pdata
160
161
162
163
164#define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
166
167#define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
169
170struct omap_hsmmc_next {
171 unsigned int dma_len;
172 s32 cookie;
173};
174
175struct omap_hsmmc_host {
176 struct device *dev;
177 struct mmc_host *mmc;
178 struct mmc_request *mrq;
179 struct mmc_command *cmd;
180 struct mmc_data *data;
181 struct clk *fclk;
182 struct clk *dbclk;
183
184
185
186
187
188
189
190 struct regulator *vcc;
191 struct regulator *vcc_aux;
192 struct regulator *pbias;
193 bool pbias_enabled;
194 void __iomem *base;
195 resource_size_t mapbase;
196 spinlock_t irq_lock;
197 unsigned int dma_len;
198 unsigned int dma_sg_idx;
199 unsigned char bus_mode;
200 unsigned char power_mode;
201 int suspended;
202 u32 con;
203 u32 hctl;
204 u32 sysctl;
205 u32 capa;
206 int irq;
207 int wake_irq;
208 int use_dma, dma_ch;
209 struct dma_chan *tx_chan;
210 struct dma_chan *rx_chan;
211 int response_busy;
212 int context_loss;
213 int protect_card;
214 int reqs_blocked;
215 int use_reg;
216 int req_in_progress;
217 unsigned long clk_rate;
218 unsigned int flags;
219#define AUTO_CMD23 (1 << 0)
220#define HSMMC_SDIO_IRQ_ENABLED (1 << 1)
221#define HSMMC_WAKE_IRQ_ENABLED (1 << 2)
222 struct omap_hsmmc_next next_data;
223 struct omap_hsmmc_platform_data *pdata;
224
225
226
227
228
229
230
231 int (*get_cover_state)(struct device *dev);
232
233 int (*card_detect)(struct device *dev);
234};
235
236struct omap_mmc_of_data {
237 u32 reg_offset;
238 u8 controller_flags;
239};
240
241static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
242
243static int omap_hsmmc_card_detect(struct device *dev)
244{
245 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
246
247 return mmc_gpio_get_cd(host->mmc);
248}
249
250static int omap_hsmmc_get_cover_state(struct device *dev)
251{
252 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
253
254 return mmc_gpio_get_cd(host->mmc);
255}
256
257#ifdef CONFIG_REGULATOR
258
259static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
260{
261 struct omap_hsmmc_host *host =
262 platform_get_drvdata(to_platform_device(dev));
263 int ret = 0;
264
265
266
267
268
269 if (!host->vcc)
270 return 0;
271
272 if (mmc_pdata(host)->before_set_reg)
273 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
274
275 if (host->pbias) {
276 if (host->pbias_enabled == 1) {
277 ret = regulator_disable(host->pbias);
278 if (!ret)
279 host->pbias_enabled = 0;
280 }
281 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
282 }
283
284
285
286
287
288
289
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291
292
293
294
295
296
297 if (power_on) {
298 if (host->vcc)
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0 && host->vcc)
304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
306 }
307 } else {
308
309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
311 if (host->vcc) {
312
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
316 }
317
318 if (host->pbias) {
319 if (vdd <= VDD_165_195)
320 ret = regulator_set_voltage(host->pbias, VDD_1V8,
321 VDD_1V8);
322 else
323 ret = regulator_set_voltage(host->pbias, VDD_3V0,
324 VDD_3V0);
325 if (ret < 0)
326 goto error_set_power;
327
328 if (host->pbias_enabled == 0) {
329 ret = regulator_enable(host->pbias);
330 if (!ret)
331 host->pbias_enabled = 1;
332 }
333 }
334
335 if (mmc_pdata(host)->after_set_reg)
336 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
337
338error_set_power:
339 return ret;
340}
341
342static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
343{
344 struct regulator *reg;
345 int ocr_value = 0;
346
347 reg = devm_regulator_get(host->dev, "vmmc");
348 if (IS_ERR(reg)) {
349 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
350 PTR_ERR(reg));
351 return PTR_ERR(reg);
352 } else {
353 host->vcc = reg;
354 ocr_value = mmc_regulator_get_ocrmask(reg);
355 if (!mmc_pdata(host)->ocr_mask) {
356 mmc_pdata(host)->ocr_mask = ocr_value;
357 } else {
358 if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
359 dev_err(host->dev, "ocrmask %x is not supported\n",
360 mmc_pdata(host)->ocr_mask);
361 mmc_pdata(host)->ocr_mask = 0;
362 return -EINVAL;
363 }
364 }
365 }
366 mmc_pdata(host)->set_power = omap_hsmmc_set_power;
367
368
369 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
370 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
371
372 reg = devm_regulator_get_optional(host->dev, "pbias");
373 host->pbias = IS_ERR(reg) ? NULL : reg;
374
375
376 if (mmc_pdata(host)->no_regulator_off_init)
377 return 0;
378
379
380
381
382 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
383 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
384 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
385
386 mmc_pdata(host)->set_power(host->dev, 1, vdd);
387 mmc_pdata(host)->set_power(host->dev, 0, 0);
388 }
389
390 return 0;
391}
392
393static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
394{
395 mmc_pdata(host)->set_power = NULL;
396}
397
398static inline int omap_hsmmc_have_reg(void)
399{
400 return 1;
401}
402
403#else
404
405static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
406{
407 return -EINVAL;
408}
409
410static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
411{
412}
413
414static inline int omap_hsmmc_have_reg(void)
415{
416 return 0;
417}
418
419#endif
420
421static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
422
423static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
424 struct omap_hsmmc_host *host,
425 struct omap_hsmmc_platform_data *pdata)
426{
427 int ret;
428
429 if (gpio_is_valid(pdata->gpio_cod)) {
430 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
431 if (ret)
432 return ret;
433
434 host->get_cover_state = omap_hsmmc_get_cover_state;
435 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
436 } else if (gpio_is_valid(pdata->gpio_cd)) {
437 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
438 if (ret)
439 return ret;
440
441 host->card_detect = omap_hsmmc_card_detect;
442 }
443
444 if (gpio_is_valid(pdata->gpio_wp)) {
445 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451}
452
453
454
455
456static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
457{
458 OMAP_HSMMC_WRITE(host->base, SYSCTL,
459 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
460}
461
462
463
464
465static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
466{
467 OMAP_HSMMC_WRITE(host->base, SYSCTL,
468 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
469 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
470 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
471}
472
473static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
474 struct mmc_command *cmd)
475{
476 u32 irq_mask = INT_EN_MASK;
477 unsigned long flags;
478
479 if (host->use_dma)
480 irq_mask &= ~(BRR_EN | BWR_EN);
481
482
483 if (cmd->opcode == MMC_ERASE)
484 irq_mask &= ~DTO_EN;
485
486 spin_lock_irqsave(&host->irq_lock, flags);
487 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
488 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
489
490
491 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
492 irq_mask |= CIRQ_EN;
493 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
494 spin_unlock_irqrestore(&host->irq_lock, flags);
495}
496
497static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
498{
499 u32 irq_mask = 0;
500 unsigned long flags;
501
502 spin_lock_irqsave(&host->irq_lock, flags);
503
504 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
505 irq_mask |= CIRQ_EN;
506 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
507 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
508 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
509 spin_unlock_irqrestore(&host->irq_lock, flags);
510}
511
512
513static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
514{
515 u16 dsor = 0;
516
517 if (ios->clock) {
518 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
519 if (dsor > CLKD_MAX)
520 dsor = CLKD_MAX;
521 }
522
523 return dsor;
524}
525
526static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
527{
528 struct mmc_ios *ios = &host->mmc->ios;
529 unsigned long regval;
530 unsigned long timeout;
531 unsigned long clkdiv;
532
533 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
534
535 omap_hsmmc_stop_clock(host);
536
537 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
538 regval = regval & ~(CLKD_MASK | DTO_MASK);
539 clkdiv = calc_divisor(host, ios);
540 regval = regval | (clkdiv << 6) | (DTO << 16);
541 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
542 OMAP_HSMMC_WRITE(host->base, SYSCTL,
543 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
544
545
546 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
547 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
548 && time_before(jiffies, timeout))
549 cpu_relax();
550
551
552
553
554
555
556
557
558
559
560 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
561 (ios->timing != MMC_TIMING_MMC_DDR52) &&
562 (ios->timing != MMC_TIMING_UHS_DDR50) &&
563 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
564 regval = OMAP_HSMMC_READ(host->base, HCTL);
565 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
566 regval |= HSPE;
567 else
568 regval &= ~HSPE;
569
570 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
571 }
572
573 omap_hsmmc_start_clock(host);
574}
575
576static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
577{
578 struct mmc_ios *ios = &host->mmc->ios;
579 u32 con;
580
581 con = OMAP_HSMMC_READ(host->base, CON);
582 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
583 ios->timing == MMC_TIMING_UHS_DDR50)
584 con |= DDR;
585 else
586 con &= ~DDR;
587 switch (ios->bus_width) {
588 case MMC_BUS_WIDTH_8:
589 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
590 break;
591 case MMC_BUS_WIDTH_4:
592 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
593 OMAP_HSMMC_WRITE(host->base, HCTL,
594 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
595 break;
596 case MMC_BUS_WIDTH_1:
597 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
598 OMAP_HSMMC_WRITE(host->base, HCTL,
599 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
600 break;
601 }
602}
603
604static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
605{
606 struct mmc_ios *ios = &host->mmc->ios;
607 u32 con;
608
609 con = OMAP_HSMMC_READ(host->base, CON);
610 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
611 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
612 else
613 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
614}
615
616#ifdef CONFIG_PM
617
618
619
620
621
622static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
623{
624 struct mmc_ios *ios = &host->mmc->ios;
625 u32 hctl, capa;
626 unsigned long timeout;
627
628 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
629 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
630 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
631 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
632 return 0;
633
634 host->context_loss++;
635
636 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
637 if (host->power_mode != MMC_POWER_OFF &&
638 (1 << ios->vdd) <= MMC_VDD_23_24)
639 hctl = SDVS18;
640 else
641 hctl = SDVS30;
642 capa = VS30 | VS18;
643 } else {
644 hctl = SDVS18;
645 capa = VS18;
646 }
647
648 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
649 hctl |= IWE;
650
651 OMAP_HSMMC_WRITE(host->base, HCTL,
652 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
653
654 OMAP_HSMMC_WRITE(host->base, CAPA,
655 OMAP_HSMMC_READ(host->base, CAPA) | capa);
656
657 OMAP_HSMMC_WRITE(host->base, HCTL,
658 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
659
660 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
661 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
662 && time_before(jiffies, timeout))
663 ;
664
665 OMAP_HSMMC_WRITE(host->base, ISE, 0);
666 OMAP_HSMMC_WRITE(host->base, IE, 0);
667 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
668
669
670 if (host->power_mode == MMC_POWER_OFF)
671 goto out;
672
673 omap_hsmmc_set_bus_width(host);
674
675 omap_hsmmc_set_clock(host);
676
677 omap_hsmmc_set_bus_mode(host);
678
679out:
680 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
681 host->context_loss);
682 return 0;
683}
684
685
686
687
688static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
689{
690 host->con = OMAP_HSMMC_READ(host->base, CON);
691 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
692 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
693 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
694}
695
696#else
697
698static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
699{
700 return 0;
701}
702
703static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
704{
705}
706
707#endif
708
709
710
711
712
713static void send_init_stream(struct omap_hsmmc_host *host)
714{
715 int reg = 0;
716 unsigned long timeout;
717
718 if (host->protect_card)
719 return;
720
721 disable_irq(host->irq);
722
723 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
724 OMAP_HSMMC_WRITE(host->base, CON,
725 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
726 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
727
728 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
729 while ((reg != CC_EN) && time_before(jiffies, timeout))
730 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
731
732 OMAP_HSMMC_WRITE(host->base, CON,
733 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
734
735 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
736 OMAP_HSMMC_READ(host->base, STAT);
737
738 enable_irq(host->irq);
739}
740
741static inline
742int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
743{
744 int r = 1;
745
746 if (host->get_cover_state)
747 r = host->get_cover_state(host->dev);
748 return r;
749}
750
751static ssize_t
752omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
753 char *buf)
754{
755 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
756 struct omap_hsmmc_host *host = mmc_priv(mmc);
757
758 return sprintf(buf, "%s\n",
759 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
760}
761
762static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
763
764static ssize_t
765omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
766 char *buf)
767{
768 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
769 struct omap_hsmmc_host *host = mmc_priv(mmc);
770
771 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
772}
773
774static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
775
776
777
778
779static void
780omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
781 struct mmc_data *data)
782{
783 int cmdreg = 0, resptype = 0, cmdtype = 0;
784
785 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
786 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
787 host->cmd = cmd;
788
789 omap_hsmmc_enable_irq(host, cmd);
790
791 host->response_busy = 0;
792 if (cmd->flags & MMC_RSP_PRESENT) {
793 if (cmd->flags & MMC_RSP_136)
794 resptype = 1;
795 else if (cmd->flags & MMC_RSP_BUSY) {
796 resptype = 3;
797 host->response_busy = 1;
798 } else
799 resptype = 2;
800 }
801
802
803
804
805
806
807 if (cmd == host->mrq->stop)
808 cmdtype = 0x3;
809
810 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
811
812 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
813 host->mrq->sbc) {
814 cmdreg |= ACEN_ACMD23;
815 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
816 }
817 if (data) {
818 cmdreg |= DP_SELECT | MSBS | BCE;
819 if (data->flags & MMC_DATA_READ)
820 cmdreg |= DDIR;
821 else
822 cmdreg &= ~(DDIR);
823 }
824
825 if (host->use_dma)
826 cmdreg |= DMAE;
827
828 host->req_in_progress = 1;
829
830 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
831 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
832}
833
834static int
835omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
836{
837 if (data->flags & MMC_DATA_WRITE)
838 return DMA_TO_DEVICE;
839 else
840 return DMA_FROM_DEVICE;
841}
842
843static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
844 struct mmc_data *data)
845{
846 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
847}
848
849static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
850{
851 int dma_ch;
852 unsigned long flags;
853
854 spin_lock_irqsave(&host->irq_lock, flags);
855 host->req_in_progress = 0;
856 dma_ch = host->dma_ch;
857 spin_unlock_irqrestore(&host->irq_lock, flags);
858
859 omap_hsmmc_disable_irq(host);
860
861 if (mrq->data && host->use_dma && dma_ch != -1)
862 return;
863 host->mrq = NULL;
864 mmc_request_done(host->mmc, mrq);
865 pm_runtime_mark_last_busy(host->dev);
866 pm_runtime_put_autosuspend(host->dev);
867}
868
869
870
871
872static void
873omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
874{
875 if (!data) {
876 struct mmc_request *mrq = host->mrq;
877
878
879 if (host->cmd && host->cmd->opcode == 6 &&
880 host->response_busy) {
881 host->response_busy = 0;
882 return;
883 }
884
885 omap_hsmmc_request_done(host, mrq);
886 return;
887 }
888
889 host->data = NULL;
890
891 if (!data->error)
892 data->bytes_xfered += data->blocks * (data->blksz);
893 else
894 data->bytes_xfered = 0;
895
896 if (data->stop && (data->error || !host->mrq->sbc))
897 omap_hsmmc_start_command(host, data->stop, NULL);
898 else
899 omap_hsmmc_request_done(host, data->mrq);
900}
901
902
903
904
905static void
906omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
907{
908 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
909 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
910 host->cmd = NULL;
911 omap_hsmmc_start_dma_transfer(host);
912 omap_hsmmc_start_command(host, host->mrq->cmd,
913 host->mrq->data);
914 return;
915 }
916
917 host->cmd = NULL;
918
919 if (cmd->flags & MMC_RSP_PRESENT) {
920 if (cmd->flags & MMC_RSP_136) {
921
922 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
923 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
924 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
925 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
926 } else {
927
928 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
929 }
930 }
931 if ((host->data == NULL && !host->response_busy) || cmd->error)
932 omap_hsmmc_request_done(host, host->mrq);
933}
934
935
936
937
938static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
939{
940 int dma_ch;
941 unsigned long flags;
942
943 host->data->error = errno;
944
945 spin_lock_irqsave(&host->irq_lock, flags);
946 dma_ch = host->dma_ch;
947 host->dma_ch = -1;
948 spin_unlock_irqrestore(&host->irq_lock, flags);
949
950 if (host->use_dma && dma_ch != -1) {
951 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
952
953 dmaengine_terminate_all(chan);
954 dma_unmap_sg(chan->device->dev,
955 host->data->sg, host->data->sg_len,
956 omap_hsmmc_get_dma_dir(host, host->data));
957
958 host->data->host_cookie = 0;
959 }
960 host->data = NULL;
961}
962
963
964
965
966#ifdef CONFIG_MMC_DEBUG
967static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
968{
969
970 static const char *omap_hsmmc_status_bits[] = {
971 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
972 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
973 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
974 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
975 };
976 char res[256];
977 char *buf = res;
978 int len, i;
979
980 len = sprintf(buf, "MMC IRQ 0x%x :", status);
981 buf += len;
982
983 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
984 if (status & (1 << i)) {
985 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
986 buf += len;
987 }
988
989 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
990}
991#else
992static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
993 u32 status)
994{
995}
996#endif
997
998
999
1000
1001
1002
1003
1004
1005static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1006 unsigned long bit)
1007{
1008 unsigned long i = 0;
1009 unsigned long limit = MMC_TIMEOUT_US;
1010
1011 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1012 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1013
1014
1015
1016
1017
1018 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1019 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1020 && (i++ < limit))
1021 udelay(1);
1022 }
1023 i = 0;
1024
1025 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1026 (i++ < limit))
1027 udelay(1);
1028
1029 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1030 dev_err(mmc_dev(host->mmc),
1031 "Timeout waiting on controller reset in %s\n",
1032 __func__);
1033}
1034
1035static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1036 int err, int end_cmd)
1037{
1038 if (end_cmd) {
1039 omap_hsmmc_reset_controller_fsm(host, SRC);
1040 if (host->cmd)
1041 host->cmd->error = err;
1042 }
1043
1044 if (host->data) {
1045 omap_hsmmc_reset_controller_fsm(host, SRD);
1046 omap_hsmmc_dma_cleanup(host, err);
1047 } else if (host->mrq && host->mrq->cmd)
1048 host->mrq->cmd->error = err;
1049}
1050
1051static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1052{
1053 struct mmc_data *data;
1054 int end_cmd = 0, end_trans = 0;
1055 int error = 0;
1056
1057 data = host->data;
1058 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1059
1060 if (status & ERR_EN) {
1061 omap_hsmmc_dbg_report_irq(host, status);
1062
1063 if (status & (CTO_EN | CCRC_EN))
1064 end_cmd = 1;
1065 if (status & (CTO_EN | DTO_EN))
1066 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1067 else if (status & (CCRC_EN | DCRC_EN))
1068 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1069
1070 if (status & ACE_EN) {
1071 u32 ac12;
1072 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1073 if (!(ac12 & ACNE) && host->mrq->sbc) {
1074 end_cmd = 1;
1075 if (ac12 & ACTO)
1076 error = -ETIMEDOUT;
1077 else if (ac12 & (ACCE | ACEB | ACIE))
1078 error = -EILSEQ;
1079 host->mrq->sbc->error = error;
1080 hsmmc_command_incomplete(host, error, end_cmd);
1081 }
1082 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1083 }
1084 if (host->data || host->response_busy) {
1085 end_trans = !end_cmd;
1086 host->response_busy = 0;
1087 }
1088 }
1089
1090 OMAP_HSMMC_WRITE(host->base, STAT, status);
1091 if (end_cmd || ((status & CC_EN) && host->cmd))
1092 omap_hsmmc_cmd_done(host, host->cmd);
1093 if ((end_trans || (status & TC_EN)) && host->mrq)
1094 omap_hsmmc_xfer_done(host, data);
1095}
1096
1097
1098
1099
1100static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1101{
1102 struct omap_hsmmc_host *host = dev_id;
1103 int status;
1104
1105 status = OMAP_HSMMC_READ(host->base, STAT);
1106 while (status & (INT_EN_MASK | CIRQ_EN)) {
1107 if (host->req_in_progress)
1108 omap_hsmmc_do_irq(host, status);
1109
1110 if (status & CIRQ_EN)
1111 mmc_signal_sdio_irq(host->mmc);
1112
1113
1114 status = OMAP_HSMMC_READ(host->base, STAT);
1115 }
1116
1117 return IRQ_HANDLED;
1118}
1119
1120static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1121{
1122 struct omap_hsmmc_host *host = dev_id;
1123
1124
1125 spin_lock(&host->irq_lock);
1126 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1127 disable_irq_nosync(host->wake_irq);
1128 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1129 }
1130 spin_unlock(&host->irq_lock);
1131 pm_request_resume(host->dev);
1132
1133 return IRQ_HANDLED;
1134}
1135
1136static void set_sd_bus_power(struct omap_hsmmc_host *host)
1137{
1138 unsigned long i;
1139
1140 OMAP_HSMMC_WRITE(host->base, HCTL,
1141 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1142 for (i = 0; i < loops_per_jiffy; i++) {
1143 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1144 break;
1145 cpu_relax();
1146 }
1147}
1148
1149
1150
1151
1152
1153
1154
1155
1156static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1157{
1158 u32 reg_val = 0;
1159 int ret;
1160
1161
1162 pm_runtime_put_sync(host->dev);
1163 if (host->dbclk)
1164 clk_disable_unprepare(host->dbclk);
1165
1166
1167 ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1168
1169
1170 if (!ret)
1171 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1172 pm_runtime_get_sync(host->dev);
1173 if (host->dbclk)
1174 clk_prepare_enable(host->dbclk);
1175
1176 if (ret != 0)
1177 goto err;
1178
1179 OMAP_HSMMC_WRITE(host->base, HCTL,
1180 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1181 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198 if ((1 << vdd) <= MMC_VDD_23_24)
1199 reg_val |= SDVS18;
1200 else
1201 reg_val |= SDVS30;
1202
1203 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1204 set_sd_bus_power(host);
1205
1206 return 0;
1207err:
1208 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1209 return ret;
1210}
1211
1212
1213static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1214{
1215 if (!host->get_cover_state)
1216 return;
1217
1218 host->reqs_blocked = 0;
1219 if (host->get_cover_state(host->dev)) {
1220 if (host->protect_card) {
1221 dev_info(host->dev, "%s: cover is closed, "
1222 "card is now accessible\n",
1223 mmc_hostname(host->mmc));
1224 host->protect_card = 0;
1225 }
1226 } else {
1227 if (!host->protect_card) {
1228 dev_info(host->dev, "%s: cover is open, "
1229 "card is now inaccessible\n",
1230 mmc_hostname(host->mmc));
1231 host->protect_card = 1;
1232 }
1233 }
1234}
1235
1236
1237
1238
1239static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1240{
1241 struct omap_hsmmc_host *host = dev_id;
1242
1243 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1244
1245 omap_hsmmc_protect_card(host);
1246 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1247 return IRQ_HANDLED;
1248}
1249
1250static void omap_hsmmc_dma_callback(void *param)
1251{
1252 struct omap_hsmmc_host *host = param;
1253 struct dma_chan *chan;
1254 struct mmc_data *data;
1255 int req_in_progress;
1256
1257 spin_lock_irq(&host->irq_lock);
1258 if (host->dma_ch < 0) {
1259 spin_unlock_irq(&host->irq_lock);
1260 return;
1261 }
1262
1263 data = host->mrq->data;
1264 chan = omap_hsmmc_get_dma_chan(host, data);
1265 if (!data->host_cookie)
1266 dma_unmap_sg(chan->device->dev,
1267 data->sg, data->sg_len,
1268 omap_hsmmc_get_dma_dir(host, data));
1269
1270 req_in_progress = host->req_in_progress;
1271 host->dma_ch = -1;
1272 spin_unlock_irq(&host->irq_lock);
1273
1274
1275 if (!req_in_progress) {
1276 struct mmc_request *mrq = host->mrq;
1277
1278 host->mrq = NULL;
1279 mmc_request_done(host->mmc, mrq);
1280 pm_runtime_mark_last_busy(host->dev);
1281 pm_runtime_put_autosuspend(host->dev);
1282 }
1283}
1284
1285static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1286 struct mmc_data *data,
1287 struct omap_hsmmc_next *next,
1288 struct dma_chan *chan)
1289{
1290 int dma_len;
1291
1292 if (!next && data->host_cookie &&
1293 data->host_cookie != host->next_data.cookie) {
1294 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1295 " host->next_data.cookie %d\n",
1296 __func__, data->host_cookie, host->next_data.cookie);
1297 data->host_cookie = 0;
1298 }
1299
1300
1301 if (next || data->host_cookie != host->next_data.cookie) {
1302 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1303 omap_hsmmc_get_dma_dir(host, data));
1304
1305 } else {
1306 dma_len = host->next_data.dma_len;
1307 host->next_data.dma_len = 0;
1308 }
1309
1310
1311 if (dma_len == 0)
1312 return -EINVAL;
1313
1314 if (next) {
1315 next->dma_len = dma_len;
1316 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1317 } else
1318 host->dma_len = dma_len;
1319
1320 return 0;
1321}
1322
1323
1324
1325
1326static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1327 struct mmc_request *req)
1328{
1329 struct dma_slave_config cfg;
1330 struct dma_async_tx_descriptor *tx;
1331 int ret = 0, i;
1332 struct mmc_data *data = req->data;
1333 struct dma_chan *chan;
1334
1335
1336 for (i = 0; i < data->sg_len; i++) {
1337 struct scatterlist *sgl;
1338
1339 sgl = data->sg + i;
1340 if (sgl->length % data->blksz)
1341 return -EINVAL;
1342 }
1343 if ((data->blksz % 4) != 0)
1344
1345
1346
1347 return -EINVAL;
1348
1349 BUG_ON(host->dma_ch != -1);
1350
1351 chan = omap_hsmmc_get_dma_chan(host, data);
1352
1353 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1354 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1355 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1356 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1357 cfg.src_maxburst = data->blksz / 4;
1358 cfg.dst_maxburst = data->blksz / 4;
1359
1360 ret = dmaengine_slave_config(chan, &cfg);
1361 if (ret)
1362 return ret;
1363
1364 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1365 if (ret)
1366 return ret;
1367
1368 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1369 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1371 if (!tx) {
1372 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1373
1374 return -1;
1375 }
1376
1377 tx->callback = omap_hsmmc_dma_callback;
1378 tx->callback_param = host;
1379
1380
1381 dmaengine_submit(tx);
1382
1383 host->dma_ch = 1;
1384
1385 return 0;
1386}
1387
1388static void set_data_timeout(struct omap_hsmmc_host *host,
1389 unsigned int timeout_ns,
1390 unsigned int timeout_clks)
1391{
1392 unsigned int timeout, cycle_ns;
1393 uint32_t reg, clkd, dto = 0;
1394
1395 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1396 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1397 if (clkd == 0)
1398 clkd = 1;
1399
1400 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1401 timeout = timeout_ns / cycle_ns;
1402 timeout += timeout_clks;
1403 if (timeout) {
1404 while ((timeout & 0x80000000) == 0) {
1405 dto += 1;
1406 timeout <<= 1;
1407 }
1408 dto = 31 - dto;
1409 timeout <<= 1;
1410 if (timeout && dto)
1411 dto += 1;
1412 if (dto >= 13)
1413 dto -= 13;
1414 else
1415 dto = 0;
1416 if (dto > 14)
1417 dto = 14;
1418 }
1419
1420 reg &= ~DTO_MASK;
1421 reg |= dto << DTO_SHIFT;
1422 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1423}
1424
1425static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1426{
1427 struct mmc_request *req = host->mrq;
1428 struct dma_chan *chan;
1429
1430 if (!req->data)
1431 return;
1432 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1433 | (req->data->blocks << 16));
1434 set_data_timeout(host, req->data->timeout_ns,
1435 req->data->timeout_clks);
1436 chan = omap_hsmmc_get_dma_chan(host, req->data);
1437 dma_async_issue_pending(chan);
1438}
1439
1440
1441
1442
1443static int
1444omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1445{
1446 int ret;
1447 host->data = req->data;
1448
1449 if (req->data == NULL) {
1450 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1451
1452
1453
1454
1455 if (req->cmd->flags & MMC_RSP_BUSY)
1456 set_data_timeout(host, 100000000U, 0);
1457 return 0;
1458 }
1459
1460 if (host->use_dma) {
1461 ret = omap_hsmmc_setup_dma_transfer(host, req);
1462 if (ret != 0) {
1463 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1464 return ret;
1465 }
1466 }
1467 return 0;
1468}
1469
1470static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1471 int err)
1472{
1473 struct omap_hsmmc_host *host = mmc_priv(mmc);
1474 struct mmc_data *data = mrq->data;
1475
1476 if (host->use_dma && data->host_cookie) {
1477 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1478
1479 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1480 omap_hsmmc_get_dma_dir(host, data));
1481 data->host_cookie = 0;
1482 }
1483}
1484
1485static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1486 bool is_first_req)
1487{
1488 struct omap_hsmmc_host *host = mmc_priv(mmc);
1489
1490 if (mrq->data->host_cookie) {
1491 mrq->data->host_cookie = 0;
1492 return ;
1493 }
1494
1495 if (host->use_dma) {
1496 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1497
1498 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1499 &host->next_data, c))
1500 mrq->data->host_cookie = 0;
1501 }
1502}
1503
1504
1505
1506
1507static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1508{
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1510 int err;
1511
1512 BUG_ON(host->req_in_progress);
1513 BUG_ON(host->dma_ch != -1);
1514 pm_runtime_get_sync(host->dev);
1515 if (host->protect_card) {
1516 if (host->reqs_blocked < 3) {
1517
1518
1519
1520
1521
1522 omap_hsmmc_reset_controller_fsm(host, SRD);
1523 omap_hsmmc_reset_controller_fsm(host, SRC);
1524 host->reqs_blocked += 1;
1525 }
1526 req->cmd->error = -EBADF;
1527 if (req->data)
1528 req->data->error = -EBADF;
1529 req->cmd->retries = 0;
1530 mmc_request_done(mmc, req);
1531 pm_runtime_mark_last_busy(host->dev);
1532 pm_runtime_put_autosuspend(host->dev);
1533 return;
1534 } else if (host->reqs_blocked)
1535 host->reqs_blocked = 0;
1536 WARN_ON(host->mrq != NULL);
1537 host->mrq = req;
1538 host->clk_rate = clk_get_rate(host->fclk);
1539 err = omap_hsmmc_prepare_data(host, req);
1540 if (err) {
1541 req->cmd->error = err;
1542 if (req->data)
1543 req->data->error = err;
1544 host->mrq = NULL;
1545 mmc_request_done(mmc, req);
1546 pm_runtime_mark_last_busy(host->dev);
1547 pm_runtime_put_autosuspend(host->dev);
1548 return;
1549 }
1550 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1551 omap_hsmmc_start_command(host, req->sbc, NULL);
1552 return;
1553 }
1554
1555 omap_hsmmc_start_dma_transfer(host);
1556 omap_hsmmc_start_command(host, req->cmd, req->data);
1557}
1558
1559
1560static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1561{
1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
1563 int do_send_init_stream = 0;
1564
1565 pm_runtime_get_sync(host->dev);
1566
1567 if (ios->power_mode != host->power_mode) {
1568 switch (ios->power_mode) {
1569 case MMC_POWER_OFF:
1570 mmc_pdata(host)->set_power(host->dev, 0, 0);
1571 break;
1572 case MMC_POWER_UP:
1573 mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1574 break;
1575 case MMC_POWER_ON:
1576 do_send_init_stream = 1;
1577 break;
1578 }
1579 host->power_mode = ios->power_mode;
1580 }
1581
1582
1583
1584 omap_hsmmc_set_bus_width(host);
1585
1586 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1587
1588
1589
1590 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1591 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1592
1593
1594
1595
1596
1597
1598 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1599 dev_dbg(mmc_dev(host->mmc),
1600 "Switch operation failed\n");
1601 }
1602 }
1603
1604 omap_hsmmc_set_clock(host);
1605
1606 if (do_send_init_stream)
1607 send_init_stream(host);
1608
1609 omap_hsmmc_set_bus_mode(host);
1610
1611 pm_runtime_put_autosuspend(host->dev);
1612}
1613
1614static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1615{
1616 struct omap_hsmmc_host *host = mmc_priv(mmc);
1617
1618 if (!host->card_detect)
1619 return -ENOSYS;
1620 return host->card_detect(host->dev);
1621}
1622
1623static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1624{
1625 struct omap_hsmmc_host *host = mmc_priv(mmc);
1626
1627 if (mmc_pdata(host)->init_card)
1628 mmc_pdata(host)->init_card(card);
1629}
1630
1631static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1632{
1633 struct omap_hsmmc_host *host = mmc_priv(mmc);
1634 u32 irq_mask, con;
1635 unsigned long flags;
1636
1637 spin_lock_irqsave(&host->irq_lock, flags);
1638
1639 con = OMAP_HSMMC_READ(host->base, CON);
1640 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1641 if (enable) {
1642 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1643 irq_mask |= CIRQ_EN;
1644 con |= CTPL | CLKEXTFREE;
1645 } else {
1646 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1647 irq_mask &= ~CIRQ_EN;
1648 con &= ~(CTPL | CLKEXTFREE);
1649 }
1650 OMAP_HSMMC_WRITE(host->base, CON, con);
1651 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1652
1653
1654
1655
1656
1657 if (!host->req_in_progress || !enable)
1658 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1659
1660
1661 OMAP_HSMMC_READ(host->base, IE);
1662
1663 spin_unlock_irqrestore(&host->irq_lock, flags);
1664}
1665
1666static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1667{
1668 struct mmc_host *mmc = host->mmc;
1669 int ret;
1670
1671
1672
1673
1674
1675
1676
1677 if (!host->dev->of_node || !host->wake_irq)
1678 return -ENODEV;
1679
1680
1681 irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1682 ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1683 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1684 mmc_hostname(mmc), host);
1685 if (ret) {
1686 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1687 goto err;
1688 }
1689
1690
1691
1692
1693
1694 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1695 struct pinctrl *p = devm_pinctrl_get(host->dev);
1696 if (!p) {
1697 ret = -ENODEV;
1698 goto err_free_irq;
1699 }
1700 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1701 dev_info(host->dev, "missing default pinctrl state\n");
1702 devm_pinctrl_put(p);
1703 ret = -EINVAL;
1704 goto err_free_irq;
1705 }
1706
1707 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1708 dev_info(host->dev, "missing idle pinctrl state\n");
1709 devm_pinctrl_put(p);
1710 ret = -EINVAL;
1711 goto err_free_irq;
1712 }
1713 devm_pinctrl_put(p);
1714 }
1715
1716 OMAP_HSMMC_WRITE(host->base, HCTL,
1717 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1718 return 0;
1719
1720err_free_irq:
1721 devm_free_irq(host->dev, host->wake_irq, host);
1722err:
1723 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1724 host->wake_irq = 0;
1725 return ret;
1726}
1727
1728static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1729{
1730 u32 hctl, capa, value;
1731
1732
1733 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1734 hctl = SDVS30;
1735 capa = VS30 | VS18;
1736 } else {
1737 hctl = SDVS18;
1738 capa = VS18;
1739 }
1740
1741 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1742 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1743
1744 value = OMAP_HSMMC_READ(host->base, CAPA);
1745 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1746
1747
1748 set_sd_bus_power(host);
1749}
1750
1751static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1752 unsigned int direction, int blk_size)
1753{
1754
1755 if (direction == MMC_DATA_READ)
1756 return 1;
1757
1758 return blk_size;
1759}
1760
1761static struct mmc_host_ops omap_hsmmc_ops = {
1762 .post_req = omap_hsmmc_post_req,
1763 .pre_req = omap_hsmmc_pre_req,
1764 .request = omap_hsmmc_request,
1765 .set_ios = omap_hsmmc_set_ios,
1766 .get_cd = omap_hsmmc_get_cd,
1767 .get_ro = mmc_gpio_get_ro,
1768 .init_card = omap_hsmmc_init_card,
1769 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1770};
1771
1772#ifdef CONFIG_DEBUG_FS
1773
1774static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1775{
1776 struct mmc_host *mmc = s->private;
1777 struct omap_hsmmc_host *host = mmc_priv(mmc);
1778
1779 seq_printf(s, "mmc%d:\n", mmc->index);
1780 seq_printf(s, "sdio irq mode\t%s\n",
1781 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1782
1783 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1784 seq_printf(s, "sdio irq \t%s\n",
1785 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1786 : "disabled");
1787 }
1788 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1789
1790 pm_runtime_get_sync(host->dev);
1791 seq_puts(s, "\nregs:\n");
1792 seq_printf(s, "CON:\t\t0x%08x\n",
1793 OMAP_HSMMC_READ(host->base, CON));
1794 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1795 OMAP_HSMMC_READ(host->base, PSTATE));
1796 seq_printf(s, "HCTL:\t\t0x%08x\n",
1797 OMAP_HSMMC_READ(host->base, HCTL));
1798 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1799 OMAP_HSMMC_READ(host->base, SYSCTL));
1800 seq_printf(s, "IE:\t\t0x%08x\n",
1801 OMAP_HSMMC_READ(host->base, IE));
1802 seq_printf(s, "ISE:\t\t0x%08x\n",
1803 OMAP_HSMMC_READ(host->base, ISE));
1804 seq_printf(s, "CAPA:\t\t0x%08x\n",
1805 OMAP_HSMMC_READ(host->base, CAPA));
1806
1807 pm_runtime_mark_last_busy(host->dev);
1808 pm_runtime_put_autosuspend(host->dev);
1809
1810 return 0;
1811}
1812
1813static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1814{
1815 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1816}
1817
1818static const struct file_operations mmc_regs_fops = {
1819 .open = omap_hsmmc_regs_open,
1820 .read = seq_read,
1821 .llseek = seq_lseek,
1822 .release = single_release,
1823};
1824
1825static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1826{
1827 if (mmc->debugfs_root)
1828 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1829 mmc, &mmc_regs_fops);
1830}
1831
1832#else
1833
1834static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1835{
1836}
1837
1838#endif
1839
1840#ifdef CONFIG_OF
1841static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1842
1843 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1844};
1845
1846static const struct omap_mmc_of_data omap4_mmc_of_data = {
1847 .reg_offset = 0x100,
1848};
1849static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1850 .reg_offset = 0x100,
1851 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1852};
1853
1854static const struct of_device_id omap_mmc_of_match[] = {
1855 {
1856 .compatible = "ti,omap2-hsmmc",
1857 },
1858 {
1859 .compatible = "ti,omap3-pre-es3-hsmmc",
1860 .data = &omap3_pre_es3_mmc_of_data,
1861 },
1862 {
1863 .compatible = "ti,omap3-hsmmc",
1864 },
1865 {
1866 .compatible = "ti,omap4-hsmmc",
1867 .data = &omap4_mmc_of_data,
1868 },
1869 {
1870 .compatible = "ti,am33xx-hsmmc",
1871 .data = &am33xx_mmc_of_data,
1872 },
1873 {},
1874};
1875MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1876
1877static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1878{
1879 struct omap_hsmmc_platform_data *pdata;
1880 struct device_node *np = dev->of_node;
1881
1882 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1883 if (!pdata)
1884 return ERR_PTR(-ENOMEM);
1885
1886 if (of_find_property(np, "ti,dual-volt", NULL))
1887 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1888
1889 pdata->gpio_cd = -EINVAL;
1890 pdata->gpio_cod = -EINVAL;
1891 pdata->gpio_wp = -EINVAL;
1892
1893 if (of_find_property(np, "ti,non-removable", NULL)) {
1894 pdata->nonremovable = true;
1895 pdata->no_regulator_off_init = true;
1896 }
1897
1898 if (of_find_property(np, "ti,needs-special-reset", NULL))
1899 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1900
1901 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1902 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1903
1904 return pdata;
1905}
1906#else
1907static inline struct omap_hsmmc_platform_data
1908 *of_get_hsmmc_pdata(struct device *dev)
1909{
1910 return ERR_PTR(-EINVAL);
1911}
1912#endif
1913
1914static int omap_hsmmc_probe(struct platform_device *pdev)
1915{
1916 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1917 struct mmc_host *mmc;
1918 struct omap_hsmmc_host *host = NULL;
1919 struct resource *res;
1920 int ret, irq;
1921 const struct of_device_id *match;
1922 dma_cap_mask_t mask;
1923 unsigned tx_req, rx_req;
1924 const struct omap_mmc_of_data *data;
1925 void __iomem *base;
1926
1927 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1928 if (match) {
1929 pdata = of_get_hsmmc_pdata(&pdev->dev);
1930
1931 if (IS_ERR(pdata))
1932 return PTR_ERR(pdata);
1933
1934 if (match->data) {
1935 data = match->data;
1936 pdata->reg_offset = data->reg_offset;
1937 pdata->controller_flags |= data->controller_flags;
1938 }
1939 }
1940
1941 if (pdata == NULL) {
1942 dev_err(&pdev->dev, "Platform Data is missing\n");
1943 return -ENXIO;
1944 }
1945
1946 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1947 irq = platform_get_irq(pdev, 0);
1948 if (res == NULL || irq < 0)
1949 return -ENXIO;
1950
1951 base = devm_ioremap_resource(&pdev->dev, res);
1952 if (IS_ERR(base))
1953 return PTR_ERR(base);
1954
1955 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1956 if (!mmc) {
1957 ret = -ENOMEM;
1958 goto err;
1959 }
1960
1961 ret = mmc_of_parse(mmc);
1962 if (ret)
1963 goto err1;
1964
1965 host = mmc_priv(mmc);
1966 host->mmc = mmc;
1967 host->pdata = pdata;
1968 host->dev = &pdev->dev;
1969 host->use_dma = 1;
1970 host->dma_ch = -1;
1971 host->irq = irq;
1972 host->mapbase = res->start + pdata->reg_offset;
1973 host->base = base + pdata->reg_offset;
1974 host->power_mode = MMC_POWER_OFF;
1975 host->next_data.cookie = 1;
1976 host->pbias_enabled = 0;
1977
1978 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1979 if (ret)
1980 goto err_gpio;
1981
1982 platform_set_drvdata(pdev, host);
1983
1984 if (pdev->dev.of_node)
1985 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1986
1987 mmc->ops = &omap_hsmmc_ops;
1988
1989 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1990
1991 if (pdata->max_freq > 0)
1992 mmc->f_max = pdata->max_freq;
1993 else if (mmc->f_max == 0)
1994 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1995
1996 spin_lock_init(&host->irq_lock);
1997
1998 host->fclk = devm_clk_get(&pdev->dev, "fck");
1999 if (IS_ERR(host->fclk)) {
2000 ret = PTR_ERR(host->fclk);
2001 host->fclk = NULL;
2002 goto err1;
2003 }
2004
2005 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2006 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2007 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2008 }
2009
2010 pm_runtime_enable(host->dev);
2011 pm_runtime_get_sync(host->dev);
2012 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2013 pm_runtime_use_autosuspend(host->dev);
2014
2015 omap_hsmmc_context_save(host);
2016
2017 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2018
2019
2020
2021 if (IS_ERR(host->dbclk)) {
2022 host->dbclk = NULL;
2023 } else if (clk_prepare_enable(host->dbclk) != 0) {
2024 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2025 host->dbclk = NULL;
2026 }
2027
2028
2029
2030 mmc->max_segs = 1024;
2031
2032 mmc->max_blk_size = 512;
2033 mmc->max_blk_count = 0xFFFF;
2034 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2035 mmc->max_seg_size = mmc->max_req_size;
2036
2037 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2038 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2039
2040 mmc->caps |= mmc_pdata(host)->caps;
2041 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2042 mmc->caps |= MMC_CAP_4_BIT_DATA;
2043
2044 if (mmc_pdata(host)->nonremovable)
2045 mmc->caps |= MMC_CAP_NONREMOVABLE;
2046
2047 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2048
2049 omap_hsmmc_conf_bus_power(host);
2050
2051 if (!pdev->dev.of_node) {
2052 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2053 if (!res) {
2054 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2055 ret = -ENXIO;
2056 goto err_irq;
2057 }
2058 tx_req = res->start;
2059
2060 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2061 if (!res) {
2062 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2063 ret = -ENXIO;
2064 goto err_irq;
2065 }
2066 rx_req = res->start;
2067 }
2068
2069 dma_cap_zero(mask);
2070 dma_cap_set(DMA_SLAVE, mask);
2071
2072 host->rx_chan =
2073 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2074 &rx_req, &pdev->dev, "rx");
2075
2076 if (!host->rx_chan) {
2077 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2078 ret = -ENXIO;
2079 goto err_irq;
2080 }
2081
2082 host->tx_chan =
2083 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2084 &tx_req, &pdev->dev, "tx");
2085
2086 if (!host->tx_chan) {
2087 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2088 ret = -ENXIO;
2089 goto err_irq;
2090 }
2091
2092
2093 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2094 mmc_hostname(mmc), host);
2095 if (ret) {
2096 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2097 goto err_irq;
2098 }
2099
2100 if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2101 ret = omap_hsmmc_reg_get(host);
2102 if (ret)
2103 goto err_irq;
2104 host->use_reg = 1;
2105 }
2106
2107 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2108
2109 omap_hsmmc_disable_irq(host);
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119 ret = omap_hsmmc_configure_wake_irq(host);
2120 if (!ret)
2121 mmc->caps |= MMC_CAP_SDIO_IRQ;
2122
2123 omap_hsmmc_protect_card(host);
2124
2125 mmc_add_host(mmc);
2126
2127 if (mmc_pdata(host)->name != NULL) {
2128 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2129 if (ret < 0)
2130 goto err_slot_name;
2131 }
2132 if (host->get_cover_state) {
2133 ret = device_create_file(&mmc->class_dev,
2134 &dev_attr_cover_switch);
2135 if (ret < 0)
2136 goto err_slot_name;
2137 }
2138
2139 omap_hsmmc_debugfs(mmc);
2140 pm_runtime_mark_last_busy(host->dev);
2141 pm_runtime_put_autosuspend(host->dev);
2142
2143 return 0;
2144
2145err_slot_name:
2146 mmc_remove_host(mmc);
2147 if (host->use_reg)
2148 omap_hsmmc_reg_put(host);
2149err_irq:
2150 if (host->tx_chan)
2151 dma_release_channel(host->tx_chan);
2152 if (host->rx_chan)
2153 dma_release_channel(host->rx_chan);
2154 pm_runtime_put_sync(host->dev);
2155 pm_runtime_disable(host->dev);
2156 if (host->dbclk)
2157 clk_disable_unprepare(host->dbclk);
2158err1:
2159err_gpio:
2160 mmc_free_host(mmc);
2161err:
2162 return ret;
2163}
2164
2165static int omap_hsmmc_remove(struct platform_device *pdev)
2166{
2167 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2168
2169 pm_runtime_get_sync(host->dev);
2170 mmc_remove_host(host->mmc);
2171 if (host->use_reg)
2172 omap_hsmmc_reg_put(host);
2173
2174 if (host->tx_chan)
2175 dma_release_channel(host->tx_chan);
2176 if (host->rx_chan)
2177 dma_release_channel(host->rx_chan);
2178
2179 pm_runtime_put_sync(host->dev);
2180 pm_runtime_disable(host->dev);
2181 if (host->dbclk)
2182 clk_disable_unprepare(host->dbclk);
2183
2184 mmc_free_host(host->mmc);
2185
2186 return 0;
2187}
2188
2189#ifdef CONFIG_PM_SLEEP
2190static int omap_hsmmc_suspend(struct device *dev)
2191{
2192 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2193
2194 if (!host)
2195 return 0;
2196
2197 pm_runtime_get_sync(host->dev);
2198
2199 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2200 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2201 OMAP_HSMMC_WRITE(host->base, IE, 0);
2202 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2203 OMAP_HSMMC_WRITE(host->base, HCTL,
2204 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2205 }
2206
2207
2208 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2209 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2210 disable_irq(host->wake_irq);
2211
2212 if (host->dbclk)
2213 clk_disable_unprepare(host->dbclk);
2214
2215 pm_runtime_put_sync(host->dev);
2216 return 0;
2217}
2218
2219
2220static int omap_hsmmc_resume(struct device *dev)
2221{
2222 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2223
2224 if (!host)
2225 return 0;
2226
2227 pm_runtime_get_sync(host->dev);
2228
2229 if (host->dbclk)
2230 clk_prepare_enable(host->dbclk);
2231
2232 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2233 omap_hsmmc_conf_bus_power(host);
2234
2235 omap_hsmmc_protect_card(host);
2236
2237 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2238 !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2239 enable_irq(host->wake_irq);
2240
2241 pm_runtime_mark_last_busy(host->dev);
2242 pm_runtime_put_autosuspend(host->dev);
2243 return 0;
2244}
2245#endif
2246
2247static int omap_hsmmc_runtime_suspend(struct device *dev)
2248{
2249 struct omap_hsmmc_host *host;
2250 unsigned long flags;
2251 int ret = 0;
2252
2253 host = platform_get_drvdata(to_platform_device(dev));
2254 omap_hsmmc_context_save(host);
2255 dev_dbg(dev, "disabled\n");
2256
2257 spin_lock_irqsave(&host->irq_lock, flags);
2258 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2259 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2260
2261 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2262 OMAP_HSMMC_WRITE(host->base, IE, 0);
2263
2264 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2265
2266
2267
2268
2269
2270 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2271 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2272 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2273 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2274 pm_runtime_mark_last_busy(dev);
2275 ret = -EBUSY;
2276 goto abort;
2277 }
2278
2279 pinctrl_pm_select_idle_state(dev);
2280
2281 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2282 enable_irq(host->wake_irq);
2283 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2284 } else {
2285 pinctrl_pm_select_idle_state(dev);
2286 }
2287
2288abort:
2289 spin_unlock_irqrestore(&host->irq_lock, flags);
2290 return ret;
2291}
2292
2293static int omap_hsmmc_runtime_resume(struct device *dev)
2294{
2295 struct omap_hsmmc_host *host;
2296 unsigned long flags;
2297
2298 host = platform_get_drvdata(to_platform_device(dev));
2299 omap_hsmmc_context_restore(host);
2300 dev_dbg(dev, "enabled\n");
2301
2302 spin_lock_irqsave(&host->irq_lock, flags);
2303 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2304 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2305
2306 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2307 disable_irq_nosync(host->wake_irq);
2308 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2309 }
2310
2311 pinctrl_pm_select_default_state(host->dev);
2312
2313
2314 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2315 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2316 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2317 } else {
2318 pinctrl_pm_select_default_state(host->dev);
2319 }
2320 spin_unlock_irqrestore(&host->irq_lock, flags);
2321 return 0;
2322}
2323
2324static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2325 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2326 .runtime_suspend = omap_hsmmc_runtime_suspend,
2327 .runtime_resume = omap_hsmmc_runtime_resume,
2328};
2329
2330static struct platform_driver omap_hsmmc_driver = {
2331 .probe = omap_hsmmc_probe,
2332 .remove = omap_hsmmc_remove,
2333 .driver = {
2334 .name = DRIVER_NAME,
2335 .pm = &omap_hsmmc_dev_pm_ops,
2336 .of_match_table = of_match_ptr(omap_mmc_of_match),
2337 },
2338};
2339
2340module_platform_driver(omap_hsmmc_driver);
2341MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2342MODULE_LICENSE("GPL");
2343MODULE_ALIAS("platform:" DRIVER_NAME);
2344MODULE_AUTHOR("Texas Instruments Inc");
2345
